USART
USART definitions for the Qorvo PAC55xx series of microcontrollers. More...
Collaboration diagram for USART:
Modules | |
| Registers | |
| Interrupt Enable Register bits | |
| Interrupt ID Register bits | |
| FIFO Control Register bits | |
| Line Control Register bits | |
| Line Status Register bits | |
Macros | |
| #define | USART_TX_FIFO_DEPTH (16) |
| TX FIFO depth. More... | |
| #define | USART_RX_FIFO_DETPH (16) |
| RX FIFO depth. More... | |
| #define | USART_EFR_ENMODE BIT4 |
| Enable Enhanced Mode to use TX and RX FIFO trigger level interrupts. More... | |
Detailed Description
USART definitions for the Qorvo PAC55xx series of microcontrollers.
- Date
- 25 Feb 2020
Definitions in this file come from the PAC55XX Family User Guide Rev 1.23 by Active-Semi dated November 19, 2019. TX and RX hardware buffer sizes are both 16 bytes.
Macro Definition Documentation
◆ USART_EFR_ENMODE
| #define USART_EFR_ENMODE BIT4 |
