libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
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Macros | |
#define | USART_DATABITS_5 (0) |
LCR:WLS 5-bit character length. More... | |
#define | USART_DATABITS_6 (0x01) |
LCR:WLS 6-bit character length. More... | |
#define | USART_DATABITS_7 (0x02) |
LCR:WLS 7-bit character length. More... | |
#define | USART_DATABITS_8 (0x03) |
LCR:WLS 8-bit character length. More... | |
#define | USART_PSELPEN_ODD (0x01) |
LCR:PSEL & LCR:PEN Odd parity. More... | |
#define | USART_PSELPEN_EVEN (0x03) |
LCR:PSEL & LCR:PEN Even parity. More... | |
#define | USART_PSELPEN_FORCE1 (0x05) |
LCR:PSEL & LCR:PEN Force 1 stick parity. More... | |
#define | USART_PSELPEN_FORCE0 (0x07) |
LCR:PSEL & LCR:PEN Force 0 stick parity. More... | |
#define | USART_PARITY_DISABLE (0) |
LCR:PSEL & LCR:PEN Disable parity. More... | |
#define | USART_PARITY_ODD USART_PSELPEN_ODD |
LCR:PSEL & LCR:PEN Odd parity. More... | |
#define | USART_PARITY_EVEN USART_PSELPEN_EVEN |
LCR:PSEL & LCR:PEN Even parity. More... | |
#define | USART_PARITY_FORCE1 USART_PSELPEN_FORCE1 |
LCR:PSEL & LCR:PEN Force 1 stick parity. More... | |
#define | USART_PARITY_FORCE0 USART_PSELPEN_FORCE0 |
LCR:PSEL & LCR:PEN Force 0 stick parity. More... | |
#define | USART_STOPBITS_1 (0) |
LCR:SBS Use 1 stop bit. More... | |
#define | USART_STOPBITS_1P5 USART_LCR_SBS |
LCR:SBS Use 1.5 stop bit when databits is 5. More... | |
#define | USART_STOPBITS_2 USART_LCR_SBS |
LCR:SBS Use 2 stop bits. More... | |
#define | USART_LCR_WLS_MASK (3) |
#define | USART_LCR_WLS(wls) ((wls) & USART_LCR_WLS_MASK) |
Word length select: 5-8 databits. More... | |
#define | USART_LCR_SBS BIT2 |
Set LCR:SBS for 1.5 or 2 stop bits, Clear for 1 stop bit. More... | |
#define | USART_LCR_PEN BIT3 |
Enable parity checking. More... | |
#define | USART_LCR_PSELPEN_MASK (7) |
#define | USART_LCR_PSELPEN_SHIFT 3 |
#define | USART_LCR_PSELPEN(psel) (((psel) & USART_LCR_PSELPEN_MASK) << USART_LCR_PSELPEN_SHIFT) |
LCR:PSEL and LCR:PEN control parity. More... | |
#define | USART_LCR_BCON BIT6 |
Break Control: Enabling this bit forces TX to logic 0. More... | |
#define USART_DATABITS_5 (0) |
#define USART_DATABITS_6 (0x01) |
#define USART_DATABITS_7 (0x02) |
#define USART_DATABITS_8 (0x03) |
#define USART_LCR_BCON BIT6 |
#define USART_LCR_PSELPEN | ( | psel | ) | (((psel) & USART_LCR_PSELPEN_MASK) << USART_LCR_PSELPEN_SHIFT) |
#define USART_LCR_SBS BIT2 |
#define USART_LCR_WLS | ( | wls | ) | ((wls) & USART_LCR_WLS_MASK) |
#define USART_PARITY_DISABLE (0) |
#define USART_PARITY_EVEN USART_PSELPEN_EVEN |
#define USART_PARITY_FORCE0 USART_PSELPEN_FORCE0 |
#define USART_PARITY_FORCE1 USART_PSELPEN_FORCE1 |
#define USART_PARITY_ODD USART_PSELPEN_ODD |
#define USART_PSELPEN_EVEN (0x03) |
#define USART_PSELPEN_FORCE0 (0x07) |
#define USART_PSELPEN_FORCE1 (0x05) |
#define USART_PSELPEN_ODD (0x01) |
#define USART_STOPBITS_1P5 USART_LCR_SBS |
#define USART_STOPBITS_2 USART_LCR_SBS |