Line Status Register bits
Collaboration diagram for Line Status Register bits:
Macros | |
| #define | USART_LSR_RDR BIT0 |
| Receiver Data Ready. More... | |
| #define | USART_LSR_OE BIT1 |
| Overrun Error. More... | |
| #define | USART_LSR_PE BIT2 |
| Parity Error. More... | |
| #define | USART_LSR_FE BIT3 |
| Framing Error. More... | |
| #define | USART_LSR_BI BIT4 |
| Break Interrupt. More... | |
| #define | USART_LSR_THRE BIT5 |
| Transmitter Holding Register Empty. More... | |
| #define | USART_LSR_TEMT BIT6 |
| Transmitter Empty. More... | |
| #define | USART_LSR_RXFE BIT7 |
| Error in RX FIFO. More... | |
