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libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
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CAN Interrupt Status Register bit definitions. More...

Macros | |
| #define | CAN_ISR_DOI BIT24 |
| DOI: Data Overflow Interrupt. More... | |
| #define | CAN_ISR_BEI BIT25 |
| BEI: Bus Error Interrupt. More... | |
| #define | CAN_ISR_TI BIT26 |
| TI: Transmit Interrupt. More... | |
| #define | CAN_ISR_RI BIT27 |
| RI: Receive Interrupt. More... | |
| #define | CAN_ISR_EPI BIT28 |
| EPI: Error Passive Interrupt. More... | |
| #define | CAN_ISR_EWI BIT29 |
| EWI: Error Warning Interrupt. More... | |
| #define | CAN_ISR_ALI BIT30 |
| ALI: Arbitration Lost Interrupt. More... | |
| #define | CAN_ISR_ACKNOWLEDGE(can_base, isr) CAN_ISR_SR_CMR_MR_SET(can_base, ((isr) & 0x7F000000)) |
| This is a helper to acknowledge an ISR. More... | |
CAN Interrupt Status Register bit definitions.
| #define CAN_ISR_ACKNOWLEDGE | ( | can_base, | |
| isr | |||
| ) | CAN_ISR_SR_CMR_MR_SET(can_base, ((isr) & 0x7F000000)) |