| ▼CM3 Defines | Defined Constants and Types for Cortex M3 core features |
| Debugging | Macros and functions to aid in debugging |
| ►Cortex Core Defines | libopencm3 Defined Constants and Types for the Cortex Core |
| Cortex Core Atomic support Defines | Atomic operation support |
| Cortex-M Data Watch and Trace unit. | System Control Space (SCS) => Data Watchpoint and Trace (DWT) |
| Cortex-M Flash Patch and Breakpoint (FPB) unit | |
| Cortex-M Instrumentation Trace Macrocell (ITM) | |
| ►Cortex-M MPU Defines | libopencm3 Cortex Memory Protection Unit |
| MPU Registers | |
| MPU TYPE register fields | The MPU_TYPE register is always available, even if the MPU is not implemented |
| MPU CTRL register fields | Defines for the Control Register |
| MPU RNR register fields | Defines for the Region Number Register |
| MPU RBAR register fields | Defines for the Region Base Address Register |
| ►MPU RASR register fields | Defines for the Region Attribute and Size Register |
| MPU RASR Attributes | Not all attributes are available on v6m |
| ►Cortex-M NVIC Defines | libopencm3 Cortex Nested Vectored Interrupt Controller |
| NVIC Registers | |
| Cortex M0/M3/M4 System Interrupts | IRQ numbers -3 and -6 to -9 are reserved |
| User interrupts for STM32 G4 series | |
| ►Cortex-M System Control Block | The System Control Block is a section of the System Control Space |
| SCB Registers | |
| SCB_CPUID Values | |
| SCB_ICSR Values | |
| SCB_VTOR Values | |
| SCB_AICR Values | |
| SCB_SCR Values | |
| SCB_CCR Values | |
| ►Cortex-M System Control Space | The System Control Space (SCS) is a memory-mapped 4KB address space that provides 32-bit registers for configuration, status reporting and control |
| SCS Registers | |
| ►Cortex-M SysTick Defines | libopencm3 Defined Constants and Types for the Cortex SysTick |
| ►STK_CSR Values | |
| Clock source selection | |
| STK_RVR Values | |
| STK_CALIB Values | |
| Cortex-M Trace Port Interface Unit (TPIU) | |
| ▼Cortex Core Peripheral APIs | APIs for Cortex Core peripherals |
| DWT | libopencm3 Cortex-M Data Watchpoint and Trace unit |
| NVIC | libopencm3 Cortex Nested Vectored Interrupt Controller |
| SCB | libopencm3 Cortex-M System Control Block |
| SysTick | libopencm3 Cortex System Tick Timer |
| Coresight Registers | CoreSight Lock Status Registers and Lock Access Registers are documented for the DWT, ITM, FPB and TPIU peripherals |
| ▼Peripheral APIs | APIs for device peripherals |
| QuadSPI peripheral API | APIs for the specialized SPI Flash peripheral |
| DMA peripheral API | DMA library for the multi channel controller found in F0/1/3 & L/G parts |
| FLASH peripheral API | libopencm3 STM32G4xx FLASH |
| PWR peripheral API | libopencm3 STM32G4xx Power Control |
| RCC peripheral API | libopencm3 STM32G4xx Reset and Clock Control |
| ADC peripheral API | libopencm3 STM32G4xx ADC |
| CORDIC peripheral API | HW accelerated maths trig/hyperbolic operations |
| CRC peripheral API | |
| CRS peripheral API | (USB) STM32 Clock Recovery Subsystem |
| DAC peripheral API | Digital to Analog Converter |
| DMAMUX peripheral API | |
| GPIO peripheral API | |
| I2C peripheral API | |
| OPAMP peripheral API | |
| RNG peripheral API | This library supports "version 1" of the random number generator peripheral (RNG) in the STM32 series of ARM Cortex Microcontrollers by ST Microelectronics |
| SPI peripheral API | |
| TIMER peripheral API | |
| USART peripheral API | |
| FDCAN peripheral API | libopencm3 STM32 FDCAN |
| STM32G4xx | Libraries for ST Microelectronics STM32G4xx series |
| ▼STM32G4xx Defines | Defined Constants and Types for the STM32G4xx series |
| ►ADC Defines | Defined Constants and Types for the STM32G4xx Analog to Digital converter |
| ADC register base addresses | |
| ADC Sample Time Selection values | |
| ADC Multi mode selection | |
| ADC Channel Numbers | |
| ADC registers | |
| ISR ADC interrupt status register | |
| IER ADC interrupt enable register | |
| CR ADC control register | |
| ►CFGR1 ADC configuration register 1 | |
| EXTEN: External trigger enable and polarity selection for regular channels | |
| RES: Data resolution | |
| SMPR ADC sample time register | |
| CFGR2 ADC configuration register 2 | |
| TR1 ADC watchdog threshold register 1 | |
| ►CCR ADC common configuration register | |
| ADC clock prescaler | |
| ►CORDIC Defines | Defined Constants and Types for the STM32G4xx CORDIC |
| CORDIC registers | |
| ►CSR CORDIC control/status register | |
| SCALE: Scaling factor | |
| PRECISION: Precision of CORDIC operation (number of iterations) | |
| FUNCTION: CORDIC operation to be performed | |
| ►CRC Defines | Defined Constants and Types for the STM32G4xx CRC Generator |
| CRC Registers | |
| ►CRC_CR values | |
| CRC Reverse input options | |
| CRC Polynomial size | |
| CRS Defines | Defined Constants and Types for the Clock Recovery System |
| ►DAC Defines | Defined Constants and Types for the STM32G4xx DAC |
| DAC register base addresses | |
| DAC Registers | |
| ►DAC_CR values | |
| DAC Channel 2 Trigger Source Selection | |
| DAC Channel 1 Trigger Source Selection | |
| DAC_SWTRIGR Values | |
| DAC_DHRxxx Values | |
| DAC_DORx Values | |
| DAC_SR Values | |
| DAC Channel Identifier | |
| DAC_CCR values | |
| ►DAC_MCR values | |
| DAC Channel 2 Mode Selection | |
| High frequency interface mode selection | |
| DAC Channel 1 Mode Selection | |
| DAC Channel 1 Sawtooth Direction Setting | |
| DAC Channel 2 Sawtooth Direction Setting | |
| DAC Channel 2 Sawtooth Increment Trigger | |
| DAC Channel 2 Sawtooth Reset Trigger | |
| DAC Channel 1 Sawtooth Increment Trigger | |
| DAC Channel 1 Sawtooth Reset Trigger | |
| ►DMA Defines | Defined Constants and Types for the STM32G4xx DMA Controller |
| DMA Interrupt Flag Offsets within channel flag | Group |
| DMA Channel Priority Levels | |
| DMA Channel Memory Word Width | |
| DMA Channel Peripheral Word Width | |
| DMA Channel Number | |
| ►DMAMUX Defines | Defined Constants and Types for the STM32G4xx DMAMUX |
| DMAMUX register base addresses | |
| SYNCID Synchronization input selected | |
| DMAREQID DMA request line selected | |
| SIGID DMA request trigger input selected | |
| ►CxCR DMA request line multiplexer channel x control register | |
| SPOL Event Polarity | Synchronization event type selector |
| CSR request line multiplexer interrupt channel status register | |
| CFR request line multiplexer interrupt clear flag register | |
| ►RGxCR DMA request generator channel x control register | |
| GPOL Event Polarity | DMA request generator trigger event type selection |
| RGSR DMA request generator interrupt status register | |
| RGCFR DMA request generator clear flag register | |
| DMAMUX Request Generator Channel Number | |
| ►FDCAN Defines | |
| FDCAN block base addresses | |
| Named constants for FIFOs | |
| registers file in each FDCAN block. | |
| FDCAN CC control register bits | |
| FDCAN interrupt register flags | |
| FDCAN interrupt enable flags | |
| FDCAN_ILS interrupt line select flags | |
| FDCAN_TXBRP Transmit request pending bits | |
| FDCAN_TXBAR Transmit buffer add request bits | |
| FDCAN_TXBCR Transmit buffer cancel request bits | |
| FDCAN_TXBTO Transmit buffer transfer occured bits | |
| FDCAN_TXBCF Transmit buffer cancellation finished bits | |
| FDCAN_TXBTIE Transmit interrupt enable bits | Each bit enables or disables transmit interrupt for transmit buffer slot |
| FDCAN_TXBCIE Transmit cancelled interrupt enable bits | Each bit enables or disables transmit cancelled interrupt for transmit buffer slot |
| Standard ID filter match type | Matching strategy for standard ID filters |
| Standard ID filter action | Defines possible actions for standard ID filters |
| Extended ID filter action | These are possible actions, extended filter can have |
| Extended ID filter match type | Matching strategy for extended ID filters |
| FIFO / buffer flags | |
| FDCAN error return values | |
| ►FLASH Defines | Defined Constants and Types for the STM32G4xx Flash Control |
| Flash_acr_values | |
| ►GPIO Defines | Defined Constants and Types for the STM32G4xx General Purpose I/O |
| GPIO Output Pin Speed | |
| GPIO Pin Identifiers | |
| GPIO Port IDs | |
| GPIO Pin Direction and Analog/Digital Mode | |
| GPIO Output Pin Driver Type | |
| GPIO Output Pin Pullup | |
| Alternate Function Pin Selection | |
| ►I2C Defines | Defined Constants and Types for the STM32G4xx I2C |
| I2C register base address | |
| OPAMP Defines | libopencm3 Defined Constants and Types for the STM32G4xx Operational Amplifier module |
| ►PWR Defines | Defined Constants and Types for the STM32G4xx Power Control |
| PVD level selection | |
| ►QuadSPI Defines | Defined constants and types for the STM32G4 QuadSPI peripheral |
| QuadSPI Registers | |
| ►RCC Defines | Defined Constants and Types for the STM32G4xx Reset and Clock Control |
| RCC Registers | |
| RCC_CR values | |
| RCC_ICSCR values | |
| ►RCC_CFGR values | |
| MCOPRE MCO prescaler | |
| MCO: Microcontroller clock output | |
| PPREx: APBx prescaler | |
| HPRE: AHB prescaler | |
| SW/SWS System clock switch (status) | |
| ►RCC_PLLCFGR - PLL Configuration Register | |
| RCC_PLLCFGR PLLR values | Set these bits correctly not to exceed 170 MHz on this domain |
| RCC_PLLCFGR PLLN values | Allowed values 8 <= n <= 127, VCO output limits specified in datasheet |
| RCC_PLLCFGR PLLM values | Allowed values 1 <= m <= 16, VCO input limits specified in datasheet |
| RCC_CIER - Clock interrupt enable register | |
| RCC_CIFR - Clock interrupt flag register | |
| RCC_CICR - Clock interrupt clear register | |
| ►RCC_AHBxRSTR reset values (full set) | |
| RCC_AHB1RSTR reset values | |
| RCC_AHB2RSTR reset values | |
| RCC_AHB3RSTR reset values | |
| ►RCC_APB1RSTRx reset values (full set) | |
| RCC_APB1RSTR1 reset values | |
| RCC_APB1RSTR2 reset values | |
| RCC_APB2RSTR reset values | |
| ►RCC_AHBxENR enable values (full set) | |
| RCC_AHB1ENR enable values | |
| RCC_AHB2ENR enable values | |
| RCC_AHB3ENR enable values | |
| ►RCC_APB1ENRx enable values (full set) | |
| RCC_APB1ENR1 enable values | |
| RCC_APB1ENR2 enable values | |
| RCC_APB2ENR enable values | |
| RCC_AHB1SMENR - AHB1 periph clock in sleep mode | |
| RCC_AHB2SMENR - AHB2 periph clock in sleep mode | |
| RCC_AHB3SMENR - AHB3 periph clock in sleep mode | |
| RCC_APB1SMENR1 - APB1 periph clock in sleep mode | |
| RCC_APB1SMENR2 - APB1 periph clock in sleep mode | |
| RCC_APB2SMENR - APB2 periph clock in sleep mode | |
| RCC_CCIPR - Peripherals independent clock config register | |
| RCC_BDCR - Backup domain control register | |
| RCC_CSR - Control/Status register | |
| RCC_CRRCR Clock Recovery RC register | |
| RNG Defines | Defined Constants and Types for the STM32G4xx RNG Control |
| ►SPI Defines | Defined Constants and Types for the STM32G4xx SPI |
| SPI Register base address | |
| SPI lsb/msb first | |
| SPI peripheral baud rates | |
| SPI peripheral baud rate prescale values | |
| SPI clock polarity | |
| SPI clock phase | |
| SPI crc length | |
| SPI data size | |
| ►SYSCFG Defines | Defined Constants and Types for the STM32G4xx Sysconfig |
| SYSCFG registers | |
| ►Timer Defines | Defined Constants and Types for the STM32G4xx Timers |
| Timer register base addresses | |
| TIMx_CR1 CKD[1:0] Clock Division Ratio | |
| TIMx_CR1 CMS[1:0]: Center-aligned Mode Selection | |
| TIMx_CR1 DIR: Direction | |
| TIMx_CR2_OIS: Force Output Idle State Control Values | |
| TIMx_CR2 MMS[6:4]: Master Mode Selection | |
| TIMx_SMCR TS Trigger selection | |
| TIMx_SMCR SMS Slave mode selection | |
| TIMx_DIER Timer DMA and Interrupt Enable Values | |
| TIMx_SR Timer Status Register Flags | |
| TIMx_EGR Timer Event Generator Values | |
| TIM_BDTR_LOCK Timer Lock Values | |
| TIM2_OR Timer 2 Option Register Internal | Trigger 1 Remap |
| TIM5_OR Timer 5 Option Register Internal Trigger 4 Remap | Only available in F2 and F4 series |
| ►USART Defines | Defined Constants and Types for the STM32G4xx USART |
| USART register base addresses | Holds all the U(S)ART peripherals supported |
| USART Parity Selection | |
| USART Tx/Rx Mode Selection | |
| USART Stop Bit Selection | |
| USART Hardware Flow Control Selection | |
| USART Registers | |
| U(S)ART convenience Flags | We define the "common" lower flag bits using a standard name, allowing them to be used regardless of which usart peripheral version you have |
| USART_CR1 Values | |
| ►USART_CR2 Values | |
| Auto baud rate mode | ABRMOD[1:0]: Auto baud rate mode |
| USART_CR3 Values | |
| USART_GTPR Values | |
| USART_RTOR Values | |
| USART_RQR Values | |
| USART_ISR Values | |
| USART_ICR Values | |
| USART_RDR/TDR Values | |
| User interrupt service routines (ISR) prototypes for STM32 G4 series | |
| USB Defines | Defined Constants and Types for the STM32F* USB drivers |
| USB Audio Type Definitions | Defined Constants and Types for the USB Audio Type Definitions |
| USB CDC Type Definitions | Defined Constants and Types for the USB CDC Type Definitions |
| USB HID Type Definitions | Defined Constants and Types for the USB HID Type Definitions |
| USB MSC Type Definitions | Defined Constants and Types for the USB MSC Type Definitions |
| USB Drivers | Defined Constants and Types for the USB Drivers |
| USB Standard Structure Definitions | Defined Constants and Types for the USB Standard Structure Definitions |
| User interrupt service routines (ISR) defaults for STM32 G4 series | |
| Generic USB Drivers | Generic USB Drivers |
| Generic USB Control Requests | Generic USB Control Requests |
| Generic USB Standard Request Interface | Generic USB Standard Request Interface |
| Usb_msc | |
1.9.4