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#define | FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) |
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#define | FLASH_PDKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) |
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#define | FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) |
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#define | FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) |
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#define | FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) |
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#define | FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) |
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#define | FLASH_ECCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18) |
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#define | FLASH_OPTR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) |
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#define | FLASH_PCROP1SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x24) |
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#define | FLASH_PCROP1ER MMIO32(FLASH_MEM_INTERFACE_BASE + 0x28) |
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#define | FLASH_WRP1AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x2C) |
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#define | FLASH_WRP1BR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x30) |
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#define | FLASH_PCROP2SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x44) |
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#define | FLASH_PCROP2ER MMIO32(FLASH_MEM_INTERFACE_BASE + 0x48) |
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#define | FLASH_WRP2AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x4C) |
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#define | FLASH_WRP2BR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x50) |
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#define | FLASH_SEC1R MMIO32(FLASH_MEM_INTERFACE_BASE + 0x70) |
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#define | FLASH_SEC2R MMIO32(FLASH_MEM_INTERFACE_BASE + 0x74) |
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#define | FLASH_ACR_DBG_SWEN (1 << 18) |
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#define | FLASH_ACR_SLEEP_PD (1 << 14) |
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#define | FLASH_ACR_RUN_PD (1 << 13) |
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#define | FLASH_ACR_PRFTEN (1 << 8) |
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#define | FLASH_ACR_LATENCY_SHIFT 0 |
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#define | FLASH_ACR_LATENCY_MASK 0xf |
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#define | FLASH_SR_BSY (1 << 16) |
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#define | FLASH_SR_OPTVERR (1 << 15) |
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#define | FLASH_SR_RDERR (1 << 14) |
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#define | FLASH_SR_FASTERR (1 << 9) |
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#define | FLASH_SR_MISERR (1 << 8) |
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#define | FLASH_SR_PGSERR (1 << 7) |
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#define | FLASH_SR_SIZERR (1 << 6) |
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#define | FLASH_SR_PGAERR (1 << 5) |
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#define | FLASH_SR_WRPERR (1 << 4) |
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#define | FLASH_SR_PROGERR (1 << 3) |
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#define | FLASH_SR_OPERR (1 << 1) |
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#define | FLASH_SR_EOP (1 << 0) |
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#define | FLASH_CR_LOCK (1 << 31) |
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#define | FLASH_CR_OPTLOCK (1 << 30) |
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#define | FLASH_CR_SEC_PROT2 (1 << 29) |
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#define | FLASH_CR_SEC_PROT1 (1 << 28) |
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#define | FLASH_CR_OBL_LAUNCH (1 << 27) |
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#define | FLASH_CR_RDERRIE (1 << 26) |
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#define | FLASH_CR_ERRIE (1 << 25) |
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#define | FLASH_CR_EOPIE (1 << 24) |
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#define | FLASH_CR_FSTPG (1 << 18) |
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#define | FLASH_CR_OPTSTRT (1 << 17) |
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#define | FLASH_CR_START (1 << 16) |
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#define | FLASH_CR_MER2 (1 << 15) |
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#define | FLASH_CR_BKER (1 << 11) |
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#define | FLASH_CR_MER1 (1 << 2) |
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#define | FLASH_CR_PER (1 << 1) |
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#define | FLASH_CR_PG (1 << 0) |
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#define | FLASH_CR_PNB_SHIFT 3 |
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#define | FLASH_CR_PNB_MASK 0x7f |
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#define | FLASH_ECCR_ECCD (1 << 31) |
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#define | FLASH_ECCR_ECCC (1 << 30) |
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#define | FLASH_ECCR_ECCD2 (1 << 31) |
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#define | FLASH_ECCR_ECCC2 (1 << 30) |
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#define | FLASH_ECCR_ECCIE (1 << 24) |
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#define | FLASH_ECCR_SYSF_ECC (1 << 22) |
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#define | FLASH_ECCR_BK_ECC (1 << 21) |
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#define | FLASH_ECCR_ADDR_ECC_SHIFT 0 |
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#define | FLASH_ECCR_ADDR_ECC_MASK 0x7ffff |
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#define | FLASH_OPTR_IRHEN (1 << 30) |
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#define | FLASH_OPTR_NRST_MODE_SHIFT 28 |
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#define | FLASH_OPTR_NRST_MODE_MASK 0x3 |
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#define | FLASH_OPTR_NRST_MODE_RESET 1 |
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#define | FLASH_OPTR_NRST_MODE_GPIO 2 |
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#define | FLASH_OPTR_NRST_MODE_BIDIR 3 |
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#define | FLASH_OPTR_nBOOT0 (1 << 27) |
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#define | FLASH_OPTR_nSWBOOT0 (1 << 26) |
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#define | FLASH_OPTR_SRAM_RST (1 << 25) |
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#define | FLASH_OPTR_SRAM_PE (1 << 24) |
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#define | FLASH_OPTR_nBOOT1 (1 << 23) |
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#define | FLASH_OPTR_DUALBANK (1 << 21) |
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#define | FLASH_OPTR_BFB2 (1 << 20) |
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#define | FLASH_OPTR_WWDG_SW (1 << 19) |
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#define | FLASH_OPTR_IWDG_STDBY (1 << 18) |
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#define | FLASH_OPTR_IWDG_STOP (1 << 17) |
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#define | FLASH_OPTR_IDWG_SW (1 << 16) |
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#define | FLASH_OPTR_nRST_SHDW (1 << 14) |
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#define | FLASH_OPTR_nRST_STDBY (1 << 13) |
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#define | FLASH_OPTR_nRST_STOP (1 << 12) |
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#define | FLASH_OPTR_BOR_SHIFT 8 |
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#define | FLASH_OPTR_BOR_MASK 0x7 |
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#define | FLASH_OPTR_BOR_LEVEL_0 0 |
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#define | FLASH_OPTR_BOR_LEVEL_1 1 |
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#define | FLASH_OPTR_BOR_LEVEL_2 2 |
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#define | FLASH_OPTR_BOR_LEVEL_3 3 |
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#define | FLASH_OPTR_BOR_LEVEL_4 4 |
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#define | FLASH_OPTR_RDP_SHIFT 0 |
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#define | FLASH_OPTR_RDP_MASK 0xff |
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#define | FLASH_OPTR_RDP_LEVEL_0 0xAA |
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#define | FLASH_OPTR_RDP_LEVEL_1 0xBB |
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#define | FLASH_OPTR_RDP_LEVEL_2 0xCC |
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#define | FLASH_PCROP1SR_PCROP1_STRT_SHIFT 0 |
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#define | FLASH_PCROP1SR_PCROP1_STRT_MASK 0x7fff |
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#define | FLASH_PCROP1ER_PCROP_RDP (1 << 31) |
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#define | FLASH_PCROP1ER_PCROP1_END_SHIFT 0 |
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#define | FLASH_PCROP1ER_PCROP1_END_MASK 0x7fff |
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#define | FLASH_WRP1AR_WRP1A_END_SHIFT 16 |
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#define | FLASH_WRP1AR_WRP1A_END_MASK 0x7f |
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#define | FLASH_WRP1AR_WRP1A_STRT_SHIFT 0 |
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#define | FLASH_WRP1AR_WRP1A_STRT_MASK 0x7f |
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#define | FLASH_WRP1BR_WRP1B_END_SHIFT 16 |
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#define | FLASH_WRP1BR_WRP1B_END_MASK 0x7f |
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#define | FLASH_WRP1BR_WRP1B_STRT_SHIFT 0 |
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#define | FLASH_WRP1BR_WRP1B_STRT_MASK 0x7f |
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#define | FLASH_PCROP2SR_PCROP2_STRT_SHIFT 0 |
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#define | FLASH_PCROP2SR_PCROP2_STRT_MASK 0x7fff |
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#define | FLASH_PCROP2ER_PCROP2_END_SHIFT 0 |
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#define | FLASH_PCROP2ER_PCROP2_END_MASK 0x7fff |
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#define | FLASH_WRP2AR_WRP2A_END_SHIFT 16 |
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#define | FLASH_WRP2AR_WRP2A_END_MASK 0x7f |
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#define | FLASH_WRP2AR_WRP2A_STRT_SHIFT 0 |
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#define | FLASH_WRP2AR_WRP2A_STRT_MASK 0x7f |
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#define | FLASH_WRP2BR_WRP2B_END_SHIFT 16 |
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#define | FLASH_WRP2BR_WRP2B_END_MASK 0xff |
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#define | FLASH_WRP2BR_WRP2B_STRT_SHIFT 0 |
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#define | FLASH_WRP2BR_WRP2B_STRT_MASK 0xff |
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#define | FLASH_SEC1R_BOOT_LOCK (1 << 16) |
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#define | FLASH_SEC1R_SEC_SIZE1_SHIFT 0 |
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#define | FLASH_SEC1R_SEC_SIZE1_MASK 0xff |
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#define | FLASH_SEC2R_SEC_SIZE2_SHIFT 0 |
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#define | FLASH_SEC2R_SEC_SIZE2_MASK 0xff |
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#define | FLASH_PDKEYR_PDKEY1 ((uint32_t)0x04152637) |
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#define | FLASH_PDKEYR_PDKEY2 ((uint32_t)0xfafbfcfd) |
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#define | FLASH_KEYR_KEY1 ((uint32_t)0x45670123) |
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#define | FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab) |
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#define | FLASH_OPTKEYR_KEY1 ((uint32_t)0x08192a3b) |
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#define | FLASH_OPTKEYR_KEY2 ((uint32_t)0x4c5d6e7f) |
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