#include <libopencm3/cm3/memorymap.h>
Go to the source code of this file.
Macro Definition Documentation
◆ ADC1_BASE
| #define ADC1_BASE (PERIPH_BASE_AHB2 + 0x0000) |
Definition at line 109 of file stm32/g4/memorymap.h.
◆ ADC2_BASE
| #define ADC2_BASE (ADC1_BASE + 0x0100) |
Definition at line 110 of file stm32/g4/memorymap.h.
◆ ADC3_BASE
| #define ADC3_BASE (PERIPH_BASE_AHB2 + 0x0400) |
Definition at line 111 of file stm32/g4/memorymap.h.
◆ ADC4_BASE
| #define ADC4_BASE (ADC3_BASE + 0x0100) |
Definition at line 112 of file stm32/g4/memorymap.h.
◆ ADC5_BASE
| #define ADC5_BASE (ADC3_BASE + 0x0200) |
Definition at line 113 of file stm32/g4/memorymap.h.
◆ AES_BASE
| #define AES_BASE (PERIPH_BASE_AHB2 + 0x60000) |
Definition at line 118 of file stm32/g4/memorymap.h.
◆ COMP_BASE
| #define COMP_BASE (PERIPH_BASE_APB2 + 0x0200) |
Definition at line 74 of file stm32/g4/memorymap.h.
◆ CORDIC_BASE
| #define CORDIC_BASE (PERIPH_BASE_AHB1 + 0x0c00) |
Definition at line 93 of file stm32/g4/memorymap.h.
◆ CRC_BASE
| #define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) |
Definition at line 97 of file stm32/g4/memorymap.h.
◆ CRS_BASE
| #define CRS_BASE (PERIPH_BASE_APB1 + 0x2000) |
Definition at line 43 of file stm32/g4/memorymap.h.
◆ DAC1_BASE
| #define DAC1_BASE (PERIPH_BASE_AHB2 + 0x0800) |
Definition at line 114 of file stm32/g4/memorymap.h.
◆ DAC2_BASE
| #define DAC2_BASE (PERIPH_BASE_AHB2 + 0x0c00) |
Definition at line 115 of file stm32/g4/memorymap.h.
◆ DAC3_BASE
| #define DAC3_BASE (PERIPH_BASE_AHB2 + 0x1000) |
Definition at line 116 of file stm32/g4/memorymap.h.
◆ DAC4_BASE
| #define DAC4_BASE (PERIPH_BASE_AHB2 + 0x1400) |
Definition at line 117 of file stm32/g4/memorymap.h.
◆ DBGMCU_BASE
| #define DBGMCU_BASE (PPBI_BASE + 0x42000) |
Definition at line 125 of file stm32/g4/memorymap.h.
◆ DESIG_FLASH_SIZE_BASE
| #define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0) |
Definition at line 128 of file stm32/g4/memorymap.h.
◆ DESIG_PACKAGE
Definition at line 133 of file stm32/g4/memorymap.h.
◆ DESIG_UNIQUE_ID0
| #define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) |
Definition at line 130 of file stm32/g4/memorymap.h.
◆ DESIG_UNIQUE_ID1
| #define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) |
Definition at line 131 of file stm32/g4/memorymap.h.
◆ DESIG_UNIQUE_ID2
| #define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8) |
Definition at line 132 of file stm32/g4/memorymap.h.
◆ DESIG_UNIQUE_ID_BASE
| #define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590) |
Definition at line 129 of file stm32/g4/memorymap.h.
◆ DMA1_BASE
| #define DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000) |
Definition at line 90 of file stm32/g4/memorymap.h.
◆ DMA2_BASE
| #define DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400) |
Definition at line 91 of file stm32/g4/memorymap.h.
◆ DMAMUX_BASE
| #define DMAMUX_BASE (PERIPH_BASE_AHB1 + 0x0800) |
Definition at line 92 of file stm32/g4/memorymap.h.
◆ EXTI_BASE
| #define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) |
Definition at line 76 of file stm32/g4/memorymap.h.
◆ FDCAN1_BASE
| #define FDCAN1_BASE (PERIPH_BASE_APB1 + 0x6400) |
Definition at line 58 of file stm32/g4/memorymap.h.
◆ FDCAN1_RAM_BASE
| #define FDCAN1_RAM_BASE (PERIPH_BASE_APB1 + 0xA400) |
Definition at line 67 of file stm32/g4/memorymap.h.
◆ FDCAN2_BASE
| #define FDCAN2_BASE (PERIPH_BASE_APB1 + 0x6800) |
Definition at line 59 of file stm32/g4/memorymap.h.
◆ FDCAN2_RAM_BASE
| #define FDCAN2_RAM_BASE (PERIPH_BASE_APB1 + 0xA800) |
Definition at line 68 of file stm32/g4/memorymap.h.
◆ FDCAN3_BASE
| #define FDCAN3_BASE (PERIPH_BASE_APB1 + 0x6c00) |
Definition at line 60 of file stm32/g4/memorymap.h.
◆ FDCAN3_RAM_BASE
| #define FDCAN3_RAM_BASE (PERIPH_BASE_APB1 + 0xAc00) |
Definition at line 69 of file stm32/g4/memorymap.h.
◆ FLASH_BASE
| #define FLASH_BASE (0x08000000U) |
Definition at line 23 of file stm32/g4/memorymap.h.
◆ FLASH_MEM_INTERFACE_BASE
| #define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000) |
Definition at line 96 of file stm32/g4/memorymap.h.
◆ FMAC_BASE
| #define FMAC_BASE (PERIPH_BASE_AHB1 + 0x1400) |
Definition at line 95 of file stm32/g4/memorymap.h.
◆ FMC1_BANK_BASE
| #define FMC1_BANK_BASE (0x60000000U) |
Definition at line 31 of file stm32/g4/memorymap.h.
◆ FMC3_BANK_BASE
| #define FMC3_BANK_BASE (0x80000000U) |
Definition at line 32 of file stm32/g4/memorymap.h.
◆ FMC_BASE
| #define FMC_BASE (0xa0000000U) |
Definition at line 121 of file stm32/g4/memorymap.h.
◆ GPIO_PORT_A_BASE
| #define GPIO_PORT_A_BASE (PERIPH_BASE_IOPORT + 0x0000) |
Definition at line 100 of file stm32/g4/memorymap.h.
◆ GPIO_PORT_B_BASE
| #define GPIO_PORT_B_BASE (PERIPH_BASE_IOPORT + 0x0400) |
Definition at line 101 of file stm32/g4/memorymap.h.
◆ GPIO_PORT_C_BASE
| #define GPIO_PORT_C_BASE (PERIPH_BASE_IOPORT + 0x0800) |
Definition at line 102 of file stm32/g4/memorymap.h.
◆ GPIO_PORT_D_BASE
| #define GPIO_PORT_D_BASE (PERIPH_BASE_IOPORT + 0x0c00) |
Definition at line 103 of file stm32/g4/memorymap.h.
◆ GPIO_PORT_E_BASE
| #define GPIO_PORT_E_BASE (PERIPH_BASE_IOPORT + 0x1000) |
Definition at line 104 of file stm32/g4/memorymap.h.
◆ GPIO_PORT_F_BASE
| #define GPIO_PORT_F_BASE (PERIPH_BASE_IOPORT + 0x1400) |
Definition at line 105 of file stm32/g4/memorymap.h.
◆ GPIO_PORT_G_BASE
| #define GPIO_PORT_G_BASE (PERIPH_BASE_IOPORT + 0x1800) |
Definition at line 106 of file stm32/g4/memorymap.h.
◆ HRTIM_BASE
| #define HRTIM_BASE (PERIPH_BASE_APB2 + 0x6800) |
Definition at line 87 of file stm32/g4/memorymap.h.
◆ I2C1_BASE
| #define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) |
Definition at line 54 of file stm32/g4/memorymap.h.
◆ I2C2_BASE
| #define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) |
Definition at line 55 of file stm32/g4/memorymap.h.
◆ I2C3_BASE
| #define I2C3_BASE (PERIPH_BASE_APB1 + 0x7800) |
Definition at line 62 of file stm32/g4/memorymap.h.
◆ I2C4_BASE
| #define I2C4_BASE (PERIPH_BASE_APB1 + 0x8400) |
Definition at line 65 of file stm32/g4/memorymap.h.
◆ INFO_BASE
| #define INFO_BASE (0x1fff0000U) |
Definition at line 25 of file stm32/g4/memorymap.h.
◆ IWDG_BASE
| #define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) |
Definition at line 47 of file stm32/g4/memorymap.h.
◆ LPTIM1_BASE
| #define LPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00) |
Definition at line 63 of file stm32/g4/memorymap.h.
◆ LPUART1_BASE
| #define LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000) |
Definition at line 64 of file stm32/g4/memorymap.h.
◆ OPAMP_BASE
| #define OPAMP_BASE (PERIPH_BASE_APB2 + 0x0300) |
Definition at line 75 of file stm32/g4/memorymap.h.
◆ PERIPH_BASE
| #define PERIPH_BASE (0x40000000U) |
Definition at line 24 of file stm32/g4/memorymap.h.
◆ PERIPH_BASE_AHB1
| #define PERIPH_BASE_AHB1 (0x40020000U) |
Definition at line 28 of file stm32/g4/memorymap.h.
◆ PERIPH_BASE_AHB2
| #define PERIPH_BASE_AHB2 (0x50000000U) |
Definition at line 30 of file stm32/g4/memorymap.h.
◆ PERIPH_BASE_APB1
| #define PERIPH_BASE_APB1 (0x40000000U) |
Definition at line 26 of file stm32/g4/memorymap.h.
◆ PERIPH_BASE_APB2
| #define PERIPH_BASE_APB2 (0x40010000U) |
Definition at line 27 of file stm32/g4/memorymap.h.
◆ PERIPH_BASE_IOPORT
| #define PERIPH_BASE_IOPORT (0x48000000U) |
Definition at line 29 of file stm32/g4/memorymap.h.
◆ POWER_CONTROL_BASE
| #define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) |
Definition at line 61 of file stm32/g4/memorymap.h.
◆ QUADSPI_BANK_BASE
| #define QUADSPI_BANK_BASE (0x90000000U) |
Definition at line 33 of file stm32/g4/memorymap.h.
◆ QUADSPI_BASE
| #define QUADSPI_BASE (0xa0001000U) |
Definition at line 122 of file stm32/g4/memorymap.h.
◆ RCC_BASE
| #define RCC_BASE (PERIPH_BASE_AHB1 + 0x1000) |
Definition at line 94 of file stm32/g4/memorymap.h.
◆ RNG_BASE
| #define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800) |
Definition at line 119 of file stm32/g4/memorymap.h.
◆ RTC_BASE
| #define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) |
Definition at line 45 of file stm32/g4/memorymap.h.
◆ SAI1_BASE
| #define SAI1_BASE (PERIPH_BASE_APB2 + 0x5400) |
Definition at line 86 of file stm32/g4/memorymap.h.
◆ SPI1_BASE
| #define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) |
Definition at line 78 of file stm32/g4/memorymap.h.
◆ SPI2_BASE
| #define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800) |
Definition at line 48 of file stm32/g4/memorymap.h.
◆ SPI3_BASE
| #define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00) |
Definition at line 49 of file stm32/g4/memorymap.h.
◆ SPI4_BASE
| #define SPI4_BASE (PERIPH_BASE_APB2 + 0x3c00) |
Definition at line 81 of file stm32/g4/memorymap.h.
◆ ST_TSENSE_CAL1_30C
Definition at line 137 of file stm32/g4/memorymap.h.
◆ ST_TSENSE_CAL2_110C
Definition at line 138 of file stm32/g4/memorymap.h.
◆ ST_VREFINT_CAL
Definition at line 136 of file stm32/g4/memorymap.h.
◆ SYSCFG_BASE
| #define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000) |
Definition at line 72 of file stm32/g4/memorymap.h.
◆ TAMP_BASE
| #define TAMP_BASE (PERIPH_BASE_APB1 + 0x2400) |
Definition at line 44 of file stm32/g4/memorymap.h.
◆ TIM15_BASE
| #define TIM15_BASE (PERIPH_BASE_APB2 + 0x4000) |
Definition at line 82 of file stm32/g4/memorymap.h.
◆ TIM16_BASE
| #define TIM16_BASE (PERIPH_BASE_APB2 + 0x4400) |
Definition at line 83 of file stm32/g4/memorymap.h.
◆ TIM17_BASE
| #define TIM17_BASE (PERIPH_BASE_APB2 + 0x4800) |
Definition at line 84 of file stm32/g4/memorymap.h.
◆ TIM1_BASE
| #define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00) |
Definition at line 77 of file stm32/g4/memorymap.h.
◆ TIM20_BASE
| #define TIM20_BASE (PERIPH_BASE_APB2 + 0x5000) |
Definition at line 85 of file stm32/g4/memorymap.h.
◆ TIM2_BASE
| #define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) |
Definition at line 37 of file stm32/g4/memorymap.h.
◆ TIM3_BASE
| #define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) |
Definition at line 38 of file stm32/g4/memorymap.h.
◆ TIM4_BASE
| #define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) |
Definition at line 39 of file stm32/g4/memorymap.h.
◆ TIM5_BASE
| #define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) |
Definition at line 40 of file stm32/g4/memorymap.h.
◆ TIM6_BASE
| #define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) |
Definition at line 41 of file stm32/g4/memorymap.h.
◆ TIM7_BASE
| #define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) |
Definition at line 42 of file stm32/g4/memorymap.h.
◆ TIM8_BASE
| #define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400) |
Definition at line 79 of file stm32/g4/memorymap.h.
◆ UART4_BASE
| #define UART4_BASE (PERIPH_BASE_APB1 + 0x4C00) |
Definition at line 52 of file stm32/g4/memorymap.h.
◆ UART5_BASE
| #define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) |
Definition at line 53 of file stm32/g4/memorymap.h.
◆ UCPD1_BASE
| #define UCPD1_BASE (PERIPH_BASE_APB1 + 0xA000) |
Definition at line 66 of file stm32/g4/memorymap.h.
◆ USART1_BASE
| #define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) |
Definition at line 80 of file stm32/g4/memorymap.h.
◆ USART2_BASE
| #define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) |
Definition at line 50 of file stm32/g4/memorymap.h.
◆ USART3_BASE
| #define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) |
Definition at line 51 of file stm32/g4/memorymap.h.
◆ USB_DEV_FS_BASE
| #define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00) |
Definition at line 56 of file stm32/g4/memorymap.h.
◆ USB_PMA_BASE
| #define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6000) |
Definition at line 57 of file stm32/g4/memorymap.h.
◆ VREFBUF_BASE
| #define VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030) |
Definition at line 73 of file stm32/g4/memorymap.h.
◆ WWDG_BASE
| #define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) |
Definition at line 46 of file stm32/g4/memorymap.h.
