VF6XX

Here is a list of all modules:

[detail level 1234]

▼CM3 Defines	Defined Constants and Types for Cortex M3 core features
Debugging	Macros and functions to aid in debugging
▼Cortex Core Defines	libopencm3 Defined Constants and Types for the Cortex Core
Cortex Core Atomic support Defines	Atomic operation support
Cortex-M Data Watch and Trace unit.	System Control Space (SCS) => Data Watchpoint and Trace (DWT)
Cortex-M Flash Patch and Breakpoint (FPB) unit
Cortex-M Instrumentation Trace Macrocell (ITM)
▼Cortex-M MPU Defines	libopencm3 Cortex Memory Protection Unit
MPU Registers
MPU TYPE register fields	The MPU_TYPE register is always available, even if the MPU is not implemented
MPU CTRL register fields	Defines for the Control Register
MPU RNR register fields	Defines for the Region Number Register
MPU RBAR register fields	Defines for the Region Base Address Register
▼MPU RASR register fields	Defines for the Region Attribute and Size Register
MPU RASR Attributes	Not all attributes are available on v6m
▼Cortex-M NVIC Defines	libopencm3 Cortex Nested Vectored Interrupt Controller
NVIC Registers
Cortex M0/M3/M4 System Interrupts	IRQ numbers -3 and -6 to -9 are reserved
User interrupts for VF6xx series
▼Cortex-M System Control Block	The System Control Block is a section of the System Control Space
SCB Registers
SCB_CPUID Values
SCB_ICSR Values
SCB_VTOR Values
SCB_AICR Values
SCB_SCR Values
SCB_CCR Values
▼Cortex-M System Control Space	The System Control Space (SCS) is a memory-mapped 4KB address space that provides 32-bit registers for configuration, status reporting and control
SCS Registers
▼Cortex-M SysTick Defines	libopencm3 Defined Constants and Types for the Cortex SysTick
▼STK_CSR Values
Clock source selection
STK_RVR Values
STK_CALIB Values
Cortex-M Trace Port Interface Unit (TPIU)
▼Cortex Core Peripheral APIs	APIs for Cortex Core peripherals
DWT	libopencm3 Cortex-M Data Watchpoint and Trace unit
NVIC	libopencm3 Cortex Nested Vectored Interrupt Controller
SCB	libopencm3 Cortex-M System Control Block
SysTick	libopencm3 Cortex System Tick Timer
Coresight Registers	CoreSight Lock Status Registers and Lock Access Registers are documented for the DWT, ITM, FPB and TPIU peripherals
▼VF6xx	Libraries for Freescale VF6xx series Cortex-M4 core
CCM	VF6xx Clock Controller Module
GPIO	VF6xx General-Purpose Input/Output (GPIO)
IOMUX-Control	VF6xx IO Pad MUX Controller
UART	VF6xx Universal Asynchronous Receiver/Transmitter (UART)
▼VF6xx Defines	Defined Constants and Types for the VF6xx series
ANADIG Defines	Defined Constants and Types for the VF6xx Analog components control digital interface
CCM Defines	Defined Constants and Types for the VF6xx Common Clock Module
▼GPIO Defines	Defined Constants and Types for the VF6xx GPIO Module
GPIO register base addresses
▼IO MUX Controller Defines	Defined Constants and Types for the VF6xx IO MUX Controller
IO MUX Controller register
▼UART Defines	Defined Constants and Types for the VF6xx UART Module
▼UART register base addresses
UART Parity Selection
USART Hardware Flow Control Selection
User interrupt service routines (ISR) prototypes for VF6xx series
User interrupt service routines (ISR) defaults for VF6xx series