VF6xx Clock Controller Module More...

Collaboration diagram for CCM:

Functions
uint32_t	ccm_get_pll_pfd (uint32_t pfd_sel, uint32_t pll_pfd, uint32_t pll_clk)
	Calculate PFD clock. More...

void	ccm_clock_gate_enable (enum ccm_clock_gate gr)
	Enable clock of given device. More...

void	ccm_clock_gate_disable (enum ccm_clock_gate gr)
	Disable clock of given device. More...

void	ccm_calculate_clocks ()
	Calculate clocks. More...

Variables
static const uint32_t	pll1_main_clk = 528000000

static const uint32_t	pll2_main_clk = 528000000

static const uint32_t	pll3_main_clk = 480000000

uint32_t	ccm_core_clk

uint32_t	ccm_platform_bus_clk

uint32_t	ccm_ipg_bus_clk

Detailed Description

VF6xx Clock Controller Module

Clock Controller Module API.

Author: © 2014 Stefan Agner stefa.nosp@m.n@ag.nosp@m.ner.c.nosp@m.h

Date: 30 Jun 2014

This library supports the Clock Controller Module in the VF6xx SoCs by Freescale.

LGPL License Terms libopencm3 License

Function Documentation

◆ ccm_calculate_clocks()

void ccm_calculate_clocks ( void )

Calculate clocks.

This function calculates the root clocks from the registers. On Vybrid, we assume that the clocks/device is setup by the main operating system running on the Cortex-A5 (for instance Linux). However, in order to calculate clocks for peripherals its important to know the current value of those clocks.

This are mainly the ccm_core_clk which the Cortex-A5 is running with and lots of other clocks derive from. The ccm_platform_bus_clk is the clock which the Cortex-M4 is running with. And the ccm_ipg_bus_clk is the clock most peripherals run with.

Definition at line 150 of file ccm.c.

References ANADIG_PLL1_PFD, ANADIG_PLL2_PFD, CCM_CACRR, CCM_CACRR_ARM_CLK_DIV_MASK, CCM_CACRR_BUS_CLK_DIV_MASK, CCM_CACRR_BUS_CLK_DIV_SHIFT, CCM_CACRR_IPG_CLK_DIV_MASK, CCM_CACRR_IPG_CLK_DIV_SHIFT, CCM_CCSR, CCM_CCSR_PLL1_PFD_CLK_SEL_MASK, CCM_CCSR_PLL1_PFD_CLK_SEL_SHIFT, CCM_CCSR_PLL2_PFD_CLK_SEL_MASK, CCM_CCSR_PLL2_PFD_CLK_SEL_SHIFT, CCM_CCSR_SYS_CLK_SEL_FAST, CCM_CCSR_SYS_CLK_SEL_MASK, CCM_CCSR_SYS_CLK_SEL_PLL1_PFD, CCM_CCSR_SYS_CLK_SEL_PLL2, CCM_CCSR_SYS_CLK_SEL_PLL2_PFD, CCM_CCSR_SYS_CLK_SEL_PLL3, CCM_CCSR_SYS_CLK_SEL_SLOW, ccm_core_clk, ccm_get_pll_pfd(), ccm_ipg_bus_clk, ccm_platform_bus_clk, pll1_main_clk, pll2_main_clk, and pll3_main_clk.

Here is the call graph for this function:

◆ ccm_clock_gate_disable()

void ccm_clock_gate_disable ( enum ccm_clock_gate gr )

Disable clock of given device.

This disables (ungates) the clock for the given device.

Parameters

[in] gr enum ccm_clock_gate. Device

Definition at line 80 of file ccm.c.

References CCM_CCGR.

◆ ccm_clock_gate_enable()

void ccm_clock_gate_enable ( enum ccm_clock_gate gr )

Enable clock of given device.

This enables (gates) the clock for the given device.

Parameters

[in] gr enum ccm_clock_gate. Device

Definition at line 66 of file ccm.c.

References CCM_CCGR.

◆ ccm_get_pll_pfd()

uint32_t ccm_get_pll_pfd	(	uint32_t	pfd_sel,
		uint32_t	pll_pfd,
		uint32_t	pll_clk
	)

Calculate PFD clock.

This function calculates the PFD clock for PLL1/2 or 3. All those PLLs have the same PFD clock muxing/calculating logic, hence we can use one function for all of them

Parameters

[in]	pfd_sel	uint32_t. The PFD selection (muxing) value
[in]	pll_pfd	uint32_t. The ANADIG PFD register containing the fractions for all possible PFDs
[in]	pll_clk	uint32_t. PLLs main clock (which the PFDs are derived from)

Definition at line 100 of file ccm.c.

References ANADIG_PLL_PFD1_FRAC_MASK, ANADIG_PLL_PFD1_FRAC_SHIFT, ANADIG_PLL_PFD2_FRAC_MASK, ANADIG_PLL_PFD2_FRAC_SHIFT, ANADIG_PLL_PFD3_FRAC_MASK, ANADIG_PLL_PFD3_FRAC_SHIFT, ANADIG_PLL_PFD4_FRAC_MASK, ANADIG_PLL_PFD4_FRAC_SHIFT, CCM_CCSR_PLL_PFD_CLK_SEL_MAIN, CCM_CCSR_PLL_PFD_CLK_SEL_PFD1, CCM_CCSR_PLL_PFD_CLK_SEL_PFD2, CCM_CCSR_PLL_PFD_CLK_SEL_PFD3, and CCM_CCSR_PLL_PFD_CLK_SEL_PFD4.