libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
Macros | Enumerations | Functions | Variables
ccm.h File Reference
#include <libopencm3/cm3/common.h>
#include <libopencm3/vf6xx/memorymap.h>
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Macros

#define CCM_CCR   MMIO32(CCM_BASE + 0x00)
 
#define CCM_CSR   MMIO32(CCM_BASE + 0x04)
 
#define CCM_CCSR   MMIO32(CCM_BASE + 0x08)
 
#define CCM_CACRR   MMIO32(CCM_BASE + 0x0C)
 
#define CCM_CSCMR1   MMIO32(CCM_BASE + 0x10)
 
#define CCM_CSCDR1   MMIO32(CCM_BASE + 0x14)
 
#define CCM_CSCDR2   MMIO32(CCM_BASE + 0x18)
 
#define CCM_CSCDR3   MMIO32(CCM_BASE + 0x1C)
 
#define CCM_CSCMR2   MMIO32(CCM_BASE + 0x20)
 
#define CCM_CTOR   MMIO32(CCM_BASE + 0x28)
 
#define CCM_CLPCR   MMIO32(CCM_BASE + 0x2C)
 
#define CCM_CISR   MMIO32(CCM_BASE + 0x30)
 
#define CCM_CIMR   MMIO32(CCM_BASE + 0x34)
 
#define CCM_CCOSR   MMIO32(CCM_BASE + 0x38)
 
#define CCM_CGPR   MMIO32(CCM_BASE + 0x3C)
 
#define CCM_CCGR(offset)   MMIO32(CCM_BASE + 0x40 + (offset))
 
#define CCM_CMEOR(ovrr)   MMIO32(CCM_BASE + 0x70 + (4 * (ovrr)))
 
#define CCM_CPPDSR   MMIO32(CCM_BASE + 0x88)
 
#define CCM_CCOWR   MMIO32(CCM_BASE + 0x8C)
 
#define CCM_CCPGR(pcgr)   MMIO32(CCM_BASE + 0x90 + (4 * (pcgr)))
 
#define CCM_CCR_FIRC_EN   (1 << 16)
 
#define CCM_CCR_FXOSC_EN   (1 << 12)
 
#define CCM_CCR_OSCNT_MASK   0xff
 
#define CCM_CSR_FXOSC_RDY   (1 << 5)
 
#define CCM_CCSR_PLL3_PFDN4_EN   (1 << 31)
 
#define CCM_CCSR_PLL3_PFDN3_EN   (1 << 30)
 
#define CCM_CCSR_PLL3_PFDN2_EN   (1 << 29)
 
#define CCM_CCSR_PLL3_PFDN1_EN   (1 << 28)
 
#define CCM_CCSR_DAP_EN   (1 << 24)
 
#define CCM_CCSR_PLL2_PFD_CLK_SEL_SHIFT   19
 
#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK   (0x7 << 19)
 
#define CCM_CCSR_PLL1_PFD_CLK_SEL_SHIFT   16
 
#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK   (0x7 << 16)
 
#define CCM_CCSR_PLL_PFD_CLK_SEL_MAIN   0x0
 
#define CCM_CCSR_PLL_PFD_CLK_SEL_PFD1   0x1
 
#define CCM_CCSR_PLL_PFD_CLK_SEL_PFD2   0x2
 
#define CCM_CCSR_PLL_PFD_CLK_SEL_PFD3   0x3
 
#define CCM_CCSR_PLL_PFD_CLK_SEL_PFD4   0x4
 
#define CCM_CCSR_PLL2_PFDN4_EN   (1 << 15)
 
#define CCM_CCSR_PLL2_PFDN3_EN   (1 << 14)
 
#define CCM_CCSR_PLL2_PFDN2_EN   (1 << 13)
 
#define CCM_CCSR_PLL2_PFDN1_EN   (1 << 12)
 
#define CCM_CCSR_PLL1_PFDN4_EN   (1 << 11)
 
#define CCM_CCSR_PLL1_PFDN3_EN   (1 << 10)
 
#define CCM_CCSR_PLL1_PFDN2_EN   (1 << 9)
 
#define CCM_CCSR_PLL1_PFDN1_EN   (1 << 8)
 
#define CCM_CCSR_DDRC_CLK_SEL   (1 << 7)
 
#define CCM_CCSR_FAST_CLK_SEL   (1 << 6)
 
#define CCM_CCSR_SLOW_CLK_SEL   (1 << 5)
 
#define CCM_CCSR_SYS_CLK_SEL_SHIFT   0
 
#define CCM_CCSR_SYS_CLK_SEL_MASK   0x7
 
#define CCM_CCSR_SYS_CLK_SEL_FAST   0x0
 
#define CCM_CCSR_SYS_CLK_SEL_SLOW   0x1
 
#define CCM_CCSR_SYS_CLK_SEL_PLL2_PFD   0x2
 
#define CCM_CCSR_SYS_CLK_SEL_PLL2   0x3
 
#define CCM_CCSR_SYS_CLK_SEL_PLL1_PFD   0x4
 
#define CCM_CCSR_SYS_CLK_SEL_PLL3   0x5
 
#define CCM_CACRR_FLEX_CLK_DIV_SHIFT   22
 
#define CCM_CACRR_FLEX_CLK_DIV_MASK   (0x7 << 22)
 
#define CCM_CACRR_PLL6_CLK_DIV   (1 << 21)
 
#define CCM_CACRR_PLL3_CLK_DIV   (1 << 20)
 
#define CCM_CACRR_PLL1_PFD_CLK_DIV_SHIFT   16
 
#define CCM_CACRR_PLL1_PFD_CLK_DIV_MASK   (0x3 << 16)
 
#define CCM_CACRR_IPG_CLK_DIV_SHIFT   11
 
#define CCM_CACRR_IPG_CLK_DIV_MASK   (0x3 << 11)
 
#define CCM_CACRR_PLL4_CLK_DIV_SHIFT   6
 
#define CCM_CACRR_PLL4_CLK_DIV_MASK   (0x7 << 6)
 
#define CCM_CACRR_BUS_CLK_DIV_SHIFT   3
 
#define CCM_CACRR_BUS_CLK_DIV_MASK   (0x7 << 3)
 
#define CCM_CACRR_ARM_CLK_DIV_SHIFT   0
 
#define CCM_CACRR_ARM_CLK_DIV_MASK   (0x7 << 0)
 

Enumerations

enum  ccm_clock_gate {
  CG0_FLEXCAN0 = 0 , CG1_RESERVED , CG2_RESERVED , CG3_RESERVED ,
  CG4_DMA_MUX0 , CG5_DMA_MUX1 , CG6_RESERVED , CG7_UART0 ,
  CG8_UART1 , CG9_UART2 , CG10_UART3 , CG11_RESERVED ,
  CG12_SPI0 , CG13_SPI1 , CG14_RESERVED , CG15_SAI0 ,
  CG16_SAI1 , CG17_SAI2 , CG18_SAI3 , CG19_CRC ,
  CG20_USBC0 , CG21_RESERVED , CG22_PDB , CG23_PIT ,
  CG24_FTM0 , CG25_FTM1 , CG26_RESERVED , CG27_ADC0 ,
  CG28_RESERVED , CG29_TCON0 , CG30_WDOG_A5 , CG31_WDOG_M4 ,
  CG32_LPTMR , CG33_RESERVED , CG34_RLE , CG35_RESERVED ,
  CG36_QSPI0 , CG37_RESERVED , CG38_RESERVED , CG39_RESERVED ,
  CG40_IOMUX , CG41_PORTA , CG42_PORTB , CG43_PORTC ,
  CG44_PORTD , CG45_PORTE , CG46_RESERVED , CG47_RESERVED ,
  CG48_ANADIG , CG49_RESERVED , CG50_SCSCM , CG51_RESERVED ,
  CG52_RESERVED , CG53_RESERVED , CG54_RESERVED , CG55_RESERVED ,
  CG56_DCU0 , CG57_RESERVED , CG58_RESERVED , CG59_RESERVED ,
  CG60_RESERVED , CG61_RESERVED , CG62_RESERVED , CG63_RESERVED ,
  CG64_ASRC , CG65_SPDIF , CG66_ESAI , CG67_RESERVED ,
  CG68_RESERVED , CG69_EWM , CG70_I2C0 , CG71_I2C1 ,
  CG72_RESERVED , CG73_RESERVED , CG74_WKUP , CG75_CCM ,
  CG76_GPC , CG77_VREG_DIG , CG78_RESERVED , CG79_CMU ,
  CG80_NOTUSED , CG81_NOTUSED , CG82_NOTUSED , CG83_NOTUSED ,
  CG84_NOTUSED , CG85_NOTUSED , CG86_NOTUSED , CG87_NOTUSED ,
  CG88_NOTUSED , CG89_NOTUSED , CG90_NOTUSED , CG91_NOTUSED ,
  CG92_NOTUSED , CG93_NOTUSED , CG94_NOTUSED , CG95_NOTUSED ,
  CG96_RESERVED , CG97_DMA_MUX2 , CG98_DMA_MUX3 , CG99_RESERVED ,
  CG100_RESERVED , CG101_OTP_CTRL , CG102_RESERVED , CG103_RESERVED ,
  CG104_RESERVED , CG105_UART4 , CG106_UART5 , CG107_RESERVED ,
  CG108_SPI2 , CG109_SPI3 , CG110_DDRMC , CG111_RESERVED ,
  CG112_RESERVED , CG113_SDHC0 , CG114_SDHC1 , CG115_RESERVED ,
  CG116_USBC1 , CG117_RESERVED , CG118_RESERVED , CG119_RESERVED ,
  CG120_FTM2 , CG121_FTM3 , CG122_RESERVED , CG123_ADC1 ,
  CG124_RESERVED , CG125_TCON1 , CG126_SEG_LCD , CG127_RESERVED ,
  CG128_RESERVED , CG129_RESERVED , CG130_RESERVED , CG131_RESERVED ,
  CG132_QSPI1 , CG133_RESERVED , CG134_RESERVED , CG135_VADC ,
  CG136_VDEC , CG137_VIU3 , CG138_RESERVED , CG139_RESERVED ,
  CG140_DAC0 , CG141_DAC1 , CG142_RESERVED , CG143_NOTUSED ,
  CG144_ETH0_1588 , CG145_ETH1_1588 , CG146_RESERVED , CG147_RESERVED ,
  CG148_FLEXCAN1 , CG149_RESERVED , CG150_RESERVED , CG151_RESERVED ,
  CG152_DCU1 , CG153_RESERVED , CG154_RESERVED , CG155_RESERVED ,
  CG156_RESERVED , CG157_RESERVED , CG158_RESERVED , CG159_RESERVED ,
  CG160_NFC , CG161_RESERVED , CG162_RESERVED , CG163_RESERVED ,
  CG164_RESERVED , CG165_RESERVED , CG166_I2C2 , CG167_I2C3 ,
  CG168_ETH_L2 , CG169_RESERVED , CG170_RESERVED , CG171_RESERVED ,
  CG172_RESERVED , CG173_RESERVED , CG174_RESERVED , CG175_RESERVED ,
  CG176_RESERVED , CG177_RESERVED , CG178_RESERVED , CG179_RESERVED ,
  CG180_RESERVED , CG181_RESERVED , CG182_RESERVED , CG183_RESERVED ,
  CG184_RESERVED , CG185_RESERVED , CG186_RESERVED , CG187_RESERVED ,
  CG188_RESERVED , CG189_RESERVED , CG190_RESERVED , CG191_RESERVED
}
 

Functions

void ccm_clock_gate_enable (enum ccm_clock_gate gr)
 Enable clock of given device. More...
 
void ccm_clock_gate_disable (enum ccm_clock_gate gr)
 Disable clock of given device. More...
 
void ccm_calculate_clocks (void)
 Calculate clocks. More...
 

Variables

uint32_t ccm_core_clk
 
uint32_t ccm_platform_bus_clk
 
uint32_t ccm_ipg_bus_clk
 

Macro Definition Documentation

◆ CCM_CACRR

#define CCM_CACRR   MMIO32(CCM_BASE + 0x0C)

Definition at line 46 of file ccm.h.

◆ CCM_CACRR_ARM_CLK_DIV_MASK

#define CCM_CACRR_ARM_CLK_DIV_MASK   (0x7 << 0)

Definition at line 133 of file ccm.h.

◆ CCM_CACRR_ARM_CLK_DIV_SHIFT

#define CCM_CACRR_ARM_CLK_DIV_SHIFT   0

Definition at line 132 of file ccm.h.

◆ CCM_CACRR_BUS_CLK_DIV_MASK

#define CCM_CACRR_BUS_CLK_DIV_MASK   (0x7 << 3)

Definition at line 131 of file ccm.h.

◆ CCM_CACRR_BUS_CLK_DIV_SHIFT

#define CCM_CACRR_BUS_CLK_DIV_SHIFT   3

Definition at line 130 of file ccm.h.

◆ CCM_CACRR_FLEX_CLK_DIV_MASK

#define CCM_CACRR_FLEX_CLK_DIV_MASK   (0x7 << 22)

Definition at line 121 of file ccm.h.

◆ CCM_CACRR_FLEX_CLK_DIV_SHIFT

#define CCM_CACRR_FLEX_CLK_DIV_SHIFT   22

Definition at line 120 of file ccm.h.

◆ CCM_CACRR_IPG_CLK_DIV_MASK

#define CCM_CACRR_IPG_CLK_DIV_MASK   (0x3 << 11)

Definition at line 127 of file ccm.h.

◆ CCM_CACRR_IPG_CLK_DIV_SHIFT

#define CCM_CACRR_IPG_CLK_DIV_SHIFT   11

Definition at line 126 of file ccm.h.

◆ CCM_CACRR_PLL1_PFD_CLK_DIV_MASK

#define CCM_CACRR_PLL1_PFD_CLK_DIV_MASK   (0x3 << 16)

Definition at line 125 of file ccm.h.

◆ CCM_CACRR_PLL1_PFD_CLK_DIV_SHIFT

#define CCM_CACRR_PLL1_PFD_CLK_DIV_SHIFT   16

Definition at line 124 of file ccm.h.

◆ CCM_CACRR_PLL3_CLK_DIV

#define CCM_CACRR_PLL3_CLK_DIV   (1 << 20)

Definition at line 123 of file ccm.h.

◆ CCM_CACRR_PLL4_CLK_DIV_MASK

#define CCM_CACRR_PLL4_CLK_DIV_MASK   (0x7 << 6)

Definition at line 129 of file ccm.h.

◆ CCM_CACRR_PLL4_CLK_DIV_SHIFT

#define CCM_CACRR_PLL4_CLK_DIV_SHIFT   6

Definition at line 128 of file ccm.h.

◆ CCM_CACRR_PLL6_CLK_DIV

#define CCM_CACRR_PLL6_CLK_DIV   (1 << 21)

Definition at line 122 of file ccm.h.

◆ CCM_CCGR

#define CCM_CCGR (   offset)    MMIO32(CCM_BASE + 0x40 + (offset))

Definition at line 59 of file ccm.h.

◆ CCM_CCOSR

#define CCM_CCOSR   MMIO32(CCM_BASE + 0x38)

Definition at line 57 of file ccm.h.

◆ CCM_CCOWR

#define CCM_CCOWR   MMIO32(CCM_BASE + 0x8C)

Definition at line 63 of file ccm.h.

◆ CCM_CCPGR

#define CCM_CCPGR (   pcgr)    MMIO32(CCM_BASE + 0x90 + (4 * (pcgr)))

Definition at line 64 of file ccm.h.

◆ CCM_CCR

#define CCM_CCR   MMIO32(CCM_BASE + 0x00)

Definition at line 43 of file ccm.h.

◆ CCM_CCR_FIRC_EN

#define CCM_CCR_FIRC_EN   (1 << 16)

Definition at line 69 of file ccm.h.

◆ CCM_CCR_FXOSC_EN

#define CCM_CCR_FXOSC_EN   (1 << 12)

Definition at line 70 of file ccm.h.

◆ CCM_CCR_OSCNT_MASK

#define CCM_CCR_OSCNT_MASK   0xff

Definition at line 71 of file ccm.h.

◆ CCM_CCSR

#define CCM_CCSR   MMIO32(CCM_BASE + 0x08)

Definition at line 45 of file ccm.h.

◆ CCM_CCSR_DAP_EN

#define CCM_CCSR_DAP_EN   (1 << 24)

Definition at line 82 of file ccm.h.

◆ CCM_CCSR_DDRC_CLK_SEL

#define CCM_CCSR_DDRC_CLK_SEL   (1 << 7)

Definition at line 106 of file ccm.h.

◆ CCM_CCSR_FAST_CLK_SEL

#define CCM_CCSR_FAST_CLK_SEL   (1 << 6)

Definition at line 107 of file ccm.h.

◆ CCM_CCSR_PLL1_PFD_CLK_SEL_MASK

#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK   (0x7 << 16)

Definition at line 88 of file ccm.h.

◆ CCM_CCSR_PLL1_PFD_CLK_SEL_SHIFT

#define CCM_CCSR_PLL1_PFD_CLK_SEL_SHIFT   16

Definition at line 87 of file ccm.h.

◆ CCM_CCSR_PLL1_PFDN1_EN

#define CCM_CCSR_PLL1_PFDN1_EN   (1 << 8)

Definition at line 104 of file ccm.h.

◆ CCM_CCSR_PLL1_PFDN2_EN

#define CCM_CCSR_PLL1_PFDN2_EN   (1 << 9)

Definition at line 103 of file ccm.h.

◆ CCM_CCSR_PLL1_PFDN3_EN

#define CCM_CCSR_PLL1_PFDN3_EN   (1 << 10)

Definition at line 102 of file ccm.h.

◆ CCM_CCSR_PLL1_PFDN4_EN

#define CCM_CCSR_PLL1_PFDN4_EN   (1 << 11)

Definition at line 101 of file ccm.h.

◆ CCM_CCSR_PLL2_PFD_CLK_SEL_MASK

#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK   (0x7 << 19)

Definition at line 86 of file ccm.h.

◆ CCM_CCSR_PLL2_PFD_CLK_SEL_SHIFT

#define CCM_CCSR_PLL2_PFD_CLK_SEL_SHIFT   19

Definition at line 85 of file ccm.h.

◆ CCM_CCSR_PLL2_PFDN1_EN

#define CCM_CCSR_PLL2_PFDN1_EN   (1 << 12)

Definition at line 99 of file ccm.h.

◆ CCM_CCSR_PLL2_PFDN2_EN

#define CCM_CCSR_PLL2_PFDN2_EN   (1 << 13)

Definition at line 98 of file ccm.h.

◆ CCM_CCSR_PLL2_PFDN3_EN

#define CCM_CCSR_PLL2_PFDN3_EN   (1 << 14)

Definition at line 97 of file ccm.h.

◆ CCM_CCSR_PLL2_PFDN4_EN

#define CCM_CCSR_PLL2_PFDN4_EN   (1 << 15)

Definition at line 96 of file ccm.h.

◆ CCM_CCSR_PLL3_PFDN1_EN

#define CCM_CCSR_PLL3_PFDN1_EN   (1 << 28)

Definition at line 80 of file ccm.h.

◆ CCM_CCSR_PLL3_PFDN2_EN

#define CCM_CCSR_PLL3_PFDN2_EN   (1 << 29)

Definition at line 79 of file ccm.h.

◆ CCM_CCSR_PLL3_PFDN3_EN

#define CCM_CCSR_PLL3_PFDN3_EN   (1 << 30)

Definition at line 78 of file ccm.h.

◆ CCM_CCSR_PLL3_PFDN4_EN

#define CCM_CCSR_PLL3_PFDN4_EN   (1 << 31)

Definition at line 77 of file ccm.h.

◆ CCM_CCSR_PLL_PFD_CLK_SEL_MAIN

#define CCM_CCSR_PLL_PFD_CLK_SEL_MAIN   0x0

Definition at line 90 of file ccm.h.

◆ CCM_CCSR_PLL_PFD_CLK_SEL_PFD1

#define CCM_CCSR_PLL_PFD_CLK_SEL_PFD1   0x1

Definition at line 91 of file ccm.h.

◆ CCM_CCSR_PLL_PFD_CLK_SEL_PFD2

#define CCM_CCSR_PLL_PFD_CLK_SEL_PFD2   0x2

Definition at line 92 of file ccm.h.

◆ CCM_CCSR_PLL_PFD_CLK_SEL_PFD3

#define CCM_CCSR_PLL_PFD_CLK_SEL_PFD3   0x3

Definition at line 93 of file ccm.h.

◆ CCM_CCSR_PLL_PFD_CLK_SEL_PFD4

#define CCM_CCSR_PLL_PFD_CLK_SEL_PFD4   0x4

Definition at line 94 of file ccm.h.

◆ CCM_CCSR_SLOW_CLK_SEL

#define CCM_CCSR_SLOW_CLK_SEL   (1 << 5)

Definition at line 108 of file ccm.h.

◆ CCM_CCSR_SYS_CLK_SEL_FAST

#define CCM_CCSR_SYS_CLK_SEL_FAST   0x0

Definition at line 112 of file ccm.h.

◆ CCM_CCSR_SYS_CLK_SEL_MASK

#define CCM_CCSR_SYS_CLK_SEL_MASK   0x7

Definition at line 111 of file ccm.h.

◆ CCM_CCSR_SYS_CLK_SEL_PLL1_PFD

#define CCM_CCSR_SYS_CLK_SEL_PLL1_PFD   0x4

Definition at line 116 of file ccm.h.

◆ CCM_CCSR_SYS_CLK_SEL_PLL2

#define CCM_CCSR_SYS_CLK_SEL_PLL2   0x3

Definition at line 115 of file ccm.h.

◆ CCM_CCSR_SYS_CLK_SEL_PLL2_PFD

#define CCM_CCSR_SYS_CLK_SEL_PLL2_PFD   0x2

Definition at line 114 of file ccm.h.

◆ CCM_CCSR_SYS_CLK_SEL_PLL3

#define CCM_CCSR_SYS_CLK_SEL_PLL3   0x5

Definition at line 117 of file ccm.h.

◆ CCM_CCSR_SYS_CLK_SEL_SHIFT

#define CCM_CCSR_SYS_CLK_SEL_SHIFT   0

Definition at line 110 of file ccm.h.

◆ CCM_CCSR_SYS_CLK_SEL_SLOW

#define CCM_CCSR_SYS_CLK_SEL_SLOW   0x1

Definition at line 113 of file ccm.h.

◆ CCM_CGPR

#define CCM_CGPR   MMIO32(CCM_BASE + 0x3C)

Definition at line 58 of file ccm.h.

◆ CCM_CIMR

#define CCM_CIMR   MMIO32(CCM_BASE + 0x34)

Definition at line 56 of file ccm.h.

◆ CCM_CISR

#define CCM_CISR   MMIO32(CCM_BASE + 0x30)

Definition at line 55 of file ccm.h.

◆ CCM_CLPCR

#define CCM_CLPCR   MMIO32(CCM_BASE + 0x2C)

Definition at line 54 of file ccm.h.

◆ CCM_CMEOR

#define CCM_CMEOR (   ovrr)    MMIO32(CCM_BASE + 0x70 + (4 * (ovrr)))

Definition at line 60 of file ccm.h.

◆ CCM_CPPDSR

#define CCM_CPPDSR   MMIO32(CCM_BASE + 0x88)

Definition at line 61 of file ccm.h.

◆ CCM_CSCDR1

#define CCM_CSCDR1   MMIO32(CCM_BASE + 0x14)

Definition at line 48 of file ccm.h.

◆ CCM_CSCDR2

#define CCM_CSCDR2   MMIO32(CCM_BASE + 0x18)

Definition at line 49 of file ccm.h.

◆ CCM_CSCDR3

#define CCM_CSCDR3   MMIO32(CCM_BASE + 0x1C)

Definition at line 50 of file ccm.h.

◆ CCM_CSCMR1

#define CCM_CSCMR1   MMIO32(CCM_BASE + 0x10)

Definition at line 47 of file ccm.h.

◆ CCM_CSCMR2

#define CCM_CSCMR2   MMIO32(CCM_BASE + 0x20)

Definition at line 51 of file ccm.h.

◆ CCM_CSR

#define CCM_CSR   MMIO32(CCM_BASE + 0x04)

Definition at line 44 of file ccm.h.

◆ CCM_CSR_FXOSC_RDY

#define CCM_CSR_FXOSC_RDY   (1 << 5)

Definition at line 74 of file ccm.h.

◆ CCM_CTOR

#define CCM_CTOR   MMIO32(CCM_BASE + 0x28)

Definition at line 53 of file ccm.h.

Enumeration Type Documentation

◆ ccm_clock_gate

enum ccm_clock_gate
Enumerator
CG0_FLEXCAN0 
CG1_RESERVED 
CG2_RESERVED 
CG3_RESERVED 
CG4_DMA_MUX0 
CG5_DMA_MUX1 
CG6_RESERVED 
CG7_UART0 
CG8_UART1 
CG9_UART2 
CG10_UART3 
CG11_RESERVED 
CG12_SPI0 
CG13_SPI1 
CG14_RESERVED 
CG15_SAI0 
CG16_SAI1 
CG17_SAI2 
CG18_SAI3 
CG19_CRC 
CG20_USBC0 
CG21_RESERVED 
CG22_PDB 
CG23_PIT 
CG24_FTM0 
CG25_FTM1 
CG26_RESERVED 
CG27_ADC0 
CG28_RESERVED 
CG29_TCON0 
CG30_WDOG_A5 
CG31_WDOG_M4 
CG32_LPTMR 
CG33_RESERVED 
CG34_RLE 
CG35_RESERVED 
CG36_QSPI0 
CG37_RESERVED 
CG38_RESERVED 
CG39_RESERVED 
CG40_IOMUX 
CG41_PORTA 
CG42_PORTB 
CG43_PORTC 
CG44_PORTD 
CG45_PORTE 
CG46_RESERVED 
CG47_RESERVED 
CG48_ANADIG 
CG49_RESERVED 
CG50_SCSCM 
CG51_RESERVED 
CG52_RESERVED 
CG53_RESERVED 
CG54_RESERVED 
CG55_RESERVED 
CG56_DCU0 
CG57_RESERVED 
CG58_RESERVED 
CG59_RESERVED 
CG60_RESERVED 
CG61_RESERVED 
CG62_RESERVED 
CG63_RESERVED 
CG64_ASRC 
CG65_SPDIF 
CG66_ESAI 
CG67_RESERVED 
CG68_RESERVED 
CG69_EWM 
CG70_I2C0 
CG71_I2C1 
CG72_RESERVED 
CG73_RESERVED 
CG74_WKUP 
CG75_CCM 
CG76_GPC 
CG77_VREG_DIG 
CG78_RESERVED 
CG79_CMU 
CG80_NOTUSED 
CG81_NOTUSED 
CG82_NOTUSED 
CG83_NOTUSED 
CG84_NOTUSED 
CG85_NOTUSED 
CG86_NOTUSED 
CG87_NOTUSED 
CG88_NOTUSED 
CG89_NOTUSED 
CG90_NOTUSED 
CG91_NOTUSED 
CG92_NOTUSED 
CG93_NOTUSED 
CG94_NOTUSED 
CG95_NOTUSED 
CG96_RESERVED 
CG97_DMA_MUX2 
CG98_DMA_MUX3 
CG99_RESERVED 
CG100_RESERVED 
CG101_OTP_CTRL 
CG102_RESERVED 
CG103_RESERVED 
CG104_RESERVED 
CG105_UART4 
CG106_UART5 
CG107_RESERVED 
CG108_SPI2 
CG109_SPI3 
CG110_DDRMC 
CG111_RESERVED 
CG112_RESERVED 
CG113_SDHC0 
CG114_SDHC1 
CG115_RESERVED 
CG116_USBC1 
CG117_RESERVED 
CG118_RESERVED 
CG119_RESERVED 
CG120_FTM2 
CG121_FTM3 
CG122_RESERVED 
CG123_ADC1 
CG124_RESERVED 
CG125_TCON1 
CG126_SEG_LCD 
CG127_RESERVED 
CG128_RESERVED 
CG129_RESERVED 
CG130_RESERVED 
CG131_RESERVED 
CG132_QSPI1 
CG133_RESERVED 
CG134_RESERVED 
CG135_VADC 
CG136_VDEC 
CG137_VIU3 
CG138_RESERVED 
CG139_RESERVED 
CG140_DAC0 
CG141_DAC1 
CG142_RESERVED 
CG143_NOTUSED 
CG144_ETH0_1588 
CG145_ETH1_1588 
CG146_RESERVED 
CG147_RESERVED 
CG148_FLEXCAN1 
CG149_RESERVED 
CG150_RESERVED 
CG151_RESERVED 
CG152_DCU1 
CG153_RESERVED 
CG154_RESERVED 
CG155_RESERVED 
CG156_RESERVED 
CG157_RESERVED 
CG158_RESERVED 
CG159_RESERVED 
CG160_NFC 
CG161_RESERVED 
CG162_RESERVED 
CG163_RESERVED 
CG164_RESERVED 
CG165_RESERVED 
CG166_I2C2 
CG167_I2C3 
CG168_ETH_L2 
CG169_RESERVED 
CG170_RESERVED 
CG171_RESERVED 
CG172_RESERVED 
CG173_RESERVED 
CG174_RESERVED 
CG175_RESERVED 
CG176_RESERVED 
CG177_RESERVED 
CG178_RESERVED 
CG179_RESERVED 
CG180_RESERVED 
CG181_RESERVED 
CG182_RESERVED 
CG183_RESERVED 
CG184_RESERVED 
CG185_RESERVED 
CG186_RESERVED 
CG187_RESERVED 
CG188_RESERVED 
CG189_RESERVED 
CG190_RESERVED 
CG191_RESERVED 

Definition at line 141 of file ccm.h.