libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
vf6xx/memorymap.h
Go to the documentation of this file.
1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2014 Stefan Agner <stefan@agner.ch>
5 *
6 * This library is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU Lesser General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public License
17 * along with this library. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef LIBOPENCM3_MEMORYMAP_H
21#define LIBOPENCM3_MEMORYMAP_H
22
23#include <libopencm3/cm3/memorymap.h>
24
25/* --- VF6xx specific peripheral definitions ----------------------------- */
26
27/* Memory map for all busses */
28#define PERIPH_BASE (0x40000000U)
29#define PERIPH_BASE_AIPS0 (PERIPH_BASE + 0x00000)
30#define PERIPH_BASE_AIPS1 (PERIPH_BASE + 0x80000)
31
32/* Pheripheral addresses */
33
34/* AIPS0 */
35#define MSCM_BASE (PERIPH_BASE_AIPS0 + 0x01000)
36
37#define SEMA4_BASE (PERIPH_BASE_AIPS0 + 0x1D000)
38
39#define UART0_BASE (PERIPH_BASE_AIPS0 + 0x27000)
40#define UART1_BASE (PERIPH_BASE_AIPS0 + 0x28000)
41#define UART2_BASE (PERIPH_BASE_AIPS0 + 0x29000)
42#define UART3_BASE (PERIPH_BASE_AIPS0 + 0x2A000)
43
44#define SPI0_BASE (PERIPH_BASE_AIPS0 + 0x2C000)
45#define SPI1_BASE (PERIPH_BASE_AIPS0 + 0x2D000)
46
47#define IOMUXC_BASE (PERIPH_BASE_AIPS0 + 0x48000)
48#define PORTA_MUX_BASE (PERIPH_BASE_AIPS0 + 0x49000)
49#define PORTB_MUX_BASE (PERIPH_BASE_AIPS0 + 0x4A000)
50#define PORTC_MUX_BASE (PERIPH_BASE_AIPS0 + 0x4B000)
51#define PORTD_MUX_BASE (PERIPH_BASE_AIPS0 + 0x4C000)
52#define PORTE_MUX_BASE (PERIPH_BASE_AIPS0 + 0x4D000)
53
54#define ANADIG_BASE (PERIPH_BASE_AIPS0 + 0x50000)
55
56#define CCM_BASE (PERIPH_BASE_AIPS0 + 0x6B000)
57
58/* AIPS1 */
59#define UART4_BASE (PERIPH_BASE_AIPS1 + 0x29000)
60#define UART5_BASE (PERIPH_BASE_AIPS1 + 0x2A000)
61
62/* GPIO module */
63#define GPIO_BASE (PERIPH_BASE + 0xff000)
64
65#endif