STM32F4

Here is a list of all modules:

[detail level 12345]

▼CM3 Defines	Defined Constants and Types for Cortex M3 core features
Debugging	Macros and functions to aid in debugging
►Cortex Core Defines	libopencm3 Defined Constants and Types for the Cortex Core
Cortex Core Atomic support Defines	Atomic operation support
Cortex-M Data Watch and Trace unit.	System Control Space (SCS) => Data Watchpoint and Trace (DWT)
Cortex-M Flash Patch and Breakpoint (FPB) unit
Cortex-M Instrumentation Trace Macrocell (ITM)
►Cortex-M MPU Defines	libopencm3 Cortex Memory Protection Unit
MPU Registers
MPU TYPE register fields	The MPU_TYPE register is always available, even if the MPU is not implemented
MPU CTRL register fields	Defines for the Control Register
MPU RNR register fields	Defines for the Region Number Register
MPU RBAR register fields	Defines for the Region Base Address Register
►MPU RASR register fields	Defines for the Region Attribute and Size Register
MPU RASR Attributes	Not all attributes are available on v6m
►Cortex-M NVIC Defines	libopencm3 Cortex Nested Vectored Interrupt Controller
NVIC Registers
Cortex M0/M3/M4 System Interrupts	IRQ numbers -3 and -6 to -9 are reserved
User interrupts for STM32 F4 series
►Cortex-M System Control Block	The System Control Block is a section of the System Control Space
SCB Registers
SCB_CPUID Values
SCB_ICSR Values
SCB_VTOR Values
SCB_AICR Values
SCB_SCR Values
SCB_CCR Values
►Cortex-M System Control Space	The System Control Space (SCS) is a memory-mapped 4KB address space that provides 32-bit registers for configuration, status reporting and control
SCS Registers
►Cortex-M SysTick Defines	libopencm3 Defined Constants and Types for the Cortex SysTick
►STK_CSR Values
Clock source selection
STK_RVR Values
STK_CALIB Values
Cortex-M Trace Port Interface Unit (TPIU)
▼Cortex Core Peripheral APIs	APIs for Cortex Core peripherals
DWT	libopencm3 Cortex-M Data Watchpoint and Trace unit
NVIC	libopencm3 Cortex Nested Vectored Interrupt Controller
SCB	libopencm3 Cortex-M System Control Block
SysTick	libopencm3 Cortex System Tick Timer
Coresight Registers	CoreSight Lock Status Registers and Lock Access Registers are documented for the DWT, ITM, FPB and TPIU peripherals
▼Peripheral APIs	APIs for device peripherals
QuadSPI peripheral API	APIs for the specialized SPI Flash peripheral
DMA2D peripheral API
DMA peripheral API	DMA library for the multi stream controller found in f2/f4/f7 parts
DSI peripheral API
LTDC peripheral API
FLASH peripheral API	libopencm3 STM32F4xx FLASH
PWR peripheral API	libopencm3 STM32F4xx Power Control
RCC peripheral API	libopencm3 STM32F4xx Reset and Clock Control
RTC peripheral API	libopencm3 STM32F4xx RTC
ADC peripheral API
CRC peripheral API
DAC peripheral API	Digital to Analog Converter
DCMI peripheral API	Digital camera interface
EXTI peripheral API
FMC peripheral API
GPIO peripheral API
HASH Peripheral API
I2C peripheral API
IWDG peripheral API
LPTIM peripheral API
RNG peripheral API	This library supports "version 1" of the random number generator peripheral (RNG) in the STM32 series of ARM Cortex Microcontrollers by ST Microelectronics
SPI peripheral API
TIMER peripheral API
USART peripheral API
▼STM32F4xx	Libraries for ST Microelectronics STM32F4xx series
CRYPTO	libopencm3 STM32F4xx CRYPTO
▼STM32F4xx Defines	Defined Constants and Types for the STM32F4xx series
►ADC Defines	Defined Constants and Types for the STM32F4xx Analog to Digital Converters
ADC Channel Numbers	Thanks ST! F40x and F41x are on 16, F42x and F43x are on 18!
ADC Trigger Identifier for Regular group
ADC Trigger Identifier for Injected group
ADC Sample Time Selection for All Channels
ADC Prescale
ADC register base addresses
ADC Status Register Flags
ADC Number of channels in discontinuous mode.
ADC watchdog channel
ADC Number of channels in discontinuous injected mode
ADC Resolution.
ADC Trigger Polarity
ADC Injected Trigger Polarity
ADC DMA mode for multi ADC mode
ADC Delay between 2 sampling phases
ADC Multi mode selection
►CRC Defines	libopencm3 Defined Constants and Types for the STM32F4xx CRC Generator
CRC Registers
CRC_CR values
►CRYPTO Defines	Defined constants and Types for the STM32F4xx Crypto Coprocessor
Registers (for F42xx or F43xx only)	Register access to the CRYP controller
API (for F42xx or F43xx only)	API for the CRYP controller
Registers (Generic)	Register access to the CRYP controller
API (Generic)	API for the CRYP controller
►DAC Defines	Defined Constants and Types for the STM32F4xx DAC
DAC register base addresses
DAC Registers
►DAC_CR values
DAC Channel 2 Trigger Source Selection
DAC Channel 1 Trigger Source Selection
DAC_SWTRIGR Values
DAC_DHRxxx Values
DAC_DORx Values
DAC_SR Values
DAC Channel Identifier
►DCMI Defines	Defined Constants and Macros for the STM32F4xx DCMI Peripheral
DCMI_CR Values
DCMI_SR Values
DCMI_RIS Values
DCMI_IER Values
DCMI_MIS Values
DCMI_ICR Values
DCMI_ESCR Values
DCMI_ESUR Values
DCMI_CWSTRT Values
DCMI_CWSIZE Values
DMA2D Defines	Defined Constants and Types for the STM32F4xx DMA2D Peripheral
►DMA Defines	Defined Constants and Types for the STM32F4xx DMA Controller
DMA Stream Number
DMA Interrupt Flag Offsets within stream flag group.
DMA Stream Data transfer direction
DMA Stream Peripheral Word Width
DMA Stream Memory Word Width
DMA Stream Priority Levels
DMA Peripheral Burst Length
DMA Memory Burst Length
DMA Channel Select
FIFO Threshold selection
FIFO Status
DSI Defines	Defines Constants and Macros for the STM32F4xx Display Serial Interface Host and Wrapper
►EXTI Defines	Defined Constants and Types for the STM32F4xx External Interrupts
EXTI Registers
►FLASH Defines	Defined Constants and Types for the STM32F4xx FLASH Memory
►Flash Registers
FLASH_ACR values	Access Control register values
FLASH Wait States
FLASH_ACR values	Access Control register values
Flash programming width
FMC Defines	Defined Constants and Types for the STM32F4xx Flexible Memory Controller
►GPIO Defines	Defined Constants and Types for the STM32F4xx General Purpose I/O
GPIO Pin Identifiers
GPIO Port IDs
GPIO Pin Direction and Analog/Digital Mode
GPIO Output Pin Driver Type
GPIO Output Pin Speed
GPIO Output Pin Pullup
Alternate Function Pin Selection
►HASH Defines	Defined Constants and Types for the STM32F4xx HASH Controller
HASH register base addresses
HASH Data Type
HASH Mode
HASH Algorithm
HASH Key length
►I2C Defines	Defined Constants and Types for the STM32F4xx I2C
I2C register base address
I2C peripheral clock duty cycles
I2C Read/Write bit
►IWDG Defines	Defined Constants and Types for the STM32F4xx Independent Watchdog Timer
IWDG Key Values
IWDG prescaler divider
IWDG Status Register Values
►LPTIM Defines	libopencm3 Defined Constants and Types for the STM32F4xx Low Power Timer
Low Power Timer register base addresses
LPTIM_ISR Interrupt and Status Register
LPTIM_ICR Interrupt Clear Register
LPTIM_IER Interrupt Enable Register
►LPTIM_CFGR Configuration Register
LPTIM_CFGR CKPOL Clock Polarity
LPTIM_CFGR CKFLT Configurable digital filter for external clock
LPTIM_CFGR TRGFLT Configurable digital filter for trigger
LPTIM_CFGR PRESC Clock prescaler
LPTIM_CFGR TRIGSEL Trigger selector
LPTIM_CFGR TRIGEN Trigger enable and polarity
LPTIM_CR Control Register
►LTDC Defines	Defined Constants and Types for the STM32F4xx LCD TFT Display Controller
LTDC Layer Number
►PWR Defines	Defined Constants and Types for the STM32F4xx Power Control
PVD level selection
►QuadSPI Defines	Defined constants and types for the STM32F4 QuadSPI peripheral
QuadSPI Registers
►RCC Defines	Defined Constants and Types for the STM32F4xx Reset and Clock Control
►RCC Registers	Reset / Clock Control Registers
RCC_CR values	Clock Control register values
RCC_PLLCFGR values	PLL Configuration register values
►RCC_CFGR values	Clock Configuration register values
RCC_CFGR APBx prescale factors	These can be used for both APB1 and APB2 prescaling
RCC_CFGR AHB prescale factors
RCC_CIR values	Clock Interrupt register values
RCC_BDCR values	Backup Domain control register values
RCC_CSR values	Clock control and status register values
RCC_SSCGR values	Spread spectrum clock generation register values
►RCC_PLLxxx/DCKy values	PLL and other dedicated clock register values
PLLSAICFGR PLLSAIP values
RCC_CKGATENR bits	Allows to enable or disable the clock gating for the specified IPs
RCC_CR values	Clock Control register values
RCC_PLLCFGR values	PLL Configuration register values
►RCC_CFGR values	Clock Configuration register values
RCC_CFGR APBx prescale factors	These can be used for both APB1 and APB2 prescaling
RCC_CFGR AHB prescale factors
RCC_CFGR Deprecated dividers	Older compatible definitions to ease migration
RCC_CIR values	Clock Interrupt register values
►RCC_AHBxRSTR reset values (full set)
RCC_AHB1RSTR reset values
RCC_AHB2RSTR reset values
RCC_AHB3RSTR reset values
Deprecated 2018
RCC_APB1RSTR reset values
RCC_APB2RSTR reset values
►RCC_AHBxENR enable values (full set)
RCC_AHB1ENR enable values
RCC_AHB2ENR enable values
RCC_AHB3ENR enable values
Deprecated 2018
RCC_APB1ENR enable values
RCC_APB2ENR enable values
RCC_APBxLPENR enable values (full set)
RCC_BDCR values	Backup Domain control register values
RCC_CSR values	Clock control and status register values
RCC_SSCGR values	Spread spectrum clock generation register values
►RCC_PLLxxx/DCKy values	PLL and other dedicated clock register values
PLLSAICFGR PLLSAIP values
RCC_CKGATENR bits	Allows to enable or disable the clock gating for the specified IPs
►RTC Defines	Defined Constants and Types for the STM32F4xx RTC
►RTC Registers	Real Time Clock registers
RTC Time register (RTC_TR) values	Note: Bits [31:23], 15, and 7 are reserved, and must be kept at reset value
RTC Date register (RTC_DR) values	Note: Bits [31:24] and [7:6] are reserved, and must be kept at reset value
►RTC control register (RTC_CR) values	Note: Bits [31:24] are reserved, and must be kept at reset value
RTC_CR_OSEL: Output selection values	These bits are used to select the flag to be routed to AFO_ALARM RTC output
RTC initialization and status register (RTC_ISR) values	Note: Bits [31:17] and [15] are reserved, and must be kept at reset value
RTC prescaler register (RTC_PRER) values
RTC Alarm register values	Applies to RTC_ALRMAR and RTC_ALRMBR
RTC time stamp time register (RTC_TSTR) values
RTC time stamp date register (RTC_TSDR) values
RTC calibration register (RTC_CALR) values
RTC tamper and alternate function configuration register (RTC_TAFCR) values
RTC Time register (RTC_TR) values	Note: Bits [31:23], 15, and 7 are reserved, and must be kept at reset value
RTC Date register (RTC_DR) values	Note: Bits [31:24] and [7:6] are reserved, and must be kept at reset value
►RTC control register (RTC_CR) values	Note: Bits [31:24] are reserved, and must be kept at reset value
RTC_CR_OSEL: Output selection values	These bits are used to select the flag to be routed to AFO_ALARM RTC output
RTC initialization and status register (RTC_ISR) values	Note: Bits [31:17] and [15] are reserved, and must be kept at reset value
RTC prescaler register (RTC_PRER) values
RTC Alarm register values	Applies to RTC_ALRMAR and RTC_ALRMBR
RTC time stamp time register (RTC_TSTR) values
RTC time stamp date register (RTC_TSDR) values
RTC calibration register (RTC_CALR) values
RTC tamper and alternate function configuration register (RTC_TAFCR) values
►SPI Defines	Defined Constants and Types for the STM32F4xx SPI
SPI Register base address
SPI lsb/msb first
SPI peripheral baud rates
SPI peripheral baud rate prescale values
SPI clock polarity
SPI clock phase
SPI data frame format
SYSCFG Defines	Defined Constants and Types for the STM32F4xx Sysconfig
►Timer Defines	libopencm3 Defined Constants and Types for the STM32F4xx Timers
Timer register base addresses
TIMx_CR1 CKD[1:0] Clock Division Ratio
TIMx_CR1 CMS[1:0]: Center-aligned Mode Selection
TIMx_CR1 DIR: Direction
TIMx_CR2_OIS: Force Output Idle State Control Values
TIMx_CR2 MMS[6:4]: Master Mode Selection
TIMx_SMCR TS Trigger selection
TIMx_SMCR SMS Slave mode selection
TIMx_DIER Timer DMA and Interrupt Enable Values
TIMx_SR Timer Status Register Flags
TIMx_EGR Timer Event Generator Values
TIM_BDTR_LOCK Timer Lock Values
TIM2_OR Timer 2 Option Register Internal	Trigger 1 Remap
TIM5_OR Timer 5 Option Register Internal Trigger 4 Remap	Only available in F2 and F4 series
►USART Defines	Defined Constants and Types for the STM32F4xx USART
USART Parity Selection
USART Tx/Rx Mode Selection
USART Stop Bit Selection
USART Hardware Flow Control Selection
USART register base addresses	Holds all the U(S)ART peripherals supported
U(S)ART convenience Flags	We define the "common" lower flag bits using a standard name, allowing them to be used regardless of which usart peripheral version you have
USART Status register Flags
User interrupt service routines (ISR) prototypes for STM32 F4 series
MAC Generic Defines	Defined Constants and Types for the Ethernet MAC
MAC STM32Fxx7 Defines	Defined Constants and Types for the Ethernet MAC for STM32Fxx7 chips
PHY Generic Defines	Defined Constants and Types for the Ethernet PHY
PHY KSZ80X1 Defines	Defined Constants and Types for the Ethernet PHY KSZ80X1 chips chips
▼CAN defines	libopencm3 Defined Constants and Types for STM32 CAN
CAN register base address
USB Audio Type Definitions	Defined Constants and Types for the USB Audio Type Definitions
USB CDC Type Definitions	Defined Constants and Types for the USB CDC Type Definitions
USB HID Type Definitions	Defined Constants and Types for the USB HID Type Definitions
USB MSC Type Definitions	Defined Constants and Types for the USB MSC Type Definitions
USB Drivers	Defined Constants and Types for the USB Drivers
USB Standard Structure Definitions	Defined Constants and Types for the USB Standard Structure Definitions
CAN	libopencm3 STM32Fxxx CAN
User interrupt service routines (ISR) defaults for STM32 F4 series
MAC Generic Drivers	Ethernet MAC Generic Drivers
MAC STM32Fxx7	Ethernet MAC STM32Fxx7 Drivers
PHY Generic Drivers	Ethernet PHY Generic Drivers
PHY KSZ8051MLL	Ethernet PHY STM32Fxx7 Drivers
Generic USB Drivers	Generic USB Drivers
Generic USB Control Requests	Generic USB Control Requests
Generic USB Standard Request Interface	Generic USB Standard Request Interface
Usb_msc