Collaboration diagram for SCB Registers:

Macros
#define	SCB_CPUID MMIO32(SCB_BASE + 0x00)
	CPUID: CPUID base register. More...

#define	SCB_ICSR MMIO32(SCB_BASE + 0x04)
	ICSR: Interrupt Control State Register. More...

#define	SCB_VTOR MMIO32(SCB_BASE + 0x08)
	VTOR: Vector Table Offset Register. More...

#define	SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
	AIRCR: Application Interrupt and Reset Control Register. More...

#define	SCB_SCR MMIO32(SCB_BASE + 0x10)
	SCR: System Control Register. More...

#define	SCB_CCR MMIO32(SCB_BASE + 0x14)
	CCR: Configuration Control Register. More...

#define	SCB_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + (ipr_id))
	System Handler Priority 8 bits Registers, SHPR1/2/3. More...

#define	SCB_SHCSR MMIO32(SCB_BASE + 0x24)
	SHCSR: System Handler Control and State Register. More...

#define	SCB_DFSR MMIO32(SCB_BASE + 0x30)
	DFSR: Debug Fault Status Register. More...

#define	SCB_CFSR MMIO32(SCB_BASE + 0x28)
	CFSR: Configurable Fault Status Registers. More...

#define	SCB_HFSR MMIO32(SCB_BASE + 0x2C)
	HFSR: Hard Fault Status Register. More...

#define	SCB_MMFAR MMIO32(SCB_BASE + 0x34)
	MMFAR: Memory Manage Fault Address Register. More...

#define	SCB_BFAR MMIO32(SCB_BASE + 0x38)
	BFAR: Bus Fault Address Register. More...

#define	SCB_AFSR MMIO32(SCB_BASE + 0x3C)
	AFSR: Auxiliary Fault Status Register. More...

#define	SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40)
	ID_PFR0: Processor Feature Register 0. More...

#define	SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44)
	ID_PFR1: Processor Feature Register 1. More...

#define	SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48)
	ID_DFR0: Debug Features Register 0. More...

#define	SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C)
	ID_AFR0: Auxiliary Features Register 0. More...

#define	SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50)
	ID_MMFR0: Memory Model Feature Register 0. More...

#define	SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54)
	ID_MMFR1: Memory Model Feature Register 1. More...

#define	SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58)
	ID_MMFR2: Memory Model Feature Register 2. More...

#define	SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C)
	ID_MMFR3: Memory Model Feature Register 3. More...

#define	SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60)
	ID_ISAR0: Instruction Set Attributes Register 0. More...

#define	SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64)
	ID_ISAR1: Instruction Set Attributes Register 1. More...

#define	SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68)
	ID_ISAR2: Instruction Set Attributes Register 2. More...

#define	SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C)
	ID_ISAR3: Instruction Set Attributes Register 3. More...

#define	SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70)
	ID_ISAR4: Instruction Set Attributes Register 4. More...

#define	SCB_CPACR MMIO32(SCB_BASE + 0x88)
	CPACR: Coprocessor Access Control Register. More...

#define	SCB_FPCCR MMIO32(SCB_BASE + 0x234)
	FPCCR: Floating-Point Context Control Register. More...

#define	SCB_FPCAR MMIO32(SCB_BASE + 0x238)
	FPCAR: Floating-Point Context Address Register. More...

#define	SCB_FPDSCR MMIO32(SCB_BASE + 0x23C)
	FPDSCR: Floating-Point Default Status Control Register. More...

#define	SCB_MVFR0 MMIO32(SCB_BASE + 0x240)
	MVFR0: Media and Floating-Point Feature Register 0. More...

#define	SCB_MVFR1 MMIO32(SCB_BASE + 0x244)
	MVFR1: Media and Floating-Point Feature Register 1. More...

#define	SCB_CLIDR MMIO32(SCB_BASE + 0x78)
	CLIDR: Cache Level ID Register. More...

#define	SCB_CTR MMIO32(SCB_BASE + 0x7C)
	CTR: Cache Type Register. More...

#define	SCB_CCSIDR MMIO32(SCB_BASE + 0x80)
	CCSIDR: Cache Size ID Registers. More...

#define	SCB_CCSELR MMIO32(SCB_BASE + 0x84)
	CSSELR: Cache Size Selection Register. More...

#define	SCB_ICIALLU MMIO32(SCB_BASE + 0x250)
	ICIALLU: I-cache invalidate all to Point of Unification. More...

#define	SCB_ICIMVAU MMIO32(SCB_BASE + 0x258)
	ICIMVAU: I-cache invalidate by MVA to Point of Unification. More...

#define	SCB_DCIMVAC MMIO32(SCB_BASE + 0x25C)
	DCIMVAC: D-cache invalidate by MVA to Point of Coherency. More...

#define	SCB_DCISW MMIO32(SCB_BASE + 0x260)
	DCISW: D-cache invalidate by set-way. More...

#define	SCB_DCCMVAU MMIO32(SCB_BASE + 0x264)
	DCCMVAU: D-cache clean by MVA to Point of Unification. More...

#define	SCB_DCCMVAC MMIO32(SCB_BASE + 0x268)
	DCCMVAC: D-cache clean by MVA to Point of Coherency. More...

#define	SCB_DCCSW MMIO32(SCB_BASE + 0x26C)
	DCISW: D-cache clean by set-way. More...

#define	SCB_DCCIMVAC MMIO32(SCB_BASE + 0x270)
	DCCIMVAC: D-cache clean and invalidate by MVA to Point of Coherency. More...

#define	SCB_DCCISW MMIO32(SCB_BASE + 0x274)
	DCCISW: D-cache clean and invalidate by set-way. More...

#define	SCB_BPIALL MMIO32(SCB_BASE + 0x278)
	BPIALL: Branch predictor invalidate all. More...

Detailed Description

Macro Definition Documentation

◆ SCB_AFSR

#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)

AFSR: Auxiliary Fault Status Register.

Definition at line 92 of file scb.h.

◆ SCB_AIRCR

#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)

AIRCR: Application Interrupt and Reset Control Register.

Definition at line 52 of file scb.h.

◆ SCB_BFAR

#define SCB_BFAR MMIO32(SCB_BASE + 0x38)

BFAR: Bus Fault Address Register.

Definition at line 89 of file scb.h.

◆ SCB_BPIALL

#define SCB_BPIALL MMIO32(SCB_BASE + 0x278)

BPIALL: Branch predictor invalidate all.

Definition at line 194 of file scb.h.

◆ SCB_CCR

#define SCB_CCR MMIO32(SCB_BASE + 0x14)

CCR: Configuration Control Register.

Definition at line 58 of file scb.h.

◆ SCB_CCSELR

#define SCB_CCSELR MMIO32(SCB_BASE + 0x84)

CSSELR: Cache Size Selection Register.

Definition at line 164 of file scb.h.

◆ SCB_CCSIDR

#define SCB_CCSIDR MMIO32(SCB_BASE + 0x80)

CCSIDR: Cache Size ID Registers.

Definition at line 161 of file scb.h.

◆ SCB_CFSR

#define SCB_CFSR MMIO32(SCB_BASE + 0x28)

CFSR: Configurable Fault Status Registers.

Definition at line 80 of file scb.h.

◆ SCB_CLIDR

#define SCB_CLIDR MMIO32(SCB_BASE + 0x78)

CLIDR: Cache Level ID Register.

Definition at line 155 of file scb.h.

◆ SCB_CPACR

#define SCB_CPACR MMIO32(SCB_BASE + 0x88)

CPACR: Coprocessor Access Control Register.

Definition at line 134 of file scb.h.

◆ SCB_CPUID

#define SCB_CPUID MMIO32(SCB_BASE + 0x00)

CPUID: CPUID base register.

Definition at line 43 of file scb.h.

◆ SCB_CTR

#define SCB_CTR MMIO32(SCB_BASE + 0x7C)

CTR: Cache Type Register.

Definition at line 158 of file scb.h.

◆ SCB_DCCIMVAC

#define SCB_DCCIMVAC MMIO32(SCB_BASE + 0x270)

DCCIMVAC: D-cache clean and invalidate by MVA to Point of Coherency.

Definition at line 188 of file scb.h.

◆ SCB_DCCISW

#define SCB_DCCISW MMIO32(SCB_BASE + 0x274)

DCCISW: D-cache clean and invalidate by set-way.

Definition at line 191 of file scb.h.

◆ SCB_DCCMVAC

#define SCB_DCCMVAC MMIO32(SCB_BASE + 0x268)

DCCMVAC: D-cache clean by MVA to Point of Coherency.

Definition at line 182 of file scb.h.

◆ SCB_DCCMVAU

#define SCB_DCCMVAU MMIO32(SCB_BASE + 0x264)

DCCMVAU: D-cache clean by MVA to Point of Unification.

Definition at line 179 of file scb.h.

◆ SCB_DCCSW

#define SCB_DCCSW MMIO32(SCB_BASE + 0x26C)

DCISW: D-cache clean by set-way.

Definition at line 185 of file scb.h.

◆ SCB_DCIMVAC

#define SCB_DCIMVAC MMIO32(SCB_BASE + 0x25C)

DCIMVAC: D-cache invalidate by MVA to Point of Coherency.

Definition at line 173 of file scb.h.

◆ SCB_DCISW

#define SCB_DCISW MMIO32(SCB_BASE + 0x260)

DCISW: D-cache invalidate by set-way.

Definition at line 176 of file scb.h.

◆ SCB_DFSR

#define SCB_DFSR MMIO32(SCB_BASE + 0x30)

DFSR: Debug Fault Status Register.

Definition at line 75 of file scb.h.

◆ SCB_FPCAR

#define SCB_FPCAR MMIO32(SCB_BASE + 0x238)

FPCAR: Floating-Point Context Address Register.

Definition at line 140 of file scb.h.

◆ SCB_FPCCR

#define SCB_FPCCR MMIO32(SCB_BASE + 0x234)

FPCCR: Floating-Point Context Control Register.

Definition at line 137 of file scb.h.

◆ SCB_FPDSCR

#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C)

FPDSCR: Floating-Point Default Status Control Register.

Definition at line 143 of file scb.h.

◆ SCB_HFSR

#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)

HFSR: Hard Fault Status Register.

Definition at line 83 of file scb.h.

◆ SCB_ICIALLU

#define SCB_ICIALLU MMIO32(SCB_BASE + 0x250)

ICIALLU: I-cache invalidate all to Point of Unification.

Definition at line 167 of file scb.h.

◆ SCB_ICIMVAU

#define SCB_ICIMVAU MMIO32(SCB_BASE + 0x258)

ICIMVAU: I-cache invalidate by MVA to Point of Unification.

Definition at line 170 of file scb.h.

◆ SCB_ICSR

#define SCB_ICSR MMIO32(SCB_BASE + 0x04)

ICSR: Interrupt Control State Register.

Definition at line 46 of file scb.h.

◆ SCB_ID_AFR0

#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C)

ID_AFR0: Auxiliary Features Register 0.

Definition at line 104 of file scb.h.

◆ SCB_ID_DFR0

#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48)

ID_DFR0: Debug Features Register 0.

Definition at line 101 of file scb.h.

◆ SCB_ID_ISAR0

#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60)

ID_ISAR0: Instruction Set Attributes Register 0.

Definition at line 119 of file scb.h.

◆ SCB_ID_ISAR1

#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64)

ID_ISAR1: Instruction Set Attributes Register 1.

Definition at line 122 of file scb.h.

◆ SCB_ID_ISAR2

#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68)

ID_ISAR2: Instruction Set Attributes Register 2.

Definition at line 125 of file scb.h.

◆ SCB_ID_ISAR3

#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C)

ID_ISAR3: Instruction Set Attributes Register 3.

Definition at line 128 of file scb.h.

◆ SCB_ID_ISAR4

#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70)

ID_ISAR4: Instruction Set Attributes Register 4.

Definition at line 131 of file scb.h.

◆ SCB_ID_MMFR0

#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50)

ID_MMFR0: Memory Model Feature Register 0.

Definition at line 107 of file scb.h.

◆ SCB_ID_MMFR1

#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54)

ID_MMFR1: Memory Model Feature Register 1.

Definition at line 110 of file scb.h.

◆ SCB_ID_MMFR2

#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58)

ID_MMFR2: Memory Model Feature Register 2.

Definition at line 113 of file scb.h.

◆ SCB_ID_MMFR3

#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C)

ID_MMFR3: Memory Model Feature Register 3.

Definition at line 116 of file scb.h.

◆ SCB_ID_PFR0

#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40)

ID_PFR0: Processor Feature Register 0.

Definition at line 95 of file scb.h.

◆ SCB_ID_PFR1

#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44)

ID_PFR1: Processor Feature Register 1.

Definition at line 98 of file scb.h.

◆ SCB_MMFAR

#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)

MMFAR: Memory Manage Fault Address Register.

Definition at line 86 of file scb.h.

◆ SCB_MVFR0

#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240)

MVFR0: Media and Floating-Point Feature Register 0.

Definition at line 146 of file scb.h.

◆ SCB_MVFR1

#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244)

MVFR1: Media and Floating-Point Feature Register 1.

Definition at line 149 of file scb.h.

◆ SCB_SCR

#define SCB_SCR MMIO32(SCB_BASE + 0x10)

SCR: System Control Register.

Definition at line 55 of file scb.h.

◆ SCB_SHCSR

#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)

SHCSR: System Handler Control and State Register.

Definition at line 72 of file scb.h.

◆ SCB_SHPR

#define SCB_SHPR ( ipr_id ) MMIO8(SCS_BASE + 0xD18 + (ipr_id))

System Handler Priority 8 bits Registers, SHPR1/2/3.

Note: : 12 8bit Registers; : 2 32bit Registers on CM0, requires word access, (shpr1 doesn't actually exist)

Definition at line 68 of file scb.h.

◆ SCB_VTOR

#define SCB_VTOR MMIO32(SCB_BASE + 0x08)

VTOR: Vector Table Offset Register.

Definition at line 49 of file scb.h.

Macros