libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
scb.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
5 * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
6 *
7 * This library is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU Lesser General Public License as published by
9 * the Free Software Foundation, either version 3 of the License, or
10 * (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public License
18 * along with this library. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef LIBOPENCM3_SCB_H
22#define LIBOPENCM3_SCB_H
23
24/**
25 * @defgroup cm_scb Cortex-M System Control Block
26 * @ingroup CM3_defines
27 *
28 * The System Control Block is a section of the System Control Space.
29 * Other members of the SCS are, for instance, DWT, ITM, SYSTICKK.
30 * The exact details of the SCB are defined in the "Architecture Reference
31 * Manual" for either ARMv7-M or ARMV6-m.
32 * @{
33 */
34#include <libopencm3/cm3/memorymap.h>
35#include <libopencm3/cm3/common.h>
36
37/** @defgroup cm_scb_registers SCB Registers
38 * @ingroup cm_scb
39 * @{
40 */
41
42/** CPUID: CPUID base register */
43#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
44
45/** ICSR: Interrupt Control State Register */
46#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
47
48/** VTOR: Vector Table Offset Register */
49#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
50
51/** AIRCR: Application Interrupt and Reset Control Register */
52#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
53
54/** SCR: System Control Register */
55#define SCB_SCR MMIO32(SCB_BASE + 0x10)
56
57/** CCR: Configuration Control Register */
58#define SCB_CCR MMIO32(SCB_BASE + 0x14)
59
60/** System Handler Priority 8 bits Registers, SHPR1/2/3.
61 * @note: 12 8bit Registers
62 * @note: 2 32bit Registers on CM0, requires word access,
63 * (shpr1 doesn't actually exist)
64 */
65#if defined(__ARM_ARCH_6M__)
66#define SCB_SHPR32(ipr_id) MMIO32(SCS_BASE + 0xD18 + ((ipr_id) * 4))
67#else
68#define SCB_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + (ipr_id))
69#endif
70
71/** SHCSR: System Handler Control and State Register */
72#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
73
74/** DFSR: Debug Fault Status Register */
75#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
76
77/* Those defined only on ARMv7 and above */
78#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
79/** CFSR: Configurable Fault Status Registers */
80#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
81
82/** HFSR: Hard Fault Status Register */
83#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
84
85/** MMFAR: Memory Manage Fault Address Register */
86#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
87
88/** BFAR: Bus Fault Address Register */
89#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
90
91/** AFSR: Auxiliary Fault Status Register */
92#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
93
94/** ID_PFR0: Processor Feature Register 0 */
95#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40)
96
97/** ID_PFR1: Processor Feature Register 1 */
98#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44)
99
100/** ID_DFR0: Debug Features Register 0 */
101#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48)
102
103/** ID_AFR0: Auxiliary Features Register 0 */
104#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C)
105
106/** ID_MMFR0: Memory Model Feature Register 0 */
107#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50)
108
109/** ID_MMFR1: Memory Model Feature Register 1 */
110#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54)
111
112/** ID_MMFR2: Memory Model Feature Register 2 */
113#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58)
114
115/** ID_MMFR3: Memory Model Feature Register 3 */
116#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C)
117
118/** ID_ISAR0: Instruction Set Attributes Register 0 */
119#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60)
120
121/** ID_ISAR1: Instruction Set Attributes Register 1 */
122#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64)
123
124/** ID_ISAR2: Instruction Set Attributes Register 2 */
125#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68)
126
127/** ID_ISAR3: Instruction Set Attributes Register 3 */
128#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C)
129
130/** ID_ISAR4: Instruction Set Attributes Register 4 */
131#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70)
132
133/** CPACR: Coprocessor Access Control Register */
134#define SCB_CPACR MMIO32(SCB_BASE + 0x88)
135
136/** FPCCR: Floating-Point Context Control Register */
137#define SCB_FPCCR MMIO32(SCB_BASE + 0x234)
138
139/** FPCAR: Floating-Point Context Address Register */
140#define SCB_FPCAR MMIO32(SCB_BASE + 0x238)
141
142/** FPDSCR: Floating-Point Default Status Control Register */
143#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C)
144
145/** MVFR0: Media and Floating-Point Feature Register 0 */
146#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240)
147
148/** MVFR1: Media and Floating-Point Feature Register 1 */
149#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244)
150#endif
151
152/* Those defined only on ARMv7EM and above */
153#if defined(__ARM_ARCH_7EM__)
154/** CLIDR: Cache Level ID Register */
155#define SCB_CLIDR MMIO32(SCB_BASE + 0x78)
156
157/** CTR: Cache Type Register */
158#define SCB_CTR MMIO32(SCB_BASE + 0x7C)
159
160/** CCSIDR: Cache Size ID Registers */
161#define SCB_CCSIDR MMIO32(SCB_BASE + 0x80)
162
163/** CSSELR: Cache Size Selection Register */
164#define SCB_CCSELR MMIO32(SCB_BASE + 0x84)
165
166/** ICIALLU: I-cache invalidate all to Point of Unification */
167#define SCB_ICIALLU MMIO32(SCB_BASE + 0x250)
168
169/** ICIMVAU: I-cache invalidate by MVA to Point of Unification */
170#define SCB_ICIMVAU MMIO32(SCB_BASE + 0x258)
171
172/** DCIMVAC: D-cache invalidate by MVA to Point of Coherency */
173#define SCB_DCIMVAC MMIO32(SCB_BASE + 0x25C)
174
175/** DCISW: D-cache invalidate by set-way */
176#define SCB_DCISW MMIO32(SCB_BASE + 0x260)
177
178/** DCCMVAU: D-cache clean by MVA to Point of Unification */
179#define SCB_DCCMVAU MMIO32(SCB_BASE + 0x264)
180
181/** DCCMVAC: D-cache clean by MVA to Point of Coherency */
182#define SCB_DCCMVAC MMIO32(SCB_BASE + 0x268)
183
184/** DCISW: D-cache clean by set-way */
185#define SCB_DCCSW MMIO32(SCB_BASE + 0x26C)
186
187/** DCCIMVAC: D-cache clean and invalidate by MVA to Point of Coherency */
188#define SCB_DCCIMVAC MMIO32(SCB_BASE + 0x270)
189
190/** DCCISW: D-cache clean and invalidate by set-way */
191#define SCB_DCCISW MMIO32(SCB_BASE + 0x274)
192
193/** BPIALL: Branch predictor invalidate all */
194#define SCB_BPIALL MMIO32(SCB_BASE + 0x278)
195#endif
196
197/**@}*/
198
199/* --- SCB values ---------------------------------------------------------- */
200
201/**
202 * @defgroup cm3_scb_cpuid_values SCB_CPUID Values
203 * @{
204 */
205/** Implementer[31:24]: Implementer code */
206#define SCB_CPUID_IMPLEMENTER_LSB 24
207#define SCB_CPUID_IMPLEMENTER (0xFF << SCB_CPUID_IMPLEMENTER_LSB)
208/** Variant[23:20]: Variant number */
209#define SCB_CPUID_VARIANT_LSB 20
210#define SCB_CPUID_VARIANT (0xF << SCB_CPUID_VARIANT_LSB)
211/** Constant[19:16]
212 * Reads as 0xF (ARMv7-M) M3, M4
213 * Reads as 0xC (ARMv6-M) M0, M0+
214 */
215#define SCB_CPUID_CONSTANT_LSB 16
216#define SCB_CPUID_CONSTANT (0xF << SCB_CPUID_CONSTANT_LSB)
217#define SCB_CPUID_CONSTANT_ARMV6 (0xC << SCB_CPUID_CONSTANT_LSB)
218#define SCB_CPUID_CONSTANT_ARMV7 (0xF << SCB_CPUID_CONSTANT_LSB)
219
220/** PartNo[15:4]: Part number of the processor */
221#define SCB_CPUID_PARTNO_LSB 4
222#define SCB_CPUID_PARTNO (0xFFF << SCB_CPUID_PARTNO_LSB)
223/** Revision[3:0]: Revision number */
224#define SCB_CPUID_REVISION_LSB 0
225#define SCB_CPUID_REVISION (0xF << SCB_CPUID_REVISION_LSB)
226/**@}*/
227
228/**
229 * @defgroup cm3_scb_icsr_values SCB_ICSR Values
230 * @{
231 */
232/** NMIPENDSET: NMI set-pending bit */
233#define SCB_ICSR_NMIPENDSET (1 << 31)
234/* Bits [30:29]: reserved - must be kept cleared */
235/** PENDSVSET: PendSV set-pending bit */
236#define SCB_ICSR_PENDSVSET (1 << 28)
237/** PENDSVCLR: PendSV clear-pending bit */
238#define SCB_ICSR_PENDSVCLR (1 << 27)
239/** PENDSTSET: SysTick exception set-pending bit */
240#define SCB_ICSR_PENDSTSET (1 << 26)
241/** PENDSTCLR: SysTick exception clear-pending bit */
242#define SCB_ICSR_PENDSTCLR (1 << 25)
243/* Bit 24: reserved - must be kept cleared */
244/** Bit 23: reserved for debug - reads as 0 when not in debug mode */
245#define SCB_ICSR_ISRPREEMPT (1 << 23)
246/** ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
247#define SCB_ICSR_ISRPENDING (1 << 22)
248/** VECTPENDING[21:12] Pending vector */
249#define SCB_ICSR_VECTPENDING_LSB 12
250#define SCB_ICSR_VECTPENDING (0x1FF << SCB_ICSR_VECTPENDING_LSB)
251/** RETOBASE: Return to base level */
252#define SCB_ICSR_RETOBASE (1 << 11)
253/* Bits [10:9]: reserved - must be kept cleared */
254/** VECTACTIVE[8:0] Active vector */
255#define SCB_ICSR_VECTACTIVE_LSB 0
256#define SCB_ICSR_VECTACTIVE (0x1FF << SCB_ICSR_VECTACTIVE_LSB)
257/**@}*/
258
259/**
260 * @defgroup cm3_scb_vtor_values SCB_VTOR Values
261 * @{
262 */
263
264/* IMPLEMENTATION DEFINED */
265
266#if defined(__ARM_ARCH_6M__)
267
268#define SCB_VTOR_TBLOFF_LSB 7
269#define SCB_VTOR_TBLOFF (0x1FFFFFF << SCB_VTOR_TBLOFF_LSB)
270
271#elif defined(CM1)
272/* VTOR not defined there */
273
274#elif defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
275
276/* Bits [31:30]: reserved - must be kept cleared */
277/* TBLOFF[29:9]: Vector table base offset field */
278/* inconsistent datasheet - LSB could be 11 */
279/* BUG: TBLOFF is in the ARMv6 Architecture reference manual defined from b7 */
280#define SCB_VTOR_TBLOFF_LSB 9
281#define SCB_VTOR_TBLOFF (0x7FFFFF << SCB_VTOR_TBLOFF_LSB)
282
283#endif
284/**@}*/
285
286
287/**
288 * @defgroup cm3_scb_aicr_values SCB_AICR Values
289 * @{
290 */
291/** VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
292#define SCB_AIRCR_VECTKEYSTAT_LSB 16
293#define SCB_AIRCR_VECTKEYSTAT (0xFFFF << SCB_AIRCR_VECTKEYSTAT_LSB)
294#define SCB_AIRCR_VECTKEY (0x05FA << SCB_AIRCR_VECTKEYSTAT_LSB)
295
296/** ENDIANNESS Data endianness bit */
297#define SCB_AIRCR_ENDIANESS (1 << 15)
298
299/* Those defined only on ARMv7 and above */
300#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
301/* Bits [14:11]: reserved - must be kept cleared */
302/** PRIGROUP[10:8]: Interrupt priority grouping field */
303#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)
304#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)
305#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8)
306#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8)
307#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8)
308#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)
309#define SCB_AIRCR_PRIGROUP_SHIFT 8
310/* Bits [7:3]: reserved - must be kept cleared */
311#endif
312
313/** SYSRESETREQ System reset request */
314#define SCB_AIRCR_SYSRESETREQ (1 << 2)
315/** VECTCLRACTIVE clears state information for exceptions */
316#define SCB_AIRCR_VECTCLRACTIVE (1 << 1)
317
318/* Those defined only on ARMv7 and above */
319#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
320/** VECTRESET cause local system reset */
321#define SCB_AIRCR_VECTRESET (1 << 0)
322#endif
323/**@}*/
324
325/**
326 * @defgroup cm3_scb_scr_values SCB_SCR Values
327 * @{
328 */
329/* Bits [31:5]: reserved - must be kept cleared */
330/** SEVONPEND Send Event on Pending bit */
331#define SCB_SCR_SEVONPEND (1 << 4)
332/* Bit 3: reserved - must be kept cleared */
333/** SLEEPDEEP implementation defined */
334#define SCB_SCR_SLEEPDEEP (1 << 2)
335/** SLEEPONEXIT sleep when exiting ISR */
336#define SCB_SCR_SLEEPONEXIT (1 << 1)
337/* Bit 0: reserved - must be kept cleared */
338/**@}*/
339
340/**
341 * @defgroup cm3_scb_ccr_values SCB_CCR Values
342 * @{
343 */
344/* Bits [31:10]: reserved - must be kept cleared */
345/** STKALIGN set to zero to break things :) */
346#define SCB_CCR_STKALIGN (1 << 9)
347
348/* Those defined only on ARMv7 and above */
349#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
350/** BFHFNMIGN set to attempt ignoring faults in handlers */
351#define SCB_CCR_BFHFNMIGN (1 << 8)
352/* Bits [7:5]: reserved - must be kept cleared */
353/** DIV_0_TRP set to trap on divide by zero*/
354#define SCB_CCR_DIV_0_TRP (1 << 4)
355#endif
356
357/** UNALIGN_TRP set to trap on unaligned */
358#define SCB_CCR_UNALIGN_TRP (1 << 3)
359
360/* Those defined only on ARMv7 and above */
361#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
362/* Bit 2: reserved - must be kept cleared */
363/** USERSETMPEND set to allow unprivileged access to STIR */
364#define SCB_CCR_USERSETMPEND (1 << 1)
365/** NONBASETHRDENA set to allow non base priority threads */
366#define SCB_CCR_NONBASETHRDENA (1 << 0)
367#endif
368
369/* Those defined only on ARMv7EM and above */
370#if defined(__ARM_ARCH_7EM__)
371/** BP set to enable branch predictor */
372#define SCB_CCR_BP (1 << 18)
373/** IC set to enable instruction cache */
374#define SCB_CCR_IC (1 << 17)
375/** DC set to enable data cache */
376#define SCB_CCR_DC (1 << 16)
377#endif
378
379/**@}*/
380
381/* These numbers are designed to be used with the SCB_SHPR() macro */
382/* SCB_SHPR1 */
383#define SCB_SHPR_PRI_4_MEMMANAGE 0
384#define SCB_SHPR_PRI_5_BUSFAULT 1
385#define SCB_SHPR_PRI_6_USAGEFAULT 2
386#define SCB_SHPR_PRI_7_RESERVED 3
387/* SCB_SHPR2 */
388#define SCB_SHPR_PRI_8_RESERVED 4
389#define SCB_SHPR_PRI_9_RESERVED 5
390#define SCB_SHPR_PRI_10_RESERVED 6
391#define SCB_SHPR_PRI_11_SVCALL 7
392/* SCB_SHPR3 */
393#define SCB_SHPR_PRI_12_RESERVED 8
394#define SCB_SHPR_PRI_13_RESERVED 9
395#define SCB_SHPR_PRI_14_PENDSV 10
396#define SCB_SHPR_PRI_15_SYSTICK 11
397
398/* --- SCB_SHCSR values ---------------------------------------------------- */
399
400/* Bits [31:19]: reserved - must be kept cleared */
401
402/* Those defined only on ARMv7 and above */
403#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
404/* USGFAULTENA: Usage fault enable */
405#define SCB_SHCSR_USGFAULTENA (1 << 18)
406/* BUSFAULTENA: Bus fault enable */
407#define SCB_SHCSR_BUSFAULTENA (1 << 17)
408/* MEMFAULTENA: Memory management fault enable */
409#define SCB_SHCSR_MEMFAULTENA (1 << 16)
410#endif
411
412/* SVCALLPENDED: SVC call pending */
413#define SCB_SHCSR_SVCALLPENDED (1 << 15)
414
415/* Those defined only on ARMv7 and above */
416#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
417/* BUSFAULTPENDED: Bus fault exception pending */
418#define SCB_SHCSR_BUSFAULTPENDED (1 << 14)
419/* MEMFAULTPENDED: Memory management fault exception pending */
420#define SCB_SHCSR_MEMFAULTPENDED (1 << 13)
421/* USGFAULTPENDED: Usage fault exception pending */
422#define SCB_SHCSR_USGFAULTPENDED (1 << 12)
423/* SYSTICKACT: SysTick exception active */
424#define SCB_SHCSR_SYSTICKACT (1 << 11)
425/* PENDSVACT: PendSV exception active */
426#define SCB_SHCSR_PENDSVACT (1 << 10)
427/* Bit 9: reserved - must be kept cleared */
428/* MONITORACT: Debug monitor active */
429#define SCB_SHCSR_MONITORACT (1 << 8)
430/* SVCALLACT: SVC call active */
431#define SCB_SHCSR_SVCALLACT (1 << 7)
432/* Bits [6:4]: reserved - must be kept cleared */
433/* USGFAULTACT: Usage fault exception active */
434#define SCB_SHCSR_USGFAULTACT (1 << 3)
435/* Bit 2: reserved - must be kept cleared */
436/* BUSFAULTACT: Bus fault exception active */
437#define SCB_SHCSR_BUSFAULTACT (1 << 1)
438/* MEMFAULTACT: Memory management fault exception active */
439#define SCB_SHCSR_MEMFAULTACT (1 << 0)
440
441/* --- SCB_CFSR values ----------------------------------------------------- */
442
443/* Bits [31:26]: reserved - must be kept cleared */
444/* DIVBYZERO: Divide by zero usage fault */
445#define SCB_CFSR_DIVBYZERO (1 << 25)
446/* UNALIGNED: Unaligned access usage fault */
447#define SCB_CFSR_UNALIGNED (1 << 24)
448/* Bits [23:20]: reserved - must be kept cleared */
449/* NOCP: No coprocessor usage fault */
450#define SCB_CFSR_NOCP (1 << 19)
451/* INVPC: Invalid PC load usage fault */
452#define SCB_CFSR_INVPC (1 << 18)
453/* INVSTATE: Invalid state usage fault */
454#define SCB_CFSR_INVSTATE (1 << 17)
455/* UNDEFINSTR: Undefined instruction usage fault */
456#define SCB_CFSR_UNDEFINSTR (1 << 16)
457/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */
458#define SCB_CFSR_BFARVALID (1 << 15)
459/* Bits [14:13]: reserved - must be kept cleared */
460/* STKERR: Bus fault on stacking for exception entry */
461#define SCB_CFSR_STKERR (1 << 12)
462/* UNSTKERR: Bus fault on unstacking for a return from exception */
463#define SCB_CFSR_UNSTKERR (1 << 11)
464/* IMPRECISERR: Imprecise data bus error */
465#define SCB_CFSR_IMPRECISERR (1 << 10)
466/* PRECISERR: Precise data bus error */
467#define SCB_CFSR_PRECISERR (1 << 9)
468/* IBUSERR: Instruction bus error */
469#define SCB_CFSR_IBUSERR (1 << 8)
470/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */
471#define SCB_CFSR_MMARVALID (1 << 7)
472/* Bits [6:5]: reserved - must be kept cleared */
473/* MSTKERR: Memory manager fault on stacking for exception entry */
474#define SCB_CFSR_MSTKERR (1 << 4)
475/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */
476#define SCB_CFSR_MUNSTKERR (1 << 3)
477/* Bit 2: reserved - must be kept cleared */
478/* DACCVIOL: Data access violation flag */
479#define SCB_CFSR_DACCVIOL (1 << 1)
480/* IACCVIOL: Instruction access violation flag */
481#define SCB_CFSR_IACCVIOL (1 << 0)
482
483/* --- SCB_HFSR values ----------------------------------------------------- */
484
485/* DEBUG_VT: reserved for debug use */
486#define SCB_HFSR_DEBUG_VT (1 << 31)
487/* FORCED: Forced hard fault */
488#define SCB_HFSR_FORCED (1 << 30)
489/* Bits [29:2]: reserved - must be kept cleared */
490/* VECTTBL: Vector table hard fault */
491#define SCB_HFSR_VECTTBL (1 << 1)
492/* Bit 0: reserved - must be kept cleared */
493
494/* --- SCB_MMFAR values ---------------------------------------------------- */
495
496/* MMFAR [31:0]: Memory management fault address */
497
498/* --- SCB_BFAR values ----------------------------------------------------- */
499
500/* BFAR [31:0]: Bus fault address */
501
502#if defined(__ARM_ARCH_7EM__)
503/* --- SCB_CTR values ------------------------------------------------------ */
504/* FORMAT: implemented CTR format */
505#define SCB_CTR_FORMAT_SHIFT 29
506#define SCB_CTR_FORMAT_MASK 0x7
507/* CWG: Cache Write-back Granule */
508#define SCB_CTR_CWG_SHIFT 24
509#define SCB_CTR_CWG_MASK 0xf
510/* ERG: Exclusives Reservation Granule */
511#define SCB_CTR_ERG_SHIFT 20
512#define SCB_CTR_ERG_MASK 0xf
513/* DMINLINE: log2 of number of words in smallest cache line of all data caches */
514#define SCB_CTR_DMINLINE_SHIFT 16
515#define SCB_CTR_DMINLINE_MASK 0x1f
516/* IMINLINE: log2 of number of words in smallest cache line of all instruction caches */
517#define SCB_CTR_IMINLINE_SHIFT 0
518#define SCB_CTR_IMINLINE_MASK 0xf
519
520#endif
521
522/* --- SCB_CPACR values ---------------------------------------------------- */
523
524/* CPACR CPn: Access privileges values */
525#define SCB_CPACR_NONE 0 /* Access denied */
526#define SCB_CPACR_PRIV 1 /* Privileged access only */
527#define SCB_CPACR_FULL 3 /* Full access */
528
529/* CPACR [20:21]: Access privileges for coprocessor 10 */
530#define SCB_CPACR_CP10 (1 << 20)
531/* CPACR [22:23]: Access privileges for coprocessor 11 */
532#define SCB_CPACR_CP11 (1 << 22)
533#endif
534
535/* --- SCB functions ------------------------------------------------------- */
536
537BEGIN_DECLS
538
539struct scb_exception_stack_frame {
540 uint32_t r0;
541 uint32_t r1;
542 uint32_t r2;
543 uint32_t r3;
544 uint32_t r12;
545 uint32_t lr;
546 uint32_t pc;
547 uint32_t xpsr;
548} __attribute__((packed));
549
550#define SCB_GET_EXCEPTION_STACK_FRAME(f) \
551 do { \
552 __asm__ volatile ("mov %[frameptr], sp" \
553 : [frameptr]"=r" (f)); \
554 } while (0)
555
556void scb_reset_system(void) __attribute__((noreturn));
557
558/* Those defined only on ARMv7 and above */
559#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
560void scb_reset_core(void) __attribute__((noreturn));
561void scb_set_priority_grouping(uint32_t prigroup);
562#endif
563
564END_DECLS
565
566/**@}*/
567
568#endif
END_DECLS
#define END_DECLS
Definition: common.h:34
BEGIN_DECLS
#define BEGIN_DECLS
Definition: common.h:33
scb_set_priority_grouping
void scb_set_priority_grouping(uint32_t prigroup)
Definition: scb.c:63
scb_reset_core
void scb_reset_core(void)
Definition: scb.c:46
scb_reset_system
void scb_reset_system(void)
Definition: scb.c:54
scb_exception_stack_frame
Definition: scb.h:539
scb_exception_stack_frame::r12
uint32_t r12
Definition: scb.h:544
scb_exception_stack_frame::xpsr
uint32_t xpsr
Definition: scb.h:547
scb_exception_stack_frame::pc
uint32_t pc
Definition: scb.h:546
scb_exception_stack_frame::r3
uint32_t r3
Definition: scb.h:543
scb_exception_stack_frame::r1
uint32_t r1
Definition: scb.h:541
scb_exception_stack_frame::r2
uint32_t r2
Definition: scb.h:542
scb_exception_stack_frame::lr
uint32_t lr
Definition: scb.h:545
scb_exception_stack_frame::r0
uint32_t r0
Definition: scb.h:540