libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
RCC peripheral API

libopencm3 STM32F4xx Reset and Clock Control More...

Collaboration diagram for RCC peripheral API:

Macros

#define _RCC_REG(i)   MMIO32(RCC_BASE + ((i) >> 5))
 
#define _RCC_BIT(i)   (1 << ((i) & 0x1f))
 

Functions

void rcc_peripheral_enable_clock (volatile uint32_t *reg, uint32_t en)
 RCC Enable Peripheral Clocks. More...
 
void rcc_peripheral_disable_clock (volatile uint32_t *reg, uint32_t en)
 RCC Disable Peripheral Clocks. More...
 
void rcc_peripheral_reset (volatile uint32_t *reg, uint32_t reset)
 RCC Reset Peripherals. More...
 
void rcc_peripheral_clear_reset (volatile uint32_t *reg, uint32_t clear_reset)
 RCC Remove Reset on Peripherals. More...
 
void rcc_periph_clock_enable (enum rcc_periph_clken clken)
 Enable Peripheral Clock in running mode. More...
 
void rcc_periph_clock_disable (enum rcc_periph_clken clken)
 Disable Peripheral Clock in running mode. More...
 
void rcc_periph_reset_pulse (enum rcc_periph_rst rst)
 Reset Peripheral, pulsed. More...
 
void rcc_periph_reset_hold (enum rcc_periph_rst rst)
 Reset Peripheral, hold. More...
 
void rcc_periph_reset_release (enum rcc_periph_rst rst)
 Reset Peripheral, release. More...
 
void rcc_set_mco (uint32_t mcosrc)
 Select the source of Microcontroller Clock Output. More...
 
void rcc_osc_bypass_enable (enum rcc_osc osc)
 RCC Enable Bypass. More...
 
void rcc_osc_bypass_disable (enum rcc_osc osc)
 RCC Disable Bypass. More...
 
uint16_t rcc_get_div_from_hpre (uint8_t div_val)
 This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers. More...
 
void rcc_osc_ready_int_clear (enum rcc_osc osc)
 
void rcc_osc_ready_int_enable (enum rcc_osc osc)
 
void rcc_osc_ready_int_disable (enum rcc_osc osc)
 
int rcc_osc_ready_int_flag (enum rcc_osc osc)
 
void rcc_css_int_clear (void)
 
int rcc_css_int_flag (void)
 
bool rcc_is_osc_ready (enum rcc_osc osc)
 Is the given oscillator ready? More...
 
void rcc_wait_for_osc_ready (enum rcc_osc osc)
 Wait for Oscillator Ready. More...
 
void rcc_wait_for_sysclk_status (enum rcc_osc osc)
 
void rcc_osc_on (enum rcc_osc osc)
 
void rcc_osc_off (enum rcc_osc osc)
 
void rcc_css_enable (void)
 
void rcc_css_disable (void)
 
void rcc_plli2s_config (uint16_t n, uint8_t r)
 Set the dividers for the PLLI2S clock outputs. More...
 
void rcc_pllsai_config (uint16_t n, uint16_t p, uint16_t q, uint16_t r)
 Set the dividers for the PLLSAI clock outputs divider p is only available on F4x9 parts, pass 0 for other parts. More...
 
void rcc_pllsai_postscalers (uint8_t q, uint8_t r)
 Set the dedicated dividers after the PLLSAI configuration. More...
 
void rcc_set_sysclk_source (uint32_t clk)
 
void rcc_set_pll_source (uint32_t pllsrc)
 
void rcc_set_ppre2 (uint32_t ppre2)
 
void rcc_set_ppre1 (uint32_t ppre1)
 
void rcc_set_hpre (uint32_t hpre)
 
void rcc_set_rtcpre (uint32_t rtcpre)
 
void rcc_set_main_pll_hsi (uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq, uint32_t pllr)
 Reconfigures the main PLL for a HSI source. More...
 
void rcc_set_main_pll_hse (uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq, uint32_t pllr)
 Reconfigures the main PLL for a HSE source. More...
 
uint32_t rcc_system_clock_source (void)
 
void rcc_clock_setup_pll (const struct rcc_clock_scale *clock)
 Setup clocks to run from PLL. More...
 
void rcc_clock_setup_hse_3v3 (const struct rcc_clock_scale *clock)
 Setup clocks with the HSE. More...
 
uint32_t rcc_get_usart_clk_freq (uint32_t usart)
 Get the peripheral clock speed for the USART at base specified. More...
 
uint32_t rcc_get_timer_clk_freq (uint32_t timer)
 Get the peripheral clock speed for the Timer at base specified. More...
 
uint32_t rcc_get_i2c_clk_freq (uint32_t i2c)
 Get the peripheral clock speed for the I2C device at base specified. More...
 
uint32_t rcc_get_spi_clk_freq (uint32_t spi)
 Get the peripheral clock speed for the SPI device at base specified. More...
 

Variables

uint32_t rcc_ahb_frequency = 16000000
 
uint32_t rcc_apb1_frequency = 16000000
 
uint32_t rcc_apb2_frequency = 16000000
 
const struct rcc_clock_scale rcc_hsi_configs [RCC_CLOCK_3V3_END]
 
const struct rcc_clock_scale rcc_hse_8mhz_3v3 [RCC_CLOCK_3V3_END]
 
const struct rcc_clock_scale rcc_hse_12mhz_3v3 [RCC_CLOCK_3V3_END]
 
const struct rcc_clock_scale rcc_hse_16mhz_3v3 [RCC_CLOCK_3V3_END]
 
const struct rcc_clock_scale rcc_hse_25mhz_3v3 [RCC_CLOCK_3V3_END]
 

Detailed Description

libopencm3 STM32F4xx Reset and Clock Control

Reset and Clock Control API.

Author
© 2013 Frantisek Burian <BuFran at seznam.cz>
Date
18 Jun 2013

This library supports the Reset and Clock Control System in the STM32 series of ARM Cortex Microcontrollers by ST Microelectronics.

LGPL License Terms libopencm3 License

Macro Definition Documentation

◆ _RCC_BIT

#define _RCC_BIT (   i)    (1 << ((i) & 0x1f))

Definition at line 122 of file rcc_common_all.c.

◆ _RCC_REG

#define _RCC_REG (   i)    MMIO32(RCC_BASE + ((i) >> 5))

Definition at line 121 of file rcc_common_all.c.

Function Documentation

◆ rcc_clock_setup_hse_3v3()

void rcc_clock_setup_hse_3v3 ( const struct rcc_clock_scale clock)

Setup clocks with the HSE.

Deprecated:
replaced by rcc_clock_setup_pll as a drop in replacement.
See also
rcc_clock_setup_pll which supports HSI as well as HSE, using the same clock structures.

Definition at line 789 of file rcc.c.

References rcc_clock_setup_pll().

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◆ rcc_clock_setup_pll()

◆ rcc_css_disable()

void rcc_css_disable ( void  )

Definition at line 540 of file rcc.c.

References RCC_CR, and RCC_CR_CSSON.

◆ rcc_css_enable()

void rcc_css_enable ( void  )

Definition at line 535 of file rcc.c.

References RCC_CR, and RCC_CR_CSSON.

◆ rcc_css_int_clear()

void rcc_css_int_clear ( void  )

Definition at line 424 of file rcc.c.

References RCC_CIR, and RCC_CIR_CSSC.

◆ rcc_css_int_flag()

int rcc_css_int_flag ( void  )

Definition at line 429 of file rcc.c.

References RCC_CIR, and RCC_CIR_CSSF.

◆ rcc_get_div_from_hpre()

uint16_t rcc_get_div_from_hpre ( uint8_t  div_val)

This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers.

Parameters
div_valMasked and shifted divider value from register (e.g. RCC_CFGR)

Definition at line 276 of file rcc_common_all.c.

◆ rcc_get_i2c_clk_freq()

uint32_t rcc_get_i2c_clk_freq ( uint32_t  i2c)

Get the peripheral clock speed for the I2C device at base specified.

Parameters
i2cBase address of I2C to get clock frequency for.

Definition at line 830 of file rcc.c.

References rcc_apb1_frequency.

◆ rcc_get_spi_clk_freq()

uint32_t rcc_get_spi_clk_freq ( uint32_t  spi)

Get the peripheral clock speed for the SPI device at base specified.

Parameters
spiBase address of SPI device to get clock frequency for (e.g. SPI1_BASE).

Definition at line 839 of file rcc.c.

References rcc_apb1_frequency, rcc_apb2_frequency, SPI2_BASE, and SPI3_BASE.

◆ rcc_get_timer_clk_freq()

uint32_t rcc_get_timer_clk_freq ( uint32_t  timer)

Get the peripheral clock speed for the Timer at base specified.

Parameters
timerBase address of TIM to get clock frequency for.

Definition at line 812 of file rcc.c.

References rcc_clock_scale::ppre1, rcc_clock_scale::ppre2, rcc_apb1_frequency, rcc_apb2_frequency, RCC_CFGR, RCC_CFGR_PPRE1_MASK, RCC_CFGR_PPRE1_SHIFT, RCC_CFGR_PPRE2_MASK, RCC_CFGR_PPRE2_SHIFT, RCC_CFGR_PPRE_DIV_NONE, TIM14_BASE, and TIM2_BASE.

◆ rcc_get_usart_clk_freq()

uint32_t rcc_get_usart_clk_freq ( uint32_t  usart)

Get the peripheral clock speed for the USART at base specified.

Parameters
usartBase address of USART to get clock frequency for.

Definition at line 798 of file rcc.c.

References rcc_apb1_frequency, rcc_apb2_frequency, USART1_BASE, and USART6_BASE.

◆ rcc_is_osc_ready()

bool rcc_is_osc_ready ( enum rcc_osc  osc)

Is the given oscillator ready?

Parameters
oscOscillator ID
Returns
true if the hardware indicates the oscillator is ready.

Definition at line 434 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSERDY, RCC_CR, RCC_CR_HSERDY, RCC_CR_HSIRDY, RCC_CR_PLLI2SRDY, RCC_CR_PLLRDY, RCC_CR_PLLSAIRDY, RCC_CSR, RCC_CSR_LSIRDY, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_PLL, RCC_PLLI2S, and RCC_PLLSAI.

Referenced by rcc_wait_for_osc_ready().

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◆ rcc_osc_bypass_disable()

void rcc_osc_bypass_disable ( enum rcc_osc  osc)

RCC Disable Bypass.

Re-enable the internal clock (high speed and low speed clocks only). The internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note
The LSE clock is in the backup domain and cannot have bypass removed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect) or the backup domain has been reset (see rcc_backupdomain_reset).
Parameters
[in]oscOscillator ID. Only HSE and LSE have effect.

Definition at line 254 of file rcc_common_all.c.

References RCC_BDCR, RCC_BDCR_LSEBYP, RCC_CR, RCC_CR_HSEBYP, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_bypass_enable()

void rcc_osc_bypass_enable ( enum rcc_osc  osc)

RCC Enable Bypass.

Enable an external clock to bypass the internal clock (high speed and low speed clocks only). The external clock must be enabled (see rcc_osc_on) and the internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note
The LSE clock is in the backup domain and cannot be bypassed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect).
Parameters
[in]oscOscillator ID. Only HSE and LSE have effect.

Definition at line 224 of file rcc_common_all.c.

References RCC_BDCR, RCC_BDCR_LSEBYP, RCC_CR, RCC_CR_HSEBYP, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_off()

void rcc_osc_off ( enum rcc_osc  osc)

Definition at line 508 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSEON, RCC_CR, RCC_CR_HSEON, RCC_CR_HSION, RCC_CR_PLLI2SON, RCC_CR_PLLON, RCC_CR_PLLSAION, RCC_CSR, RCC_CSR_LSION, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_PLL, RCC_PLLI2S, and RCC_PLLSAI.

Referenced by rcc_clock_setup_pll().

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◆ rcc_osc_on()

void rcc_osc_on ( enum rcc_osc  osc)

Definition at line 481 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSEON, RCC_CR, RCC_CR_HSEON, RCC_CR_HSION, RCC_CR_PLLI2SON, RCC_CR_PLLON, RCC_CR_PLLSAION, RCC_CSR, RCC_CSR_LSION, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI, RCC_PLL, RCC_PLLI2S, and RCC_PLLSAI.

Referenced by rcc_clock_setup_pll().

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◆ rcc_osc_ready_int_clear()

◆ rcc_osc_ready_int_disable()

◆ rcc_osc_ready_int_enable()

◆ rcc_osc_ready_int_flag()

◆ rcc_periph_clock_disable()

void rcc_periph_clock_disable ( enum rcc_periph_clken  clken)

Disable Peripheral Clock in running mode.

Disable the clock on particular peripheral.

Parameters
[in]clkenrcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 148 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_clock_enable()

void rcc_periph_clock_enable ( enum rcc_periph_clken  clken)

Enable Peripheral Clock in running mode.

Enable the clock on particular peripheral.

Parameters
[in]clkenrcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 134 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

Referenced by rcc_clock_setup_pll(), stm32f107_usbd_init(), and stm32f207_usbd_init().

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◆ rcc_periph_reset_hold()

void rcc_periph_reset_hold ( enum rcc_periph_rst  rst)

Reset Peripheral, hold.

Reset particular peripheral, and hold in reset state.

Parameters
[in]rstrcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 179 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_pulse()

void rcc_periph_reset_pulse ( enum rcc_periph_rst  rst)

Reset Peripheral, pulsed.

Reset particular peripheral, and restore to working state.

Parameters
[in]rstrcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 163 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

Referenced by can_reset(), i2c_reset(), and spi_reset().

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◆ rcc_periph_reset_release()

void rcc_periph_reset_release ( enum rcc_periph_rst  rst)

Reset Peripheral, release.

Restore peripheral from reset state to working state.

Parameters
[in]rstrcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 194 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_peripheral_clear_reset()

void rcc_peripheral_clear_reset ( volatile uint32_t *  reg,
uint32_t  clear_reset 
)

RCC Remove Reset on Peripherals.

Remove the reset on particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could have the reset removed simultaneously only if they are controlled by the same register.

See also
rcc_periph_reset_release for a less error prone version, if you only need to unreset a single peripheral.
rcc_periph_reset_pulse if you are only going to toggle reset anyway.
Parameters
[in]*regUnsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]clear_resetUnsigned int32. Logical OR of all resets to be removed:

Definition at line 116 of file rcc_common_all.c.

◆ rcc_peripheral_disable_clock()

void rcc_peripheral_disable_clock ( volatile uint32_t *  reg,
uint32_t  en 
)

RCC Disable Peripheral Clocks.

Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be disabled simultaneously only if they are controlled by the same register.

See also
rcc_periph_clock_disable for a less error prone version, if you only need to disable a single peripheral.
Parameters
[in]*regUnsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]enUnsigned int32. Logical OR of all enables to be used for disabling.

Definition at line 69 of file rcc_common_all.c.

◆ rcc_peripheral_enable_clock()

void rcc_peripheral_enable_clock ( volatile uint32_t *  reg,
uint32_t  en 
)

RCC Enable Peripheral Clocks.

Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be enabled simultaneously only if they are controlled by the same register.

See also
rcc_periph_clock_enable for a less error prone version, if you only need to enable a single peripheral.
Parameters
[in]*regUnsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]enUnsigned int32. Logical OR of all enables to be set

Definition at line 46 of file rcc_common_all.c.

◆ rcc_peripheral_reset()

void rcc_peripheral_reset ( volatile uint32_t *  reg,
uint32_t  reset 
)

RCC Reset Peripherals.

Reset particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could be reset simultaneously only if they are controlled by the same register.

See also
rcc_periph_reset_hold for a less error prone version, if you only need to reset a single peripheral.
rcc_periph_reset_pulse if you are only going to toggle reset anyway.
Parameters
[in]*regUnsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]resetUnsigned int32. Logical OR of all resets.

Definition at line 92 of file rcc_common_all.c.

◆ rcc_plli2s_config()

void rcc_plli2s_config ( uint16_t  n,
uint8_t  r 
)

Set the dividers for the PLLI2S clock outputs.

Parameters
nvalid range depends on target device, check your RefManual.
rvalid range is 2..7

Definition at line 550 of file rcc.c.

References RCC_PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_MASK, RCC_PLLI2SCFGR_PLLI2SN_SHIFT, RCC_PLLI2SCFGR_PLLI2SR_MASK, and RCC_PLLI2SCFGR_PLLI2SR_SHIFT.

◆ rcc_pllsai_config()

void rcc_pllsai_config ( uint16_t  n,
uint16_t  p,
uint16_t  q,
uint16_t  r 
)

Set the dividers for the PLLSAI clock outputs divider p is only available on F4x9 parts, pass 0 for other parts.

Parameters
nvalid range is 49..432
p0 if unused, PLLSAICFGR PLLSAIP values
qvalid range is 2..15
rvalid range is 2..7
See also
rcc_pllsai_postscalers

Definition at line 566 of file rcc.c.

References RCC_PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN_MASK, RCC_PLLSAICFGR_PLLSAIN_SHIFT, RCC_PLLSAICFGR_PLLSAIP_MASK, RCC_PLLSAICFGR_PLLSAIP_SHIFT, RCC_PLLSAICFGR_PLLSAIQ_MASK, RCC_PLLSAICFGR_PLLSAIQ_SHIFT, RCC_PLLSAICFGR_PLLSAIR_MASK, and RCC_PLLSAICFGR_PLLSAIR_SHIFT.

◆ rcc_pllsai_postscalers()

void rcc_pllsai_postscalers ( uint8_t  q,
uint8_t  r 
)

Set the dedicated dividers after the PLLSAI configuration.

Parameters
qdedicated PLLSAI divider, for either A or B
rdedicated LCD-TFT divider, see LTDC
See also
rcc_pllsai_config

Definition at line 583 of file rcc.c.

References RCC_DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ_MASK, RCC_DCKCFGR_PLLSAIDIVQ_SHIFT, RCC_DCKCFGR_PLLSAIDIVR_MASK, and RCC_DCKCFGR_PLLSAIDIVR_SHIFT.

◆ rcc_set_hpre()

void rcc_set_hpre ( uint32_t  hpre)

Definition at line 629 of file rcc.c.

References rcc_clock_scale::hpre, and RCC_CFGR.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_main_pll_hse()

void rcc_set_main_pll_hse ( uint32_t  pllm,
uint32_t  plln,
uint32_t  pllp,
uint32_t  pllq,
uint32_t  pllr 
)

Reconfigures the main PLL for a HSE source.

Any reserved bits are kept at their reset values.

Parameters
pllmDivider for the main PLL input clock
pllnMain PLL multiplication factor for VCO
pllpMain PLL divider for main system clock
pllqMain PLL divider for USB OTG FS, SDMMC & RNG
pllrMain PLL divider for DSI (for parts without DSI, provide 0 here)

Definition at line 680 of file rcc.c.

References rcc_clock_scale::pllm, rcc_clock_scale::plln, rcc_clock_scale::pllp, rcc_clock_scale::pllq, rcc_clock_scale::pllr, RCC_PLLCFGR, RCC_PLLCFGR_PLLM_MASK, RCC_PLLCFGR_PLLM_SHIFT, RCC_PLLCFGR_PLLN_MASK, RCC_PLLCFGR_PLLN_SHIFT, RCC_PLLCFGR_PLLP_MASK, RCC_PLLCFGR_PLLP_SHIFT, RCC_PLLCFGR_PLLQ_MASK, RCC_PLLCFGR_PLLQ_SHIFT, RCC_PLLCFGR_PLLR_MASK, RCC_PLLCFGR_PLLR_SHIFT, and RCC_PLLCFGR_PLLSRC.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_main_pll_hsi()

void rcc_set_main_pll_hsi ( uint32_t  pllm,
uint32_t  plln,
uint32_t  pllp,
uint32_t  pllq,
uint32_t  pllr 
)

Reconfigures the main PLL for a HSI source.

Any reserved bits are kept at their reset values.

Parameters
pllmDivider for the main PLL input clock
pllnMain PLL multiplication factor for VCO
pllpMain PLL divider for main system clock
pllqMain PLL divider for USB OTG FS, SDMMC & RNG
pllrMain PLL divider for DSI (for parts without DSI, provide 0 here)

Definition at line 656 of file rcc.c.

References rcc_clock_scale::pllm, rcc_clock_scale::plln, rcc_clock_scale::pllp, rcc_clock_scale::pllq, rcc_clock_scale::pllr, RCC_PLLCFGR, RCC_PLLCFGR_PLLM_MASK, RCC_PLLCFGR_PLLM_SHIFT, RCC_PLLCFGR_PLLN_MASK, RCC_PLLCFGR_PLLN_SHIFT, RCC_PLLCFGR_PLLP_MASK, RCC_PLLCFGR_PLLP_SHIFT, RCC_PLLCFGR_PLLQ_MASK, RCC_PLLCFGR_PLLQ_SHIFT, RCC_PLLCFGR_PLLR_MASK, and RCC_PLLCFGR_PLLR_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_mco()

void rcc_set_mco ( uint32_t  mcosrc)

Select the source of Microcontroller Clock Output.

Exact sources available depend on your target. On devices with multiple MCO pins, this function controls MCO1

Parameters
[in]mcosrcthe unshifted source bits

Definition at line 207 of file rcc_common_all.c.

References RCC_CFGR, RCC_CFGR_MCO_MASK, and RCC_CFGR_MCO_SHIFT.

◆ rcc_set_pll_source()

void rcc_set_pll_source ( uint32_t  pllsrc)

Definition at line 602 of file rcc.c.

References RCC_PLLCFGR.

◆ rcc_set_ppre1()

void rcc_set_ppre1 ( uint32_t  ppre1)

Definition at line 620 of file rcc.c.

References rcc_clock_scale::ppre1, and RCC_CFGR.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_ppre2()

void rcc_set_ppre2 ( uint32_t  ppre2)

Definition at line 611 of file rcc.c.

References rcc_clock_scale::ppre2, and RCC_CFGR.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_rtcpre()

void rcc_set_rtcpre ( uint32_t  rtcpre)

Definition at line 638 of file rcc.c.

References RCC_CFGR.

◆ rcc_set_sysclk_source()

void rcc_set_sysclk_source ( uint32_t  clk)

Definition at line 593 of file rcc.c.

References RCC_CFGR.

Referenced by rcc_clock_setup_pll().

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◆ rcc_system_clock_source()

uint32_t rcc_system_clock_source ( void  )

Definition at line 695 of file rcc.c.

References RCC_CFGR.

◆ rcc_wait_for_osc_ready()

void rcc_wait_for_osc_ready ( enum rcc_osc  osc)

Wait for Oscillator Ready.

Block until the hardware indicates that the Oscillator is ready.

Parameters
oscOscillator ID

Definition at line 455 of file rcc.c.

References rcc_is_osc_ready().

Referenced by rcc_clock_setup_pll().

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◆ rcc_wait_for_sysclk_status()

void rcc_wait_for_sysclk_status ( enum rcc_osc  osc)

Definition at line 460 of file rcc.c.

References RCC_CFGR, RCC_CFGR_SWS_HSE, RCC_CFGR_SWS_HSI, RCC_CFGR_SWS_MASK, RCC_CFGR_SWS_PLL, RCC_CFGR_SWS_SHIFT, RCC_HSE, RCC_HSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll().

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Variable Documentation

◆ rcc_ahb_frequency

uint32_t rcc_ahb_frequency = 16000000

Definition at line 48 of file rcc.c.

Referenced by rcc_clock_setup_pll().

◆ rcc_apb1_frequency

uint32_t rcc_apb1_frequency = 16000000

◆ rcc_apb2_frequency

uint32_t rcc_apb2_frequency = 16000000

◆ rcc_hse_12mhz_3v3

const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END]

Definition at line 50 of file rcc.c.

◆ rcc_hse_16mhz_3v3

const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END]

Definition at line 50 of file rcc.c.

◆ rcc_hse_25mhz_3v3

const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END]

Definition at line 50 of file rcc.c.

◆ rcc_hse_8mhz_3v3

const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END]

Definition at line 50 of file rcc.c.

◆ rcc_hsi_configs

const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END]

Definition at line 50 of file rcc.c.