libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
stm32/f4/memorymap.h File Reference
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Macros

#define FLASH_BASE   (0x08000000U)
 
#define PERIPH_BASE   (0x40000000U)
 
#define PERIPH_BASE_APB1   (PERIPH_BASE + 0x00000)
 
#define PERIPH_BASE_APB2   (PERIPH_BASE + 0x10000)
 
#define PERIPH_BASE_AHB1   (PERIPH_BASE + 0x20000)
 
#define PERIPH_BASE_AHB2   0x50000000U
 
#define PERIPH_BASE_AHB3   0x60000000U
 
#define TIM2_BASE   (PERIPH_BASE_APB1 + 0x0000)
 
#define TIM3_BASE   (PERIPH_BASE_APB1 + 0x0400)
 
#define TIM4_BASE   (PERIPH_BASE_APB1 + 0x0800)
 
#define TIM5_BASE   (PERIPH_BASE_APB1 + 0x0c00)
 
#define TIM6_BASE   (PERIPH_BASE_APB1 + 0x1000)
 
#define TIM7_BASE   (PERIPH_BASE_APB1 + 0x1400)
 
#define TIM12_BASE   (PERIPH_BASE_APB1 + 0x1800)
 
#define TIM13_BASE   (PERIPH_BASE_APB1 + 0x1c00)
 
#define TIM14_BASE   (PERIPH_BASE_APB1 + 0x2000)
 
#define LPTIM1_BASE   (PERIPH_BASE_APB1 + 0x2400)
 
#define RTC_BASE   (PERIPH_BASE_APB1 + 0x2800)
 
#define WWDG_BASE   (PERIPH_BASE_APB1 + 0x2c00)
 
#define IWDG_BASE   (PERIPH_BASE_APB1 + 0x3000)
 
#define I2S2_EXT_BASE   (PERIPH_BASE_APB1 + 0x3400)
 
#define SPI2_BASE   (PERIPH_BASE_APB1 + 0x3800)
 
#define SPI3_BASE   (PERIPH_BASE_APB1 + 0x3c00)
 
#define I2S3_EXT_BASE   (PERIPH_BASE_APB1 + 0x4000)
 
#define USART2_BASE   (PERIPH_BASE_APB1 + 0x4400)
 
#define USART3_BASE   (PERIPH_BASE_APB1 + 0x4800)
 
#define UART4_BASE   (PERIPH_BASE_APB1 + 0x4c00)
 
#define UART5_BASE   (PERIPH_BASE_APB1 + 0x5000)
 
#define I2C1_BASE   (PERIPH_BASE_APB1 + 0x5400)
 
#define I2C2_BASE   (PERIPH_BASE_APB1 + 0x5800)
 
#define I2C3_BASE   (PERIPH_BASE_APB1 + 0x5C00)
 
#define FMPI2C1_BASE   (PERIPH_BASE_APB1 + 0x6000)
 
#define BX_CAN1_BASE   (PERIPH_BASE_APB1 + 0x6400)
 
#define BX_CAN2_BASE   (PERIPH_BASE_APB1 + 0x6800)
 
#define POWER_CONTROL_BASE   (PERIPH_BASE_APB1 + 0x7000)
 
#define DAC_BASE   (PERIPH_BASE_APB1 + 0x7400)
 
#define UART7_BASE   (PERIPH_BASE_APB1 + 0x7800)
 
#define UART8_BASE   (PERIPH_BASE_APB1 + 0x7c00)
 
#define TIM1_BASE   (PERIPH_BASE_APB2 + 0x0000)
 
#define TIM8_BASE   (PERIPH_BASE_APB2 + 0x0400)
 
#define USART1_BASE   (PERIPH_BASE_APB2 + 0x1000)
 
#define USART6_BASE   (PERIPH_BASE_APB2 + 0x1400)
 
#define ADC1_BASE   (PERIPH_BASE_APB2 + 0x2000)
 
#define ADC2_BASE   (PERIPH_BASE_APB2 + 0x2100)
 
#define ADC3_BASE   (PERIPH_BASE_APB2 + 0x2200)
 
#define ADC_COMMON_BASE   (PERIPH_BASE_APB2 + 0x2300)
 
#define SDIO_BASE   (PERIPH_BASE_APB2 + 0x2C00)
 
#define SPI1_BASE   (PERIPH_BASE_APB2 + 0x3000)
 
#define SPI4_BASE   (PERIPH_BASE_APB2 + 0x3400)
 
#define SYSCFG_BASE   (PERIPH_BASE_APB2 + 0x3800)
 
#define EXTI_BASE   (PERIPH_BASE_APB2 + 0x3C00)
 
#define TIM9_BASE   (PERIPH_BASE_APB2 + 0x4000)
 
#define TIM10_BASE   (PERIPH_BASE_APB2 + 0x4400)
 
#define TIM11_BASE   (PERIPH_BASE_APB2 + 0x4800)
 
#define SPI5_BASE   (PERIPH_BASE_APB2 + 0x5000)
 
#define SPI6_BASE   (PERIPH_BASE_APB2 + 0x5400)
 
#define SAI1_BASE   (PERIPH_BASE_APB2 + 0x5800)
 
#define LTDC_BASE   (PERIPH_BASE_APB2 + 0x6800)
 
#define DSI_BASE   (PERIPH_BASE_APB2 + 0x6C00)
 
#define GPIO_PORT_A_BASE   (PERIPH_BASE_AHB1 + 0x0000)
 
#define GPIO_PORT_B_BASE   (PERIPH_BASE_AHB1 + 0x0400)
 
#define GPIO_PORT_C_BASE   (PERIPH_BASE_AHB1 + 0x0800)
 
#define GPIO_PORT_D_BASE   (PERIPH_BASE_AHB1 + 0x0C00)
 
#define GPIO_PORT_E_BASE   (PERIPH_BASE_AHB1 + 0x1000)
 
#define GPIO_PORT_F_BASE   (PERIPH_BASE_AHB1 + 0x1400)
 
#define GPIO_PORT_G_BASE   (PERIPH_BASE_AHB1 + 0x1800)
 
#define GPIO_PORT_H_BASE   (PERIPH_BASE_AHB1 + 0x1C00)
 
#define GPIO_PORT_I_BASE   (PERIPH_BASE_AHB1 + 0x2000)
 
#define GPIO_PORT_J_BASE   (PERIPH_BASE_AHB1 + 0x2400)
 
#define GPIO_PORT_K_BASE   (PERIPH_BASE_AHB1 + 0x2800)
 
#define CRC_BASE   (PERIPH_BASE_AHB1 + 0x3000)
 
#define RCC_BASE   (PERIPH_BASE_AHB1 + 0x3800)
 
#define FLASH_MEM_INTERFACE_BASE   (PERIPH_BASE_AHB1 + 0x3C00)
 
#define BKPSRAM_BASE   (PERIPH_BASE_AHB1 + 0x4000)
 
#define DMA1_BASE   (PERIPH_BASE_AHB1 + 0x6000)
 
#define DMA2_BASE   (PERIPH_BASE_AHB1 + 0x6400)
 
#define ETHERNET_BASE   (PERIPH_BASE_AHB1 + 0x8000)
 
#define DMA2D_BASE   (PERIPH_BASE_AHB1 + 0xB000U)
 
#define USB_OTG_HS_BASE   (PERIPH_BASE_AHB1 + 0x20000)
 
#define USB_OTG_FS_BASE   (PERIPH_BASE_AHB2 + 0x00000)
 
#define DCMI_BASE   (PERIPH_BASE_AHB2 + 0x50000)
 
#define CRYP_BASE   (PERIPH_BASE_AHB2 + 0x60000)
 
#define HASH_BASE   (PERIPH_BASE_AHB2 + 0x60400)
 
#define RNG_BASE   (PERIPH_BASE_AHB2 + 0x60800)
 
#define FMC_BANK1   (PERIPH_BASE_AHB3)
 
#define FMC_BANK2   (PERIPH_BASE_AHB3 + 0x10000000U)
 
#define FMC_BANK3   (PERIPH_BASE_AHB3 + 0x20000000U)
 
#define QUADSPI_BANK   (PERIPH_BASE_AHB3 + 0x30000000U)
 
#define FSMC_BASE   (PERIPH_BASE_AHB3 + 0x40000000U)
 
#define FMC_BASE   (PERIPH_BASE_AHB3 + 0x40000000U)
 
#define QUADSPI_BASE   (PERIPH_BASE_AHB3 + 0x40001000U)
 
#define FMC_BANK5   (PERIPH_BASE_AHB3 + 0x60000000U)
 
#define FMC_BANK6   (PERIPH_BASE_AHB3 + 0x70000000U)
 
#define DBGMCU_BASE   (PPBI_BASE + 0x00042000)
 
#define DESIG_FLASH_SIZE_BASE   (0x1FFF7A22U)
 
#define DESIG_UNIQUE_ID_BASE   (0x1FFF7A10U)
 
#define DESIG_UNIQUE_ID0   MMIO32(DESIG_UNIQUE_ID_BASE)
 
#define DESIG_UNIQUE_ID1   MMIO32(DESIG_UNIQUE_ID_BASE + 4)
 
#define DESIG_UNIQUE_ID2   MMIO32(DESIG_UNIQUE_ID_BASE + 8)
 
#define ST_VREFINT_CAL   MMIO16(0x1FFF7A2A)
 
#define ST_TSENSE_CAL1_30C   MMIO16(0x1FFF7A2C)
 
#define ST_TSENSE_CAL2_110C   MMIO16(0x1FFF7A2E)
 

Macro Definition Documentation

◆ ADC1_BASE

#define ADC1_BASE   (PERIPH_BASE_APB2 + 0x2000)

Definition at line 80 of file stm32/f4/memorymap.h.

◆ ADC2_BASE

#define ADC2_BASE   (PERIPH_BASE_APB2 + 0x2100)

Definition at line 81 of file stm32/f4/memorymap.h.

◆ ADC3_BASE

#define ADC3_BASE   (PERIPH_BASE_APB2 + 0x2200)

Definition at line 82 of file stm32/f4/memorymap.h.

◆ ADC_COMMON_BASE

#define ADC_COMMON_BASE   (PERIPH_BASE_APB2 + 0x2300)

Definition at line 83 of file stm32/f4/memorymap.h.

◆ BKPSRAM_BASE

#define BKPSRAM_BASE   (PERIPH_BASE_AHB1 + 0x4000)

Definition at line 120 of file stm32/f4/memorymap.h.

◆ BX_CAN1_BASE

#define BX_CAN1_BASE   (PERIPH_BASE_APB1 + 0x6400)

Definition at line 64 of file stm32/f4/memorymap.h.

◆ BX_CAN2_BASE

#define BX_CAN2_BASE   (PERIPH_BASE_APB1 + 0x6800)

Definition at line 65 of file stm32/f4/memorymap.h.

◆ CRC_BASE

#define CRC_BASE   (PERIPH_BASE_AHB1 + 0x3000)

Definition at line 116 of file stm32/f4/memorymap.h.

◆ CRYP_BASE

#define CRYP_BASE   (PERIPH_BASE_AHB2 + 0x60000)

Definition at line 136 of file stm32/f4/memorymap.h.

◆ DAC_BASE

#define DAC_BASE   (PERIPH_BASE_APB1 + 0x7400)

Definition at line 68 of file stm32/f4/memorymap.h.

◆ DBGMCU_BASE

#define DBGMCU_BASE   (PPBI_BASE + 0x00042000)

Definition at line 160 of file stm32/f4/memorymap.h.

◆ DCMI_BASE

#define DCMI_BASE   (PERIPH_BASE_AHB2 + 0x50000)

Definition at line 134 of file stm32/f4/memorymap.h.

◆ DESIG_FLASH_SIZE_BASE

#define DESIG_FLASH_SIZE_BASE   (0x1FFF7A22U)

Definition at line 163 of file stm32/f4/memorymap.h.

◆ DESIG_UNIQUE_ID0

#define DESIG_UNIQUE_ID0   MMIO32(DESIG_UNIQUE_ID_BASE)

Definition at line 165 of file stm32/f4/memorymap.h.

◆ DESIG_UNIQUE_ID1

#define DESIG_UNIQUE_ID1   MMIO32(DESIG_UNIQUE_ID_BASE + 4)

Definition at line 166 of file stm32/f4/memorymap.h.

◆ DESIG_UNIQUE_ID2

#define DESIG_UNIQUE_ID2   MMIO32(DESIG_UNIQUE_ID_BASE + 8)

Definition at line 167 of file stm32/f4/memorymap.h.

◆ DESIG_UNIQUE_ID_BASE

#define DESIG_UNIQUE_ID_BASE   (0x1FFF7A10U)

Definition at line 164 of file stm32/f4/memorymap.h.

◆ DMA1_BASE

#define DMA1_BASE   (PERIPH_BASE_AHB1 + 0x6000)

Definition at line 122 of file stm32/f4/memorymap.h.

◆ DMA2_BASE

#define DMA2_BASE   (PERIPH_BASE_AHB1 + 0x6400)

Definition at line 123 of file stm32/f4/memorymap.h.

◆ DMA2D_BASE

#define DMA2D_BASE   (PERIPH_BASE_AHB1 + 0xB000U)

Definition at line 126 of file stm32/f4/memorymap.h.

◆ DSI_BASE

#define DSI_BASE   (PERIPH_BASE_APB2 + 0x6C00)

Definition at line 100 of file stm32/f4/memorymap.h.

◆ ETHERNET_BASE

#define ETHERNET_BASE   (PERIPH_BASE_AHB1 + 0x8000)

Definition at line 125 of file stm32/f4/memorymap.h.

◆ EXTI_BASE

#define EXTI_BASE   (PERIPH_BASE_APB2 + 0x3C00)

Definition at line 91 of file stm32/f4/memorymap.h.

◆ FLASH_BASE

#define FLASH_BASE   (0x08000000U)

Definition at line 28 of file stm32/f4/memorymap.h.

◆ FLASH_MEM_INTERFACE_BASE

#define FLASH_MEM_INTERFACE_BASE   (PERIPH_BASE_AHB1 + 0x3C00)

Definition at line 119 of file stm32/f4/memorymap.h.

◆ FMC_BANK1

#define FMC_BANK1   (PERIPH_BASE_AHB3)

Definition at line 144 of file stm32/f4/memorymap.h.

◆ FMC_BANK2

#define FMC_BANK2   (PERIPH_BASE_AHB3 + 0x10000000U)

Definition at line 146 of file stm32/f4/memorymap.h.

◆ FMC_BANK3

#define FMC_BANK3   (PERIPH_BASE_AHB3 + 0x20000000U)

Definition at line 148 of file stm32/f4/memorymap.h.

◆ FMC_BANK5

#define FMC_BANK5   (PERIPH_BASE_AHB3 + 0x60000000U)

Definition at line 155 of file stm32/f4/memorymap.h.

◆ FMC_BANK6

#define FMC_BANK6   (PERIPH_BASE_AHB3 + 0x70000000U)

Definition at line 157 of file stm32/f4/memorymap.h.

◆ FMC_BASE

#define FMC_BASE   (PERIPH_BASE_AHB3 + 0x40000000U)

Definition at line 152 of file stm32/f4/memorymap.h.

◆ FMPI2C1_BASE

#define FMPI2C1_BASE   (PERIPH_BASE_APB1 + 0x6000)

Definition at line 63 of file stm32/f4/memorymap.h.

◆ FSMC_BASE

#define FSMC_BASE   (PERIPH_BASE_AHB3 + 0x40000000U)

Definition at line 151 of file stm32/f4/memorymap.h.

◆ GPIO_PORT_A_BASE

#define GPIO_PORT_A_BASE   (PERIPH_BASE_AHB1 + 0x0000)

Definition at line 104 of file stm32/f4/memorymap.h.

◆ GPIO_PORT_B_BASE

#define GPIO_PORT_B_BASE   (PERIPH_BASE_AHB1 + 0x0400)

Definition at line 105 of file stm32/f4/memorymap.h.

◆ GPIO_PORT_C_BASE

#define GPIO_PORT_C_BASE   (PERIPH_BASE_AHB1 + 0x0800)

Definition at line 106 of file stm32/f4/memorymap.h.

◆ GPIO_PORT_D_BASE

#define GPIO_PORT_D_BASE   (PERIPH_BASE_AHB1 + 0x0C00)

Definition at line 107 of file stm32/f4/memorymap.h.

◆ GPIO_PORT_E_BASE

#define GPIO_PORT_E_BASE   (PERIPH_BASE_AHB1 + 0x1000)

Definition at line 108 of file stm32/f4/memorymap.h.

◆ GPIO_PORT_F_BASE

#define GPIO_PORT_F_BASE   (PERIPH_BASE_AHB1 + 0x1400)

Definition at line 109 of file stm32/f4/memorymap.h.

◆ GPIO_PORT_G_BASE

#define GPIO_PORT_G_BASE   (PERIPH_BASE_AHB1 + 0x1800)

Definition at line 110 of file stm32/f4/memorymap.h.

◆ GPIO_PORT_H_BASE

#define GPIO_PORT_H_BASE   (PERIPH_BASE_AHB1 + 0x1C00)

Definition at line 111 of file stm32/f4/memorymap.h.

◆ GPIO_PORT_I_BASE

#define GPIO_PORT_I_BASE   (PERIPH_BASE_AHB1 + 0x2000)

Definition at line 112 of file stm32/f4/memorymap.h.

◆ GPIO_PORT_J_BASE

#define GPIO_PORT_J_BASE   (PERIPH_BASE_AHB1 + 0x2400)

Definition at line 113 of file stm32/f4/memorymap.h.

◆ GPIO_PORT_K_BASE

#define GPIO_PORT_K_BASE   (PERIPH_BASE_AHB1 + 0x2800)

Definition at line 114 of file stm32/f4/memorymap.h.

◆ HASH_BASE

#define HASH_BASE   (PERIPH_BASE_AHB2 + 0x60400)

Definition at line 137 of file stm32/f4/memorymap.h.

◆ I2C1_BASE

#define I2C1_BASE   (PERIPH_BASE_APB1 + 0x5400)

Definition at line 60 of file stm32/f4/memorymap.h.

◆ I2C2_BASE

#define I2C2_BASE   (PERIPH_BASE_APB1 + 0x5800)

Definition at line 61 of file stm32/f4/memorymap.h.

◆ I2C3_BASE

#define I2C3_BASE   (PERIPH_BASE_APB1 + 0x5C00)

Definition at line 62 of file stm32/f4/memorymap.h.

◆ I2S2_EXT_BASE

#define I2S2_EXT_BASE   (PERIPH_BASE_APB1 + 0x3400)

Definition at line 52 of file stm32/f4/memorymap.h.

◆ I2S3_EXT_BASE

#define I2S3_EXT_BASE   (PERIPH_BASE_APB1 + 0x4000)

Definition at line 55 of file stm32/f4/memorymap.h.

◆ IWDG_BASE

#define IWDG_BASE   (PERIPH_BASE_APB1 + 0x3000)

Definition at line 51 of file stm32/f4/memorymap.h.

◆ LPTIM1_BASE

#define LPTIM1_BASE   (PERIPH_BASE_APB1 + 0x2400)

Definition at line 48 of file stm32/f4/memorymap.h.

◆ LTDC_BASE

#define LTDC_BASE   (PERIPH_BASE_APB2 + 0x6800)

Definition at line 99 of file stm32/f4/memorymap.h.

◆ PERIPH_BASE

#define PERIPH_BASE   (0x40000000U)

Definition at line 29 of file stm32/f4/memorymap.h.

◆ PERIPH_BASE_AHB1

#define PERIPH_BASE_AHB1   (PERIPH_BASE + 0x20000)

Definition at line 32 of file stm32/f4/memorymap.h.

◆ PERIPH_BASE_AHB2

#define PERIPH_BASE_AHB2   0x50000000U

Definition at line 33 of file stm32/f4/memorymap.h.

◆ PERIPH_BASE_AHB3

#define PERIPH_BASE_AHB3   0x60000000U

Definition at line 34 of file stm32/f4/memorymap.h.

◆ PERIPH_BASE_APB1

#define PERIPH_BASE_APB1   (PERIPH_BASE + 0x00000)

Definition at line 30 of file stm32/f4/memorymap.h.

◆ PERIPH_BASE_APB2

#define PERIPH_BASE_APB2   (PERIPH_BASE + 0x10000)

Definition at line 31 of file stm32/f4/memorymap.h.

◆ POWER_CONTROL_BASE

#define POWER_CONTROL_BASE   (PERIPH_BASE_APB1 + 0x7000)

Definition at line 67 of file stm32/f4/memorymap.h.

◆ QUADSPI_BANK

#define QUADSPI_BANK   (PERIPH_BASE_AHB3 + 0x30000000U)

Definition at line 150 of file stm32/f4/memorymap.h.

◆ QUADSPI_BASE

#define QUADSPI_BASE   (PERIPH_BASE_AHB3 + 0x40001000U)

Definition at line 153 of file stm32/f4/memorymap.h.

◆ RCC_BASE

#define RCC_BASE   (PERIPH_BASE_AHB1 + 0x3800)

Definition at line 118 of file stm32/f4/memorymap.h.

◆ RNG_BASE

#define RNG_BASE   (PERIPH_BASE_AHB2 + 0x60800)

Definition at line 139 of file stm32/f4/memorymap.h.

◆ RTC_BASE

#define RTC_BASE   (PERIPH_BASE_APB1 + 0x2800)

Definition at line 49 of file stm32/f4/memorymap.h.

◆ SAI1_BASE

#define SAI1_BASE   (PERIPH_BASE_APB2 + 0x5800)

Definition at line 98 of file stm32/f4/memorymap.h.

◆ SDIO_BASE

#define SDIO_BASE   (PERIPH_BASE_APB2 + 0x2C00)

Definition at line 85 of file stm32/f4/memorymap.h.

◆ SPI1_BASE

#define SPI1_BASE   (PERIPH_BASE_APB2 + 0x3000)

Definition at line 87 of file stm32/f4/memorymap.h.

◆ SPI2_BASE

#define SPI2_BASE   (PERIPH_BASE_APB1 + 0x3800)

Definition at line 53 of file stm32/f4/memorymap.h.

◆ SPI3_BASE

#define SPI3_BASE   (PERIPH_BASE_APB1 + 0x3c00)

Definition at line 54 of file stm32/f4/memorymap.h.

◆ SPI4_BASE

#define SPI4_BASE   (PERIPH_BASE_APB2 + 0x3400)

Definition at line 88 of file stm32/f4/memorymap.h.

◆ SPI5_BASE

#define SPI5_BASE   (PERIPH_BASE_APB2 + 0x5000)

Definition at line 96 of file stm32/f4/memorymap.h.

◆ SPI6_BASE

#define SPI6_BASE   (PERIPH_BASE_APB2 + 0x5400)

Definition at line 97 of file stm32/f4/memorymap.h.

◆ ST_TSENSE_CAL1_30C

#define ST_TSENSE_CAL1_30C   MMIO16(0x1FFF7A2C)

Definition at line 171 of file stm32/f4/memorymap.h.

◆ ST_TSENSE_CAL2_110C

#define ST_TSENSE_CAL2_110C   MMIO16(0x1FFF7A2E)

Definition at line 172 of file stm32/f4/memorymap.h.

◆ ST_VREFINT_CAL

#define ST_VREFINT_CAL   MMIO16(0x1FFF7A2A)

Definition at line 170 of file stm32/f4/memorymap.h.

◆ SYSCFG_BASE

#define SYSCFG_BASE   (PERIPH_BASE_APB2 + 0x3800)

Definition at line 90 of file stm32/f4/memorymap.h.

◆ TIM10_BASE

#define TIM10_BASE   (PERIPH_BASE_APB2 + 0x4400)

Definition at line 93 of file stm32/f4/memorymap.h.

◆ TIM11_BASE

#define TIM11_BASE   (PERIPH_BASE_APB2 + 0x4800)

Definition at line 94 of file stm32/f4/memorymap.h.

◆ TIM12_BASE

#define TIM12_BASE   (PERIPH_BASE_APB1 + 0x1800)

Definition at line 45 of file stm32/f4/memorymap.h.

◆ TIM13_BASE

#define TIM13_BASE   (PERIPH_BASE_APB1 + 0x1c00)

Definition at line 46 of file stm32/f4/memorymap.h.

◆ TIM14_BASE

#define TIM14_BASE   (PERIPH_BASE_APB1 + 0x2000)

Definition at line 47 of file stm32/f4/memorymap.h.

◆ TIM1_BASE

#define TIM1_BASE   (PERIPH_BASE_APB2 + 0x0000)

Definition at line 74 of file stm32/f4/memorymap.h.

◆ TIM2_BASE

#define TIM2_BASE   (PERIPH_BASE_APB1 + 0x0000)

Definition at line 39 of file stm32/f4/memorymap.h.

◆ TIM3_BASE

#define TIM3_BASE   (PERIPH_BASE_APB1 + 0x0400)

Definition at line 40 of file stm32/f4/memorymap.h.

◆ TIM4_BASE

#define TIM4_BASE   (PERIPH_BASE_APB1 + 0x0800)

Definition at line 41 of file stm32/f4/memorymap.h.

◆ TIM5_BASE

#define TIM5_BASE   (PERIPH_BASE_APB1 + 0x0c00)

Definition at line 42 of file stm32/f4/memorymap.h.

◆ TIM6_BASE

#define TIM6_BASE   (PERIPH_BASE_APB1 + 0x1000)

Definition at line 43 of file stm32/f4/memorymap.h.

◆ TIM7_BASE

#define TIM7_BASE   (PERIPH_BASE_APB1 + 0x1400)

Definition at line 44 of file stm32/f4/memorymap.h.

◆ TIM8_BASE

#define TIM8_BASE   (PERIPH_BASE_APB2 + 0x0400)

Definition at line 75 of file stm32/f4/memorymap.h.

◆ TIM9_BASE

#define TIM9_BASE   (PERIPH_BASE_APB2 + 0x4000)

Definition at line 92 of file stm32/f4/memorymap.h.

◆ UART4_BASE

#define UART4_BASE   (PERIPH_BASE_APB1 + 0x4c00)

Definition at line 58 of file stm32/f4/memorymap.h.

◆ UART5_BASE

#define UART5_BASE   (PERIPH_BASE_APB1 + 0x5000)

Definition at line 59 of file stm32/f4/memorymap.h.

◆ UART7_BASE

#define UART7_BASE   (PERIPH_BASE_APB1 + 0x7800)

Definition at line 69 of file stm32/f4/memorymap.h.

◆ UART8_BASE

#define UART8_BASE   (PERIPH_BASE_APB1 + 0x7c00)

Definition at line 70 of file stm32/f4/memorymap.h.

◆ USART1_BASE

#define USART1_BASE   (PERIPH_BASE_APB2 + 0x1000)

Definition at line 77 of file stm32/f4/memorymap.h.

◆ USART2_BASE

#define USART2_BASE   (PERIPH_BASE_APB1 + 0x4400)

Definition at line 56 of file stm32/f4/memorymap.h.

◆ USART3_BASE

#define USART3_BASE   (PERIPH_BASE_APB1 + 0x4800)

Definition at line 57 of file stm32/f4/memorymap.h.

◆ USART6_BASE

#define USART6_BASE   (PERIPH_BASE_APB2 + 0x1400)

Definition at line 78 of file stm32/f4/memorymap.h.

◆ USB_OTG_FS_BASE

#define USB_OTG_FS_BASE   (PERIPH_BASE_AHB2 + 0x00000)

Definition at line 132 of file stm32/f4/memorymap.h.

◆ USB_OTG_HS_BASE

#define USB_OTG_HS_BASE   (PERIPH_BASE_AHB1 + 0x20000)

Definition at line 128 of file stm32/f4/memorymap.h.

◆ WWDG_BASE

#define WWDG_BASE   (PERIPH_BASE_APB1 + 0x2c00)

Definition at line 50 of file stm32/f4/memorymap.h.