libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
stm32/f4/memorymap.h
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_MEMORYMAP_H
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#define LIBOPENCM3_MEMORYMAP_H
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#include <
libopencm3/cm3/memorymap.h
>
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/* --- STM32F4 specific peripheral definitions ----------------------------- */
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/* Memory map for all busses */
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#define FLASH_BASE (0x08000000U)
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#define PERIPH_BASE (0x40000000U)
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#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
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#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
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#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000)
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#define PERIPH_BASE_AHB2 0x50000000U
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#define PERIPH_BASE_AHB3 0x60000000U
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/* Register boundary addresses */
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/* APB1 */
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#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000)
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#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400)
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#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800)
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#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)
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#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
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#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)
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#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800)
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#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00)
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#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000)
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#define LPTIM1_BASE (PERIPH_BASE_APB1 + 0x2400)
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#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
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#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
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#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
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#define I2S2_EXT_BASE (PERIPH_BASE_APB1 + 0x3400)
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#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
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#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)
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#define I2S3_EXT_BASE (PERIPH_BASE_APB1 + 0x4000)
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#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
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#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)
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#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)
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#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000)
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#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400)
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#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800)
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#define I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00)
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#define FMPI2C1_BASE (PERIPH_BASE_APB1 + 0x6000)
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#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)
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#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)
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/* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */
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#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
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#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
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#define UART7_BASE (PERIPH_BASE_APB1 + 0x7800)
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#define UART8_BASE (PERIPH_BASE_APB1 + 0x7c00)
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/* PERIPH_BASE_APB1 + 0x7800 (0x4000 8000 - 0x4000 FFFF): Reserved */
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/* APB2 */
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#define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000)
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#define TIM8_BASE (PERIPH_BASE_APB2 + 0x0400)
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/* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 0FFF): Reserved */
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#define USART1_BASE (PERIPH_BASE_APB2 + 0x1000)
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#define USART6_BASE (PERIPH_BASE_APB2 + 0x1400)
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/* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */
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#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000)
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#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2100)
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#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2200)
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#define ADC_COMMON_BASE (PERIPH_BASE_APB2 + 0x2300)
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/* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */
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#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2C00)
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/* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */
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#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
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#define SPI4_BASE (PERIPH_BASE_APB2 + 0x3400)
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/* PERIPH_BASE_APB2 + 0x3500 (0x4001 3500 - 0x4001 37FF): Reserved */
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#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800)
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#define EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00)
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#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4000)
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#define TIM10_BASE (PERIPH_BASE_APB2 + 0x4400)
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#define TIM11_BASE (PERIPH_BASE_APB2 + 0x4800)
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/* PERIPH_BASE_APB2 + 0x4C00 (0x4001 4C00 - 0x4001 4FFF): Reserved */
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#define SPI5_BASE (PERIPH_BASE_APB2 + 0x5000)
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#define SPI6_BASE (PERIPH_BASE_APB2 + 0x5400)
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#define SAI1_BASE (PERIPH_BASE_APB2 + 0x5800)
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#define LTDC_BASE (PERIPH_BASE_APB2 + 0x6800)
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#define DSI_BASE (PERIPH_BASE_APB2 + 0x6C00)
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/* PERIPH_BASE_APB2 + 0x7400 (0x4001 7400 - 0x4001 FFFF): Reserved */
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/* AHB1 */
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#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000)
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#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400)
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#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800)
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#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00)
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#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000)
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#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400)
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#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800)
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#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00)
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#define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000)
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#define GPIO_PORT_J_BASE (PERIPH_BASE_AHB1 + 0x2400)
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#define GPIO_PORT_K_BASE (PERIPH_BASE_AHB1 + 0x2800)
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/* PERIPH_BASE_AHB1 + 0x2C00 (0x4002 2C00 - 0x4002 2FFF): Reserved */
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#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)
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/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */
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#define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800)
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#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00)
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#define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000)
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/* PERIPH_BASE_AHB1 + 0x5000 (0x4002 5000 - 0x4002 5FFF): Reserved */
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#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000)
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#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400)
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/* PERIPH_BASE_AHB1 + 0x6800 (0x4002 6800 - 0x4002 7FFF): Reserved */
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#define ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000)
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#define DMA2D_BASE (PERIPH_BASE_AHB1 + 0xB000U)
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/* PERIPH_BASE_AHB1 + 0x9400 (0x4002 9400 - 0x4003 FFFF): Reserved */
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#define USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000)
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/* PERIPH_BASE_AHB1 + 0x60000 (0x4008 0000 - 0x4FFF FFFF): Reserved */
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/* AHB2 */
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#define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x00000)
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/* PERIPH_BASE_AHB2 + 0x40000 (0x5004 0000 - 0x5004 FFFF): Reserved */
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#define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000)
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/* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5005 FFFF): Reserved */
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#define CRYP_BASE (PERIPH_BASE_AHB2 + 0x60000)
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#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400)
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/* PERIPH_BASE_AHB2 + 0x60C00 (0x5006 0C00 - 0x5006 07FF): Reserved */
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#define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800)
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/* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */
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/* AHB3 */
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/* Address: 0x60000000 */
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#define FMC_BANK1 (PERIPH_BASE_AHB3)
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/* Address: 0x70000000 */
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#define FMC_BANK2 (PERIPH_BASE_AHB3 + 0x10000000U)
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/* Address: 0x80000000 */
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#define FMC_BANK3 (PERIPH_BASE_AHB3 + 0x20000000U)
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/* Address: 0x90000000 */
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#define QUADSPI_BANK (PERIPH_BASE_AHB3 + 0x30000000U)
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#define FSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000U)
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#define FMC_BASE (PERIPH_BASE_AHB3 + 0x40000000U)
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#define QUADSPI_BASE (PERIPH_BASE_AHB3 + 0x40001000U)
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/* Address: 0xC0000000 */
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#define FMC_BANK5 (PERIPH_BASE_AHB3 + 0x60000000U)
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/* Address: 0xD0000000 */
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#define FMC_BANK6 (PERIPH_BASE_AHB3 + 0x70000000U)
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/* PPIB */
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#define DBGMCU_BASE (PPBI_BASE + 0x00042000)
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/* Device Electronic Signature */
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#define DESIG_FLASH_SIZE_BASE (0x1FFF7A22U)
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#define DESIG_UNIQUE_ID_BASE (0x1FFF7A10U)
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#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE)
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#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4)
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#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8)
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/* ST provided factory calibration values @ 3.3V */
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#define ST_VREFINT_CAL MMIO16(0x1FFF7A2A)
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#define ST_TSENSE_CAL1_30C MMIO16(0x1FFF7A2C)
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#define ST_TSENSE_CAL2_110C MMIO16(0x1FFF7A2E)
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#endif
memorymap.h
include
libopencm3
stm32
f4
memorymap.h
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