libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
cm3/memorymap.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This library is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU Lesser General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public License
17 * along with this library. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef LIBOPENCM3_CM3_MEMORYMAP_H
21#define LIBOPENCM3_CM3_MEMORYMAP_H
22
23/* --- ARM Cortex-M0, M3 and M4 specific definitions ----------------------- */
24
25/* Private peripheral bus - Internal */
26#define PPBI_BASE (0xE0000000U)
27
28/* Those defined only on ARMv7 and above */
29#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
30/* ITM: Instrumentation Trace Macrocell */
31#define ITM_BASE (PPBI_BASE + 0x0000)
32
33/* DWT: Data Watchpoint and Trace unit */
34#define DWT_BASE (PPBI_BASE + 0x1000)
35
36/* FPB: Flash Patch and Breakpoint unit */
37#define FPB_BASE (PPBI_BASE + 0x2000)
38#endif
39
40/* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */
41
42#define SCS_BASE (PPBI_BASE + 0xE000)
43
44/* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */
45
46/* Those defined only on ARMv7 and above */
47#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
48#define TPIU_BASE (PPBI_BASE + 0x40000)
49#endif
50
51/* --- SCS: System Control Space --- */
52
53/* Those defined only on ARMv7 and above */
54#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
55/* ITR: Interrupt Type Register */
56#define ITR_BASE (SCS_BASE + 0x0000)
57#endif
58
59/* SYS_TICK: System Timer */
60#define SYS_TICK_BASE (SCS_BASE + 0x0010)
61
62/* NVIC: Nested Vector Interrupt Controller */
63#define NVIC_BASE (SCS_BASE + 0x0100)
64
65/* SCB: System Control Block */
66#define SCB_BASE (SCS_BASE + 0x0D00)
67
68/* MPU: Memory protection unit */
69#define MPU_BASE (SCS_BASE + 0x0D90)
70
71/* Those defined only on CM0*/
72#if defined(__ARM_ARCH_6M__)
73/* DEBUG: Debug control and configuration */
74#define DEBUG_BASE (SCS_BASE + 0x0DF0)
75#endif
76
77/* Those defined only on ARMv7 and above */
78#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
79/* STE: Software Trigger Interrupt Register */
80#define STIR_BASE (SCS_BASE + 0x0F00)
81/* ID: ID space */
82#define ID_BASE (SCS_BASE + 0x0FD0)
83#endif
84
85/**
86 * @defgroup coresight_registers Coresight Registers
87 * @{
88 * CoreSight Lock Status Registers and Lock Access Registers are
89 * documented for the DWT, ITM, FPB and TPIU peripherals
90 */
91#define CORESIGHT_LSR_OFFSET 0xfb4
92#define CORESIGHT_LAR_OFFSET 0xfb0
93
94/** CoreSight Lock Status Register lock status bit */
95#define CORESIGHT_LSR_SLK (1<<1)
96/** CoreSight Lock Status Register lock availability bit */
97#define CORESIGHT_LSR_SLI (1<<0)
98/** CoreSight Lock Access key, common for all */
99#define CORESIGHT_LAR_KEY 0xC5ACCE55
100
101/**@}*/
102
103#endif