PLL Configuration register values.
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PLL Configuration register values.
◆ RCC_PLLCFGR_PLLM_MASK
#define RCC_PLLCFGR_PLLM_MASK 0x3f |
◆ RCC_PLLCFGR_PLLM_SHIFT
#define RCC_PLLCFGR_PLLM_SHIFT 0 |
◆ RCC_PLLCFGR_PLLN_MASK
#define RCC_PLLCFGR_PLLN_MASK 0x1ff |
◆ RCC_PLLCFGR_PLLN_SHIFT
#define RCC_PLLCFGR_PLLN_SHIFT 6 |
◆ RCC_PLLCFGR_PLLP_MASK
#define RCC_PLLCFGR_PLLP_MASK 0x3 |
◆ RCC_PLLCFGR_PLLP_SHIFT
#define RCC_PLLCFGR_PLLP_SHIFT 16 |
◆ RCC_PLLCFGR_PLLQ_MASK
#define RCC_PLLCFGR_PLLQ_MASK 0xf |
◆ RCC_PLLCFGR_PLLQ_SHIFT
#define RCC_PLLCFGR_PLLQ_SHIFT 24 |
◆ RCC_PLLCFGR_PLLR_MASK
#define RCC_PLLCFGR_PLLR_MASK 0x7 |
◆ RCC_PLLCFGR_PLLR_SHIFT
#define RCC_PLLCFGR_PLLR_SHIFT 28 |
◆ RCC_PLLCFGR_PLLSRC
#define RCC_PLLCFGR_PLLSRC (1 << 22) |