Macros | |
| #define | QUADSPI_CR MMIO32(QUADSPI_BASE + 0x0U) |
| QUADSPI Control register. More... | |
| #define | QUADSPI_DCR MMIO32(QUADSPI_BASE + 0x4U) |
| QUADSPI Device Configuration. More... | |
| #define | QUADSPI_SR MMIO32(QUADSPI_BASE + 0x8U) |
| QUADSPI Status Register. More... | |
| #define | QUADSPI_FCR MMIO32(QUADSPI_BASE + 0xCU) |
| QUADSPI Flag Clear Register. More... | |
| #define | QUADSPI_DLR MMIO32(QUADSPI_BASE + 0x10U) |
| QUADSPI Data Length Register. More... | |
| #define | QUADSPI_CCR MMIO32(QUADSPI_BASE + 0x14U) |
| QUADSPI Communication Configuration Register. More... | |
| #define | QUADSPI_AR MMIO32(QUADSPI_BASE + 0x18U) |
| QUADSPI address register. More... | |
| #define | QUADSPI_ABR MMIO32(QUADSPI_BASE + 0x1CU) |
| QUADSPI alternate bytes register. More... | |
| #define | QUADSPI_DR MMIO32(QUADSPI_BASE + 0x20U) |
| QUADSPI data register. More... | |
| #define | QUADSPI_BYTE_DR MMIO8(QUADSPI_BASE + 0x20U) |
| BYTE addressable version for fetching bytes from the interface. More... | |
| #define | QUADSPI_PSMKR MMIO32(QUADSPI_BASE + 0x24U) |
| QUADSPI polling status. More... | |
| #define | QUADSPI_PSMAR MMIO32(QUADSPI_BASE + 0x28U) |
| QUADSPI polling status match. More... | |
| #define | QUADSPI_PIR MMIO32(QUADSPI_BASE + 0x2CU) |
| QUADSPI polling interval register. More... | |
| #define | QUADSPI_LPTR MMIO32(QUADSPI_BASE + 0x30U |
| QUADSPI low power timeout. More... | |
Detailed Description
Macro Definition Documentation
◆ QUADSPI_ABR
| #define QUADSPI_ABR MMIO32(QUADSPI_BASE + 0x1CU) |
QUADSPI alternate bytes register.
Definition at line 34 of file quadspi_common_v1.h.
◆ QUADSPI_AR
| #define QUADSPI_AR MMIO32(QUADSPI_BASE + 0x18U) |
QUADSPI address register.
Definition at line 31 of file quadspi_common_v1.h.
◆ QUADSPI_BYTE_DR
| #define QUADSPI_BYTE_DR MMIO8(QUADSPI_BASE + 0x20U) |
BYTE addressable version for fetching bytes from the interface.
Definition at line 39 of file quadspi_common_v1.h.
◆ QUADSPI_CCR
| #define QUADSPI_CCR MMIO32(QUADSPI_BASE + 0x14U) |
QUADSPI Communication Configuration Register.
Definition at line 28 of file quadspi_common_v1.h.
◆ QUADSPI_CR
| #define QUADSPI_CR MMIO32(QUADSPI_BASE + 0x0U) |
QUADSPI Control register.
Definition at line 13 of file quadspi_common_v1.h.
◆ QUADSPI_DCR
| #define QUADSPI_DCR MMIO32(QUADSPI_BASE + 0x4U) |
QUADSPI Device Configuration.
Definition at line 16 of file quadspi_common_v1.h.
◆ QUADSPI_DLR
| #define QUADSPI_DLR MMIO32(QUADSPI_BASE + 0x10U) |
QUADSPI Data Length Register.
Definition at line 25 of file quadspi_common_v1.h.
◆ QUADSPI_DR
| #define QUADSPI_DR MMIO32(QUADSPI_BASE + 0x20U) |
QUADSPI data register.
Definition at line 37 of file quadspi_common_v1.h.
◆ QUADSPI_FCR
| #define QUADSPI_FCR MMIO32(QUADSPI_BASE + 0xCU) |
QUADSPI Flag Clear Register.
Definition at line 22 of file quadspi_common_v1.h.
◆ QUADSPI_LPTR
| #define QUADSPI_LPTR MMIO32(QUADSPI_BASE + 0x30U |
QUADSPI low power timeout.
Definition at line 51 of file quadspi_common_v1.h.
◆ QUADSPI_PIR
| #define QUADSPI_PIR MMIO32(QUADSPI_BASE + 0x2CU) |
QUADSPI polling interval register.
Definition at line 48 of file quadspi_common_v1.h.
◆ QUADSPI_PSMAR
| #define QUADSPI_PSMAR MMIO32(QUADSPI_BASE + 0x28U) |
QUADSPI polling status match.
Definition at line 45 of file quadspi_common_v1.h.
◆ QUADSPI_PSMKR
| #define QUADSPI_PSMKR MMIO32(QUADSPI_BASE + 0x24U) |
QUADSPI polling status.
Definition at line 42 of file quadspi_common_v1.h.
◆ QUADSPI_SR
| #define QUADSPI_SR MMIO32(QUADSPI_BASE + 0x8U) |
QUADSPI Status Register.
Definition at line 19 of file quadspi_common_v1.h.
