libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
quadspi_common_v1.h
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1/** @addtogroup quadspi_defines
2 * @author Chuck McManis <cmcmanis@mcmanis.com> 2016
3 * @copyright SPDX: LGPL-3.0-or-later
4 * @{
5 */
6
7#pragma once
8
9/** @addtogroup quadspi_registers QuadSPI Registers
10 * @{
11 */
12/** QUADSPI Control register */
13#define QUADSPI_CR MMIO32(QUADSPI_BASE + 0x0U)
14
15/** QUADSPI Device Configuration */
16#define QUADSPI_DCR MMIO32(QUADSPI_BASE + 0x4U)
17
18/** QUADSPI Status Register */
19#define QUADSPI_SR MMIO32(QUADSPI_BASE + 0x8U)
20
21/** QUADSPI Flag Clear Register */
22#define QUADSPI_FCR MMIO32(QUADSPI_BASE + 0xCU)
23
24/** QUADSPI Data Length Register */
25#define QUADSPI_DLR MMIO32(QUADSPI_BASE + 0x10U)
26
27/** QUADSPI Communication Configuration Register */
28#define QUADSPI_CCR MMIO32(QUADSPI_BASE + 0x14U)
29
30/** QUADSPI address register */
31#define QUADSPI_AR MMIO32(QUADSPI_BASE + 0x18U)
32
33/** QUADSPI alternate bytes register */
34#define QUADSPI_ABR MMIO32(QUADSPI_BASE + 0x1CU)
35
36/** QUADSPI data register */
37#define QUADSPI_DR MMIO32(QUADSPI_BASE + 0x20U)
38/** BYTE addressable version for fetching bytes from the interface */
39#define QUADSPI_BYTE_DR MMIO8(QUADSPI_BASE + 0x20U)
40
41/** QUADSPI polling status */
42#define QUADSPI_PSMKR MMIO32(QUADSPI_BASE + 0x24U)
43
44/** QUADSPI polling status match */
45#define QUADSPI_PSMAR MMIO32(QUADSPI_BASE + 0x28U)
46
47/** QUADSPI polling interval register */
48#define QUADSPI_PIR MMIO32(QUADSPI_BASE + 0x2CU)
49
50/** QUADSPI low power timeout */
51#define QUADSPI_LPTR MMIO32(QUADSPI_BASE + 0x30U
52/**@}*/
53
54#define QUADSPI_CR_PRESCALE_MASK 0xff
55#define QUADSPI_CR_PRESCALE_SHIFT 24
56#define QUADSPI_CR_PMM (1 << 23)
57#define QUADSPI_CR_APMS (1 << 22)
58/* bit 21 is reserved */
59#define QUADSPI_CR_TOIE (1 << 20)
60#define QUADSPI_CR_SMIE (1 << 19)
61#define QUADSPI_CR_FTIE (1 << 18)
62#define QUADSPI_CR_TCIE (1 << 17)
63#define QUADSPI_CR_TEIE (1 << 16)
64
65/* bits 15:13 reserved */
66#define QUADSPI_CR_FTHRES_MASK 0x1f
67#define QUADSPI_CR_FTHRES_SHIFT 8
68#define QUADSPI_CR_FSEL (1 << 7)
69#define QUADSPI_CR_DFM (1 << 6)
70/* bit 5 reserved */
71#define QUADSPI_CR_SSHIFT (1 << 4)
72#define QUADSPI_CR_TCEN (1 << 3)
73/* bit 2 reserved on h7, DMAEN on f4 */
74#define QUADSPI_CR_ABORT (1 << 1)
75#define QUADSPI_CR_EN (1 << 0)
76
77/* bits 31:21 reserved */
78#define QUADSPI_DCR_FSIZE_MASK 0x1f
79#define QUADSPI_DCR_FSIZE_SHIFT 16
80/* bits 15:11 reserved */
81#define QUADSPI_DCR_CSHT_MASK 0x7
82#define QUADSPI_DCR_CSHT_SHIFT 8
83/* bits 7:1 reserved */
84#define QUADSPI_DCR_CKMODE (1 << 0)
85
86/* bits 31:14 reserved */
87#define QUADSPI_SR_FLEVEL_MASK 0x3f
88#define QUADSPI_SR_FLEVEL_SHIFT 8
89
90/* bits 7:6 reserved */
91#define QUADSPI_SR_BUSY (1 << 5)
92#define QUADSPI_SR_TOF (1 << 4)
93#define QUADSPI_SR_SMF (1 << 3)
94#define QUADSPI_SR_FTF (1 << 2)
95#define QUADSPI_SR_TCF (1 << 1)
96#define QUADSPI_SR_TEF (1 << 0)
97
98/* bits 31:5 reserved */
99#define QUADSPI_FCR_CTOF (1 << 4)
100#define QUADSPI_FCR_CSMF (1 << 3)
101/* bit 2 reserved */
102#define QUADSPI_FCR_CTCF (1 << 1)
103#define QUADSPI_FCR_CTEF (1 << 0)
104
105#define QUADSPI_CCR_DDRM (1 << 31)
106#define QUADSPI_CCR_DHHC (1 << 30)
107/* bit 29 reserved on F4, FRCM on H7 */
108#define QUADSPI_CCR_SIOO (1 << 28)
109#define QUADSPI_CCR_FMODE_MASK 0x3
110#define QUADSPI_CCR_FMODE_SHIFT 26
111#define QUADSPI_CCR_DMODE_MASK 0x3
112#define QUADSPI_CCR_DMODE_SHIFT 24
113/* bit 23 reserved */
114#define QUADSPI_CCR_DCYC_MASK 0x1f
115#define QUADSPI_CCR_DCYC_SHIFT 18
116
117#define QUADSPI_CCR_ABSIZE_MASK 0x3
118#define QUADSPI_CCR_ABSIZE_SHIFT 16
119
120#define QUADSPI_CCR_ABMODE_MASK 0x3
121#define QUADSPI_CCR_ABMODE_SHIFT 14
122
123#define QUADSPI_CCR_ADSIZE_MASK 0x3
124#define QUADSPI_CCR_ADSIZE_SHIFT 12
125
126#define QUADSPI_CCR_ADMODE_MASK 0x3
127#define QUADSPI_CCR_ADMODE_SHIFT 10
128
129#define QUADSPI_CCR_IMODE_MASK 0x3
130#define QUADSPI_CCR_IMODE_SHIFT 8
131
132#define QUADSPI_CCR_INST_MASK 0xff
133#define QUADSPI_CCR_INST_SHIFT 0
134
135/* MODE values */
136#define QUADSPI_CCR_MODE_NONE 0
137#define QUADSPI_CCR_MODE_1LINE 1
138#define QUADSPI_CCR_MODE_2LINE 2
139#define QUADSPI_CCR_MODE_4LINE 3
140
141/* FMODE values */
142#define QUADSPI_CCR_FMODE_IWRITE 0
143#define QUADSPI_CCR_FMODE_IREAD 1
144#define QUADSPI_CCR_FMODE_APOLL 2
145#define QUADSPI_CCR_FMODE_MEMMAP 3
146
147/**@}*/
148
149
150/**
151 * @defgroup quadspi_file QuadSPI peripheral API
152 * @brief APIs for the specialized SPI Flash peripheral
153 * @ingroup peripheral_apis
154 * @copyright SPDX: LGPL-3.0-or-later
155 *
156 * The QUADSPI is a specialized communication interface targeting single,
157 * dual or quad SPI Flash memories
158 * @{
159 */
160
162
163/**
164 * Enable the quadspi peripheral.
165 */
166void quadspi_enable(void);
167
168/**
169 * Disable the quadspi peripheral.
170 */
171void quadspi_disable(void);
172
174
175/**@}*/
#define END_DECLS
Definition: common.h:34
#define BEGIN_DECLS
Definition: common.h:33
void quadspi_enable(void)
Enable the quadspi peripheral.
void quadspi_disable(void)
Disable the quadspi peripheral.