Collaboration diagram for SCS Registers:

Macros
#define	SCS_DHCSR MMIO32(SCS_BASE + 0xDF0)
	Debug Halting Control and Status Register (DHCSR). More...

#define	SCS_DCRSR MMIO32(SCS_BASE + 0xDF4)
	Debug Core Register Selector Register (DCRSR). More...

#define	SCS_DCRDR MMIO32(SCS_BASE + 0xDF8)
	Debug Core Register Data Register (DCRDR) More...

#define	SCS_DEMCR MMIO32(SCS_BASE + 0xDFC)
	Debug Exception and Monitor Control Register (DEMCR). More...

Detailed Description

Macro Definition Documentation

◆ SCS_DCRDR

#define SCS_DCRDR MMIO32(SCS_BASE + 0xDF8)

Debug Core Register Data Register (DCRDR)

Purpose With the DCRSR, see Debug Core Register Selector Register, the DCRDR provides debug access to the ARM core registers, special-purpose registers, and Floating-point extension registers. The DCRDR is the data register for these accesses.

Used on its own, the DCRDR provides a message passing resource between an external debugger and a debug agent running on the processor. Note: The architecture does not define any handshaking mechanism for this use of DCRDR. Usage constraints: See Use of DCRSR and DCRDR for constraints that apply to particular transfers using the DCRSR and DCRDR. Configurations Always implemented.

Definition at line 93 of file scs.h.

◆ SCS_DCRSR

#define SCS_DCRSR MMIO32(SCS_BASE + 0xDF4)

Debug Core Register Selector Register (DCRSR).

Purpose With the DCRDR, the DCRSR provides debug access to the ARM core registers, special-purpose registers, and Floating-point extension registers. A write to DCRSR specifies the register to transfer, whether the transfer is a read or a write, and starts the transfer. Usage constraints: Only accessible in Debug state. Configurations Always implemented.

Definition at line 75 of file scs.h.

◆ SCS_DEMCR

#define SCS_DEMCR MMIO32(SCS_BASE + 0xDFC)

Debug Exception and Monitor Control Register (DEMCR).

Purpose Manages vector catch behavior and DebugMonitor handling when debugging. Usage constraints:

Bits [23:16] provide DebugMonitor exception control.
Bits [15:0] provide Debug state, halting debug, control. Configurations Always implemented.

Definition at line 105 of file scs.h.

◆ SCS_DHCSR

#define SCS_DHCSR MMIO32(SCS_BASE + 0xDF0)

Debug Halting Control and Status Register (DHCSR).

Purpose Controls halting debug. Usage constraints: The effect of modifying the C_STEP or C_MASKINTS bit when the system is running with halting debug enabled is UNPREDICTABLE. Halting debug is enabled when C_DEBUGEN is set to 1. The system is running when S_HALT is set to 0.

When C_DEBUGEN is set to 0, the processor ignores the values of all other bits in this register.
For more information about the use of DHCSR see Debug stepping on page C1-824. Configurations Always implemented.