libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
scs.h
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1/*
2 * This file is part of the libopencm3 project.
3 *
4 * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 * Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
6 *
7 * This library is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU Lesser General Public License as published by
9 * the Free Software Foundation, either version 3 of the License, or
10 * (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public License
18 * along with this library. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef LIBOPENCM3_CM3_SCS_H
22#define LIBOPENCM3_CM3_SCS_H
23
24/**
25 * @defgroup cm_scs Cortex-M System Control Space
26 * @ingroup CM3_defines
27 * The System Control Space (SCS) is a memory-mapped 4KB address space that
28 * provides 32-bit registers for configuration, status reporting and control.
29 * The SCS registers divide into the following groups:
30 * - system control and identification
31 * - the CPUID processor identification space
32 * - system configuration and status
33 * - fault reporting
34 * - a system timer, SysTick
35 * - a Nested Vectored Interrupt Controller (NVIC)
36 * - a Protected Memory System Architecture (PMSA)
37 * - system debug.
38 *
39 * Most portions of the SCS are covered by their own header files, eg
40 * systick.h, dwt.h, scb.h, itm.h, fpb.h
41 * @{
42 */
43
44/** @defgroup cm_scs_registers SCS Registers
45 * @ingroup cm_scs
46 * @{
47 */
48
49/**
50 * Debug Halting Control and Status Register (DHCSR).
51 *
52 * Purpose Controls halting debug.
53 * Usage constraints: The effect of modifying the C_STEP or C_MASKINTS bit when
54 * the system is running with halting debug enabled is UNPREDICTABLE.
55 * Halting debug is enabled when C_DEBUGEN is set to 1. The system is running
56 * when S_HALT is set to 0.
57 * - When C_DEBUGEN is set to 0, the processor ignores the values of all other
58 * bits in this register.
59 * - For more information about the use of DHCSR see Debug stepping on page
60 * C1-824.
61 * Configurations Always implemented.
62 */
63#define SCS_DHCSR MMIO32(SCS_BASE + 0xDF0)
64/**
65 * Debug Core Register Selector Register (DCRSR).
66 *
67 * Purpose With the DCRDR, the DCRSR provides debug access to the ARM core
68 * registers, special-purpose registers, and Floating-point extension
69 * registers. A write to DCRSR specifies the register to transfer, whether the
70 * transfer is a read or a write, and starts the transfer.
71 * Usage constraints: Only accessible in Debug state.
72 * Configurations Always implemented.
73 *
74 */
75#define SCS_DCRSR MMIO32(SCS_BASE + 0xDF4)
76/**
77 * Debug Core Register Data Register (DCRDR)
78 *
79 * Purpose With the DCRSR, see Debug Core Register Selector Register, the DCRDR
80 * provides debug access to the ARM core registers, special-purpose registers,
81 * and Floating-point extension registers. The DCRDR is the data register for
82 * these accesses.
83 * - Used on its own, the DCRDR provides a message passing resource between an
84 * external debugger and a debug agent running on the processor.
85 * Note:
86 * The architecture does not define any handshaking mechanism for this use of
87 * DCRDR.
88 * Usage constraints: See Use of DCRSR and DCRDR for constraints that apply to
89 * particular transfers using the DCRSR and DCRDR.
90 * Configurations Always implemented.
91 *
92 */
93#define SCS_DCRDR MMIO32(SCS_BASE + 0xDF8)
94/**
95 * Debug Exception and Monitor Control Register (DEMCR).
96 *
97 * Purpose Manages vector catch behavior and DebugMonitor handling when
98 * debugging.
99 * Usage constraints:
100 * - Bits [23:16] provide DebugMonitor exception control.
101 * - Bits [15:0] provide Debug state, halting debug, control.
102 * Configurations Always implemented.
103 *
104 */
105#define SCS_DEMCR MMIO32(SCS_BASE + 0xDFC)
106
107/**@}*/
108
109/* Debug Halting Control and Status Register (DHCSR) */
110#define SCS_DHCSR_DBGKEY 0xA05F0000
111#define SCS_DHCSR_C_DEBUGEN 0x00000001
112#define SCS_DHCSR_C_HALT 0x00000002
113#define SCS_DHCSR_C_STEP 0x00000004
114#define SCS_DHCSR_C_MASKINTS 0x00000008
115#define SCS_DHCSR_C_SNAPSTALL 0x00000020
116#define SCS_DHCSR_S_REGRDY 0x00010000
117#define SCS_DHCSR_S_HALT 0x00020000
118#define SCS_DHCSR_S_SLEEP 0x00040000
119#define SCS_DHCSR_S_LOCKUP 0x00080000
120#define SCS_DHCSR_S_RETIRE_ST 0x01000000
121#define SCS_DHCSR_S_RESET_ST 0x02000000
122
123/* Debug Core Register Selector Register (DCRSR) */
124#define SCS_DCRSR_REGSEL_MASK 0x0000001F
125#define SCS_DCRSR_REGSEL_XPSR 0x00000010
126#define SCS_DCRSR_REGSEL_MSP 0x00000011
127#define SCS_DCRSR_REGSEL_PSP 0x00000012
128
129/* Debug Exception and Monitor Control Register (DEMCR) */
130/* Bits 31:25 - Reserved */
131#define SCS_DEMCR_TRCENA (1 << 24)
132/* Bits 23:20 - Reserved */
133#define SCS_DEMCR_MON_REQ (1 << 19)
134#define SCS_DEMCR_MON_STEP (1 << 18)
135#define SCS_DEMCR_VC_MON_PEND (1 << 17)
136#define SCS_DEMCR_VC_MON_EN (1 << 16)
137/* Bits 15:11 - Reserved */
138#define SCS_DEMCR_VC_HARDERR (1 << 10)
139#define SCS_DEMCR_VC_INTERR (1 << 9)
140#define SCS_DEMCR_VC_BUSERR (1 << 8)
141#define SCS_DEMCR_VC_STATERR (1 << 7)
142#define SCS_DEMCR_VC_CHKERR (1 << 6)
143#define SCS_DEMCR_VC_NOCPERR (1 << 5)
144#define SCS_DEMCR_VC_MMERR (1 << 4)
145/* Bits 3:1 - Reserved */
146#define SCS_DEMCR_VC_CORERESET (1 << 0)
147
148/* CoreSight Lock Status Register for this peripheral */
149#define SCS_DWT_LSR MMIO32(SCS_DWT_BASE + 0xFB4)
150/* CoreSight Lock Access Register for this peripheral */
151#define SCS_DWT_LAR MMIO32(SCS_DWT_BASE + 0xFB0)
152
153
154/**@}*/
155#endif