PLL and other dedicated clock register values. More...

Collaboration diagram for RCC_PLLxxx/DCKy values:

Modules
	PLLSAICFGR PLLSAIP values

Macros
#define	RCC_PLLI2SCFGR_PLLI2SR_SHIFT 28

#define	RCC_PLLI2SCFGR_PLLI2SR_MASK 0x7

#define	RCC_PLLI2SCFGR_PLLI2SQ_SHIFT 24

#define	RCC_PLLI2SCFGR_PLLI2SQ_MASK 0xf

#define	RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6

#define	RCC_PLLI2SCFGR_PLLI2SN_MASK 0x1ff

#define	RCC_PLLSAICFGR_PLLSAIR_SHIFT 28

#define	RCC_PLLSAICFGR_PLLSAIR_MASK 0x7

#define	RCC_PLLSAICFGR_PLLSAIQ_SHIFT 24

#define	RCC_PLLSAICFGR_PLLSAIQ_MASK 0xF

#define	RCC_PLLSAICFGR_PLLSAIP_SHIFT 16

#define	RCC_PLLSAICFGR_PLLSAIP_MASK 0x3

#define	RCC_PLLSAICFGR_PLLSAIN_SHIFT 6

#define	RCC_PLLSAICFGR_PLLSAIN_MASK 0x1FF

#define	RCC_DCKCFGR_DSISEL (1 << 29)

#define	RCC_DCKCFGR_SDMMCSEL (1 << 28)

#define	RCC_DCKCFGR_48MSEL (1 << 27)

#define	RCC_DCKCFGR_TIMPRE (1 << 24)

#define	RCC_DCKCFGR_SAI1BSRC_SHIFT 22

#define	RCC_DCKCFGR_SAI1BSRC_MASK 0x3

#define	RCC_DCKCFGR_SAI1ASRC_SHIFT 20

#define	RCC_DCKCFGR_SAI1ASRC_MASK 0x3

#define	RCC_DCKCFGR_SAI1SRC_SAIQ 0x0

#define	RCC_DCKCFGR_SAI1SRC_I2SQ 0x1

#define	RCC_DCKCFGR_SAI1SRC_ALT 0x2

#define	RCC_DCKCFGR_SAI1SRC_ERROR 0x3

#define	RCC_DCKCFGR_PLLSAIDIVR_SHIFT 16

#define	RCC_DCKCFGR_PLLSAIDIVR_MASK 0x3

#define	RCC_DCKCFGR_PLLSAIDIVR_DIVR_2 0x0

#define	RCC_DCKCFGR_PLLSAIDIVR_DIVR_4 0x1

#define	RCC_DCKCFGR_PLLSAIDIVR_DIVR_8 0x2

#define	RCC_DCKCFGR_PLLSAIDIVR_DIVR_16 0x3

#define	RCC_DCKCFGR_PLLSAIDIVQ_SHIFT 8

#define	RCC_DCKCFGR_PLLSAIDIVQ_MASK 0x1f

#define	RCC_DCKCFGR_PLLI2SDIVQ_SHIFT 0

#define	RCC_DCKCFGR_PLLI2SDIVQ_MASK 0x1f

Detailed Description

PLL and other dedicated clock register values.

Macro Definition Documentation

◆ RCC_DCKCFGR_48MSEL

#define RCC_DCKCFGR_48MSEL (1 << 27)

Definition at line 747 of file f4/rcc.h.

◆ RCC_DCKCFGR_DSISEL

#define RCC_DCKCFGR_DSISEL (1 << 29)

Definition at line 745 of file f4/rcc.h.

◆ RCC_DCKCFGR_PLLI2SDIVQ_MASK

#define RCC_DCKCFGR_PLLI2SDIVQ_MASK 0x1f

Definition at line 773 of file f4/rcc.h.

◆ RCC_DCKCFGR_PLLI2SDIVQ_SHIFT

#define RCC_DCKCFGR_PLLI2SDIVQ_SHIFT 0

Definition at line 772 of file f4/rcc.h.

◆ RCC_DCKCFGR_PLLSAIDIVQ_MASK

#define RCC_DCKCFGR_PLLSAIDIVQ_MASK 0x1f

Definition at line 770 of file f4/rcc.h.

◆ RCC_DCKCFGR_PLLSAIDIVQ_SHIFT

#define RCC_DCKCFGR_PLLSAIDIVQ_SHIFT 8

Definition at line 769 of file f4/rcc.h.

◆ RCC_DCKCFGR_PLLSAIDIVR_DIVR_16

#define RCC_DCKCFGR_PLLSAIDIVR_DIVR_16 0x3

Definition at line 767 of file f4/rcc.h.

◆ RCC_DCKCFGR_PLLSAIDIVR_DIVR_2

#define RCC_DCKCFGR_PLLSAIDIVR_DIVR_2 0x0

Definition at line 764 of file f4/rcc.h.

◆ RCC_DCKCFGR_PLLSAIDIVR_DIVR_4

#define RCC_DCKCFGR_PLLSAIDIVR_DIVR_4 0x1

Definition at line 765 of file f4/rcc.h.

◆ RCC_DCKCFGR_PLLSAIDIVR_DIVR_8

#define RCC_DCKCFGR_PLLSAIDIVR_DIVR_8 0x2

Definition at line 766 of file f4/rcc.h.

◆ RCC_DCKCFGR_PLLSAIDIVR_MASK

#define RCC_DCKCFGR_PLLSAIDIVR_MASK 0x3

Definition at line 763 of file f4/rcc.h.

◆ RCC_DCKCFGR_PLLSAIDIVR_SHIFT

#define RCC_DCKCFGR_PLLSAIDIVR_SHIFT 16

Definition at line 762 of file f4/rcc.h.

◆ RCC_DCKCFGR_SAI1ASRC_MASK

#define RCC_DCKCFGR_SAI1ASRC_MASK 0x3

Definition at line 754 of file f4/rcc.h.

◆ RCC_DCKCFGR_SAI1ASRC_SHIFT

#define RCC_DCKCFGR_SAI1ASRC_SHIFT 20

Definition at line 753 of file f4/rcc.h.

◆ RCC_DCKCFGR_SAI1BSRC_MASK

#define RCC_DCKCFGR_SAI1BSRC_MASK 0x3

Definition at line 751 of file f4/rcc.h.

◆ RCC_DCKCFGR_SAI1BSRC_SHIFT

#define RCC_DCKCFGR_SAI1BSRC_SHIFT 22

Definition at line 750 of file f4/rcc.h.

◆ RCC_DCKCFGR_SAI1SRC_ALT

#define RCC_DCKCFGR_SAI1SRC_ALT 0x2

Definition at line 759 of file f4/rcc.h.

◆ RCC_DCKCFGR_SAI1SRC_ERROR

#define RCC_DCKCFGR_SAI1SRC_ERROR 0x3

Definition at line 760 of file f4/rcc.h.

◆ RCC_DCKCFGR_SAI1SRC_I2SQ

#define RCC_DCKCFGR_SAI1SRC_I2SQ 0x1

Definition at line 758 of file f4/rcc.h.

◆ RCC_DCKCFGR_SAI1SRC_SAIQ

#define RCC_DCKCFGR_SAI1SRC_SAIQ 0x0

Definition at line 757 of file f4/rcc.h.

◆ RCC_DCKCFGR_SDMMCSEL

#define RCC_DCKCFGR_SDMMCSEL (1 << 28)

Definition at line 746 of file f4/rcc.h.

◆ RCC_DCKCFGR_TIMPRE

#define RCC_DCKCFGR_TIMPRE (1 << 24)

Definition at line 748 of file f4/rcc.h.

◆ RCC_PLLI2SCFGR_PLLI2SN_MASK

#define RCC_PLLI2SCFGR_PLLI2SN_MASK 0x1ff

Definition at line 715 of file f4/rcc.h.

◆ RCC_PLLI2SCFGR_PLLI2SN_SHIFT

#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6

Definition at line 714 of file f4/rcc.h.

◆ RCC_PLLI2SCFGR_PLLI2SQ_MASK

#define RCC_PLLI2SCFGR_PLLI2SQ_MASK 0xf

Definition at line 712 of file f4/rcc.h.

◆ RCC_PLLI2SCFGR_PLLI2SQ_SHIFT

#define RCC_PLLI2SCFGR_PLLI2SQ_SHIFT 24

Definition at line 711 of file f4/rcc.h.

◆ RCC_PLLI2SCFGR_PLLI2SR_MASK

#define RCC_PLLI2SCFGR_PLLI2SR_MASK 0x7

Definition at line 709 of file f4/rcc.h.

◆ RCC_PLLI2SCFGR_PLLI2SR_SHIFT

#define RCC_PLLI2SCFGR_PLLI2SR_SHIFT 28

Definition at line 708 of file f4/rcc.h.

◆ RCC_PLLSAICFGR_PLLSAIN_MASK

#define RCC_PLLSAICFGR_PLLSAIN_MASK 0x1FF

Definition at line 741 of file f4/rcc.h.

◆ RCC_PLLSAICFGR_PLLSAIN_SHIFT

#define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6

Definition at line 740 of file f4/rcc.h.

◆ RCC_PLLSAICFGR_PLLSAIP_MASK

#define RCC_PLLSAICFGR_PLLSAIP_MASK 0x3

Definition at line 729 of file f4/rcc.h.

◆ RCC_PLLSAICFGR_PLLSAIP_SHIFT

#define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16

Definition at line 728 of file f4/rcc.h.

◆ RCC_PLLSAICFGR_PLLSAIQ_MASK

#define RCC_PLLSAICFGR_PLLSAIQ_MASK 0xF

Definition at line 725 of file f4/rcc.h.

◆ RCC_PLLSAICFGR_PLLSAIQ_SHIFT

#define RCC_PLLSAICFGR_PLLSAIQ_SHIFT 24

Definition at line 724 of file f4/rcc.h.

◆ RCC_PLLSAICFGR_PLLSAIR_MASK

#define RCC_PLLSAICFGR_PLLSAIR_MASK 0x7

Definition at line 721 of file f4/rcc.h.

◆ RCC_PLLSAICFGR_PLLSAIR_SHIFT

#define RCC_PLLSAICFGR_PLLSAIR_SHIFT 28

Definition at line 720 of file f4/rcc.h.

Modules

Macros