RCC_PLLCFGR PLLR values

Set these bits correctly not to exceed 170 MHz on this domain. More...

Collaboration diagram for RCC_PLLCFGR PLLR values:

Macros
#define	RCC_PLLCFGR_PLLR_DIV2   0
#define	RCC_PLLCFGR_PLLR_DIV4   1
#define	RCC_PLLCFGR_PLLR_DIV6   2
#define	RCC_PLLCFGR_PLLR_DIV8   3

Detailed Description

Set these bits correctly not to exceed 170 MHz on this domain.

Macro Definition Documentation

RCC_PLLCFGR_PLLR_DIV2

#define RCC_PLLCFGR_PLLR_DIV2   0

Definition at line 206 of file g4/rcc.h.

RCC_PLLCFGR_PLLR_DIV4

#define RCC_PLLCFGR_PLLR_DIV4   1

Definition at line 207 of file g4/rcc.h.

RCC_PLLCFGR_PLLR_DIV6

#define RCC_PLLCFGR_PLLR_DIV6   2

Definition at line 208 of file g4/rcc.h.

RCC_PLLCFGR_PLLR_DIV8

#define RCC_PLLCFGR_PLLR_DIV8   3

Definition at line 209 of file g4/rcc.h.