Defined Constants and Types for the STM32G4xx Reset and Clock Control More...

Collaboration diagram for RCC Defines:

Data Structures
struct	rcc_clock_scale

Modules
	RCC Registers

	RCC_CR values

	RCC_ICSCR values

	RCC_CFGR values

	RCC_PLLCFGR - PLL Configuration Register

	RCC_CIER - Clock interrupt enable register

	RCC_CIFR - Clock interrupt flag register

	RCC_CICR - Clock interrupt clear register

	RCC_AHBxRSTR reset values (full set)

	RCC_APB1RSTRx reset values (full set)

	RCC_APB2RSTR reset values

	RCC_AHBxENR enable values (full set)

	RCC_APB1ENRx enable values (full set)

	RCC_APB2ENR enable values

	RCC_AHB1SMENR - AHB1 periph clock in sleep mode

	RCC_AHB2SMENR - AHB2 periph clock in sleep mode

	RCC_AHB3SMENR - AHB3 periph clock in sleep mode

	RCC_APB1SMENR1 - APB1 periph clock in sleep mode

	RCC_APB1SMENR2 - APB1 periph clock in sleep mode

	RCC_APB2SMENR - APB2 periph clock in sleep mode

	RCC_CCIPR - Peripherals independent clock config register

	RCC_BDCR - Backup domain control register

	RCC_CSR - Control/Status register

	RCC_CRRCR Clock Recovery RC register

Macros
#define	_REG_BIT(base, bit) (((base) << 5) + (bit))

Enumerations
enum	rcc_clock_source { RCC_CPUCLK , RCC_SYSCLK , RCC_PERCLK , RCC_SYSTICKCLK , RCC_HCLK3 , RCC_AHBCLK , RCC_APB1CLK , RCC_APB2CLK }
	Enumerations for core system/bus clocks for user/driver/system access to base bus clocks not directly associated with a peripheral. More...

enum	rcc_clock_3v3 { RCC_CLOCK_3V3_24MHZ , RCC_CLOCK_3V3_48MHZ , RCC_CLOCK_3V3_96MHZ , RCC_CLOCK_3V3_170MHZ , RCC_CLOCK_3V3_END }

enum	rcc_osc { RCC_HSI48 , RCC_PLL , RCC_HSE , RCC_HSI16 , RCC_LSE , RCC_LSI }

enum	rcc_periph_clken { RCC_CRC = _REG_BIT(RCC_AHB1ENR_OFFSET, 12) , RCC_FLASH = _REG_BIT(RCC_AHB1ENR_OFFSET, 8) , RCC_FMAC = _REG_BIT(RCC_AHB1ENR_OFFSET, 4) , RCC_CORDIC = _REG_BIT(RCC_AHB1ENR_OFFSET, 3) , RCC_DMAMUX1 = _REG_BIT(RCC_AHB1ENR_OFFSET, 2) , RCC_DMA2 = _REG_BIT(RCC_AHB1ENR_OFFSET, 1) , RCC_DMA1 = _REG_BIT(RCC_AHB1ENR_OFFSET, 0) , RCC_RNG = _REG_BIT(RCC_AHB2ENR_OFFSET, 26) , RCC_AES = _REG_BIT(RCC_AHB2ENR_OFFSET, 24) , RCC_DAC4 = _REG_BIT(RCC_AHB2ENR_OFFSET, 19) , RCC_DAC3 = _REG_BIT(RCC_AHB2ENR_OFFSET, 18) , RCC_DAC2 = _REG_BIT(RCC_AHB2ENR_OFFSET, 17) , RCC_DAC1 = _REG_BIT(RCC_AHB2ENR_OFFSET, 16) , RCC_ADC345 = _REG_BIT(RCC_AHB2ENR_OFFSET, 14) , RCC_ADC12 = _REG_BIT(RCC_AHB2ENR_OFFSET, 13) , RCC_ADC1 = _REG_BIT(RCC_AHB2ENR_OFFSET, 13) , RCC_GPIOG = _REG_BIT(RCC_AHB2ENR_OFFSET, 6) , RCC_GPIOF = _REG_BIT(RCC_AHB2ENR_OFFSET, 5) , RCC_GPIOE = _REG_BIT(RCC_AHB2ENR_OFFSET, 4) , RCC_GPIOD = _REG_BIT(RCC_AHB2ENR_OFFSET, 3) , RCC_GPIOC = _REG_BIT(RCC_AHB2ENR_OFFSET, 2) , RCC_GPIOB = _REG_BIT(RCC_AHB2ENR_OFFSET, 1) , RCC_GPIOA = _REG_BIT(RCC_AHB2ENR_OFFSET, 0) , RCC_QSPI = _REG_BIT(RCC_AHB3ENR_OFFSET, 8) , RCC_FMC = _REG_BIT(RCC_AHB3ENR_OFFSET, 0) , RCC_LPTIM1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 31) , RCC_I2C3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 30) , RCC_PWR = _REG_BIT(RCC_APB1ENR1_OFFSET, 28) , RCC_FDCAN = _REG_BIT(RCC_APB1ENR1_OFFSET, 25) , RCC_USB = _REG_BIT(RCC_APB1ENR1_OFFSET, 23) , RCC_I2C2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 22) , RCC_I2C1 = _REG_BIT(RCC_APB1ENR1_OFFSET, 21) , RCC_UART5 = _REG_BIT(RCC_APB1ENR1_OFFSET, 20) , RCC_UART4 = _REG_BIT(RCC_APB1ENR1_OFFSET, 19) , RCC_USART3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 18) , RCC_USART2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 17) , RCC_SPI3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 15) , RCC_SPI2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 14) , RCC_WWDG = _REG_BIT(RCC_APB1ENR1_OFFSET, 11) , RCC_RTCAPB = _REG_BIT(RCC_APB1ENR1_OFFSET, 10) , RCC_CRS = _REG_BIT(RCC_APB1ENR1_OFFSET, 8) , RCC_TIM7 = _REG_BIT(RCC_APB1ENR1_OFFSET, 5) , RCC_TIM6 = _REG_BIT(RCC_APB1ENR1_OFFSET, 4) , RCC_TIM5 = _REG_BIT(RCC_APB1ENR1_OFFSET, 3) , RCC_TIM4 = _REG_BIT(RCC_APB1ENR1_OFFSET, 2) , RCC_TIM3 = _REG_BIT(RCC_APB1ENR1_OFFSET, 1) , RCC_TIM2 = _REG_BIT(RCC_APB1ENR1_OFFSET, 0) , RCC_UCPD1 = _REG_BIT(RCC_APB1ENR2_OFFSET, 8) , RCC_I2C4 = _REG_BIT(RCC_APB1ENR2_OFFSET, 1) , RCC_LPUART1 = _REG_BIT(RCC_APB1ENR2_OFFSET, 0) , RCC_HRTIM1 = _REG_BIT(RCC_APB2ENR_OFFSET, 26) , RCC_SAI1 = _REG_BIT(RCC_APB2ENR_OFFSET, 21) , RCC_TIM20 = _REG_BIT(RCC_APB2ENR_OFFSET, 20) , RCC_TIM17 = _REG_BIT(RCC_APB2ENR_OFFSET, 18) , RCC_TIM16 = _REG_BIT(RCC_APB2ENR_OFFSET, 17) , RCC_TIM15 = _REG_BIT(RCC_APB2ENR_OFFSET, 16) , RCC_SPI4 = _REG_BIT(RCC_APB2ENR_OFFSET, 15) , RCC_USART1 = _REG_BIT(RCC_APB2ENR_OFFSET, 14) , RCC_TIM8 = _REG_BIT(RCC_APB2ENR_OFFSET, 13) , RCC_SPI1 = _REG_BIT(RCC_APB2ENR_OFFSET, 12) , RCC_TIM1 = _REG_BIT(RCC_APB2ENR_OFFSET, 11) , RCC_SYSCFG = _REG_BIT(RCC_APB2ENR_OFFSET, 0) , SCC_CRC = _REG_BIT(RCC_AHB1SMENR_OFFSET, 12) , SCC_SRAM1 = _REG_BIT(RCC_AHB1SMENR_OFFSET, 9) , SCC_FLASH = _REG_BIT(RCC_AHB1SMENR_OFFSET, 8) , SCC_FMAC = _REG_BIT(RCC_AHB1SMENR_OFFSET, 4) , SCC_CORDIC = _REG_BIT(RCC_AHB1SMENR_OFFSET, 3) , SCC_DMAMUX1 = _REG_BIT(RCC_AHB1SMENR_OFFSET, 2) , SCC_DMA2 = _REG_BIT(RCC_AHB1SMENR_OFFSET, 1) , SCC_DMA1 = _REG_BIT(RCC_AHB1SMENR_OFFSET, 0) , SCC_RNG = _REG_BIT(RCC_AHB2SMENR_OFFSET, 26) , SCC_AES = _REG_BIT(RCC_AHB2SMENR_OFFSET, 24) , SCC_DAC4 = _REG_BIT(RCC_AHB2SMENR_OFFSET, 19) , SCC_DAC3 = _REG_BIT(RCC_AHB2SMENR_OFFSET, 18) , SCC_DAC2 = _REG_BIT(RCC_AHB2SMENR_OFFSET, 17) , SCC_DAC1 = _REG_BIT(RCC_AHB2SMENR_OFFSET, 16) , SCC_ADC345 = _REG_BIT(RCC_AHB2SMENR_OFFSET, 14) , SCC_ADC12 = _REG_BIT(RCC_AHB2SMENR_OFFSET, 13) , SCC_ADC1 = _REG_BIT(RCC_AHB2SMENR_OFFSET, 13) , SCC_CCMSRAM = _REG_BIT(RCC_AHB2SMENR_OFFSET, 10) , SCC_SRAM2 = _REG_BIT(RCC_AHB2SMENR_OFFSET, 9) , SCC_GPIOG = _REG_BIT(RCC_AHB2SMENR_OFFSET, 6) , SCC_GPIOF = _REG_BIT(RCC_AHB2SMENR_OFFSET, 5) , SCC_GPIOE = _REG_BIT(RCC_AHB2SMENR_OFFSET, 4) , SCC_GPIOD = _REG_BIT(RCC_AHB2SMENR_OFFSET, 3) , SCC_GPIOC = _REG_BIT(RCC_AHB2SMENR_OFFSET, 2) , SCC_GPIOB = _REG_BIT(RCC_AHB2SMENR_OFFSET, 1) , SCC_GPIOA = _REG_BIT(RCC_AHB2SMENR_OFFSET, 0) , SCC_QSPI = _REG_BIT(RCC_AHB3SMENR_OFFSET, 8) , SCC_FMC = _REG_BIT(RCC_AHB3SMENR_OFFSET, 0) , SCC_LPTIM1 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 31) , SCC_I2C3 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 30) , SCC_PWR = _REG_BIT(RCC_APB1SMENR1_OFFSET, 28) , SCC_FDCAN = _REG_BIT(RCC_APB1SMENR1_OFFSET, 25) , SCC_USB = _REG_BIT(RCC_APB1SMENR1_OFFSET, 23) , SCC_I2C2 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 22) , SCC_I2C1 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 21) , SCC_UART5 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 20) , SCC_UART4 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 19) , SCC_USART3 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 18) , SCC_USART2 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 17) , SCC_SPI3 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 15) , SCC_SPI2 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 14) , SCC_WWDG = _REG_BIT(RCC_APB1SMENR1_OFFSET, 11) , SCC_RTCAPB = _REG_BIT(RCC_APB1SMENR1_OFFSET, 10) , SCC_CRS = _REG_BIT(RCC_APB1SMENR1_OFFSET, 8) , SCC_TIM7 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 5) , SCC_TIM6 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 4) , SCC_TIM5 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 3) , SCC_TIM4 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 2) , SCC_TIM3 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 1) , SCC_TIM2 = _REG_BIT(RCC_APB1SMENR1_OFFSET, 0) , SCC_UCPD1 = _REG_BIT(RCC_APB1SMENR2_OFFSET, 8) , SCC_I2C4 = _REG_BIT(RCC_APB1SMENR2_OFFSET, 1) , SCC_LPUART1 = _REG_BIT(RCC_APB1SMENR2_OFFSET, 0) , SCC_HRTIM1 = _REG_BIT(RCC_APB2SMENR_OFFSET, 26) , SCC_SAI1 = _REG_BIT(RCC_APB2SMENR_OFFSET, 21) , SCC_TIM20 = _REG_BIT(RCC_APB2SMENR_OFFSET, 20) , SCC_TIM17 = _REG_BIT(RCC_APB2SMENR_OFFSET, 18) , SCC_TIM16 = _REG_BIT(RCC_APB2SMENR_OFFSET, 17) , SCC_TIM15 = _REG_BIT(RCC_APB2SMENR_OFFSET, 16) , SCC_SPI4 = _REG_BIT(RCC_APB2SMENR_OFFSET, 15) , SCC_USART1 = _REG_BIT(RCC_APB2SMENR_OFFSET, 14) , SCC_TIM8 = _REG_BIT(RCC_APB2SMENR_OFFSET, 13) , SCC_SPI1 = _REG_BIT(RCC_APB2SMENR_OFFSET, 12) , SCC_TIM1 = _REG_BIT(RCC_APB2SMENR_OFFSET, 11) , SCC_SYSCFG = _REG_BIT(RCC_APB2SMENR_OFFSET, 0) }

enum	rcc_periph_rst { RST_CRC = _REG_BIT(RCC_AHB1RSTR_OFFSET, 12) , RST_FLASH = _REG_BIT(RCC_AHB1RSTR_OFFSET, 8) , RST_FMAC = _REG_BIT(RCC_AHB1RSTR_OFFSET, 4) , RST_CORDIC = _REG_BIT(RCC_AHB1RSTR_OFFSET, 3) , RST_DMAMUX1 = _REG_BIT(RCC_AHB1RSTR_OFFSET, 2) , RST_DMA2 = _REG_BIT(RCC_AHB1RSTR_OFFSET, 1) , RST_DMA1 = _REG_BIT(RCC_AHB1RSTR_OFFSET, 0) , RST_RNG = _REG_BIT(RCC_AHB2RSTR_OFFSET, 26) , RST_AES = _REG_BIT(RCC_AHB2RSTR_OFFSET, 24) , RST_DAC4 = _REG_BIT(RCC_AHB2RSTR_OFFSET, 19) , RST_DAC3 = _REG_BIT(RCC_AHB2RSTR_OFFSET, 18) , RST_DAC2 = _REG_BIT(RCC_AHB2RSTR_OFFSET, 17) , RST_DAC1 = _REG_BIT(RCC_AHB2RSTR_OFFSET, 16) , RST_ADC345 = _REG_BIT(RCC_AHB2RSTR_OFFSET, 14) , RST_ADC12 = _REG_BIT(RCC_AHB2RSTR_OFFSET, 13) , RST_ADC1 = _REG_BIT(RCC_AHB2RSTR_OFFSET, 13) , RST_GPIOG = _REG_BIT(RCC_AHB2RSTR_OFFSET, 6) , RST_GPIOF = _REG_BIT(RCC_AHB2RSTR_OFFSET, 5) , RST_GPIOE = _REG_BIT(RCC_AHB2RSTR_OFFSET, 4) , RST_GPIOD = _REG_BIT(RCC_AHB2RSTR_OFFSET, 3) , RST_GPIOC = _REG_BIT(RCC_AHB2RSTR_OFFSET, 2) , RST_GPIOB = _REG_BIT(RCC_AHB2RSTR_OFFSET, 1) , RST_GPIOA = _REG_BIT(RCC_AHB2RSTR_OFFSET, 0) , RST_QSPI = _REG_BIT(RCC_AHB3RSTR_OFFSET, 8) , RST_FMC = _REG_BIT(RCC_AHB3RSTR_OFFSET, 0) , RST_LPTIM1 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 31) , RST_I2C3 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 30) , RST_PWR = _REG_BIT(RCC_APB1RSTR1_OFFSET, 28) , RST_FDCAN = _REG_BIT(RCC_APB1RSTR1_OFFSET, 25) , RST_USB = _REG_BIT(RCC_APB1RSTR1_OFFSET, 23) , RST_I2C2 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 22) , RST_I2C1 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 21) , RST_UART5 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 20) , RST_UART4 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 19) , RST_USART3 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 18) , RST_USART2 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 17) , RST_SPI3 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 15) , RST_SPI2 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 14) , RST_CRS = _REG_BIT(RCC_APB1RSTR1_OFFSET, 8) , RST_TIM7 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 5) , RST_TIM6 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 4) , RST_TIM5 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 3) , RST_TIM4 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 2) , RST_TIM3 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 1) , RST_TIM2 = _REG_BIT(RCC_APB1RSTR1_OFFSET, 0) , RST_UCPD1 = _REG_BIT(RCC_APB1RSTR2_OFFSET, 8) , RST_I2C4 = _REG_BIT(RCC_APB1RSTR2_OFFSET, 1) , RST_LPUART1 = _REG_BIT(RCC_APB1RSTR2_OFFSET, 0) , RST_HRTIM1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 26) , RST_SAI1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 21) , RST_TIM20 = _REG_BIT(RCC_APB2RSTR_OFFSET, 20) , RST_TIM17 = _REG_BIT(RCC_APB2RSTR_OFFSET, 18) , RST_TIM16 = _REG_BIT(RCC_APB2RSTR_OFFSET, 17) , RST_TIM15 = _REG_BIT(RCC_APB2RSTR_OFFSET, 16) , RST_SPI4 = _REG_BIT(RCC_APB2RSTR_OFFSET, 15) , RST_USART1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 14) , RST_TIM8 = _REG_BIT(RCC_APB2RSTR_OFFSET, 13) , RST_SPI1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 12) , RST_TIM1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 11) , RST_SYSCFG = _REG_BIT(RCC_APB2RSTR_OFFSET, 0) }

Functions
void	rcc_osc_ready_int_clear (enum rcc_osc osc)

void	rcc_osc_ready_int_enable (enum rcc_osc osc)

void	rcc_osc_ready_int_disable (enum rcc_osc osc)

int	rcc_osc_ready_int_flag (enum rcc_osc osc)

void	rcc_css_int_clear (void)

int	rcc_css_int_flag (void)

void	rcc_wait_for_sysclk_status (enum rcc_osc osc)

void	rcc_osc_on (enum rcc_osc osc)

void	rcc_osc_off (enum rcc_osc osc)

void	rcc_css_enable (void)

void	rcc_css_disable (void)

void	rcc_set_sysclk_source (uint32_t clk)

void	rcc_set_pll_source (uint32_t pllsrc)

void	rcc_set_ppre2 (uint32_t ppre2)

void	rcc_set_ppre1 (uint32_t ppre1)

void	rcc_set_hpre (uint32_t hpre)

void	rcc_set_main_pll (uint32_t pllsrc, uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq, uint32_t pllr)
	Reconfigures the main PLL for a HSE source. More...

uint32_t	rcc_system_clock_source (void)

void	rcc_clock_setup_pll (const struct rcc_clock_scale *clock)
	Setup clocks to run from PLL. More...

void	rcc_clock_setup_hse_3v3 (const struct rcc_clock_scale *clock)
	Setup clocks with the HSE. More...

void	rcc_set_clock48_source (uint32_t clksel)
	Set clock source for 48MHz clock. More...

uint32_t	rcc_get_usart_clk_freq (uint32_t usart)
	Get the peripheral clock speed for the specified (LP)UxART. More...

void	rcc_peripheral_enable_clock (volatile uint32_t *reg, uint32_t en)
	RCC Enable Peripheral Clocks. More...

void	rcc_peripheral_disable_clock (volatile uint32_t *reg, uint32_t en)
	RCC Disable Peripheral Clocks. More...

void	rcc_peripheral_reset (volatile uint32_t *reg, uint32_t reset)
	RCC Reset Peripherals. More...

void	rcc_peripheral_clear_reset (volatile uint32_t *reg, uint32_t clear_reset)
	RCC Remove Reset on Peripherals. More...

void	rcc_periph_clock_enable (enum rcc_periph_clken clken)
	Enable Peripheral Clock in running mode. More...

void	rcc_periph_clock_disable (enum rcc_periph_clken clken)
	Disable Peripheral Clock in running mode. More...

void	rcc_periph_reset_pulse (enum rcc_periph_rst rst)
	Reset Peripheral, pulsed. More...

void	rcc_periph_reset_hold (enum rcc_periph_rst rst)
	Reset Peripheral, hold. More...

void	rcc_periph_reset_release (enum rcc_periph_rst rst)
	Reset Peripheral, release. More...

void	rcc_set_mco (uint32_t mcosrc)
	Select the source of Microcontroller Clock Output. More...

void	rcc_osc_bypass_enable (enum rcc_osc osc)
	RCC Enable Bypass. More...

void	rcc_osc_bypass_disable (enum rcc_osc osc)
	RCC Disable Bypass. More...

bool	rcc_is_osc_ready (enum rcc_osc osc)
	Is the given oscillator ready? More...

void	rcc_wait_for_osc_ready (enum rcc_osc osc)
	Wait for Oscillator Ready. More...

uint16_t	rcc_get_div_from_hpre (uint8_t div_val)
	This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers. More...

Variables
uint32_t	rcc_ahb_frequency

uint32_t	rcc_apb1_frequency

uint32_t	rcc_apb2_frequency

const struct rcc_clock_scale	rcc_hsi_configs [RCC_CLOCK_3V3_END]

const struct rcc_clock_scale	rcc_hse_8mhz_3v3 [RCC_CLOCK_3V3_END]

const struct rcc_clock_scale	rcc_hse_12mhz_3v3 [RCC_CLOCK_3V3_END]

const struct rcc_clock_scale	rcc_hse_16mhz_3v3 [RCC_CLOCK_3V3_END]

#define	RCC_CCIPR2_SEL_MASK 0x3
	defgroup rcc_ccipr2_values RCC_CCIPR2 - Peripherals independent clock config register 2 More...

#define	RCC_CCIPR2_QSPI_SYS 0

#define	RCC_CCIPR2_QSPI_HSI16 1

#define	RCC_CCIPR2_QSPI_PLLQ 2

#define	RCC_CCIPR2_QSPI_SHIFT 20

#define	RCC_CCIPR2_I2C4_PCLK 0

#define	RCC_CCIPR2_I2C4_SYS 1

#define	RCC_CCIPR2_I2C4_HSI16 2

#define	RCC_CCIPR2_I2C4_SHIFT 0

Detailed Description

Defined Constants and Types for the STM32G4xx Reset and Clock Control

Version: 1.0.0

Author: © 2020 Karl Palsson karlp.nosp@m.@twe.nosp@m.ak.ne.nosp@m.t.au; © 2020 Sam Kirkham sam.k.nosp@m.irkh.nosp@m.am@co.nosp@m.deth.nosp@m.ink.c.nosp@m.o.uk; © 2020 Ben Brewer ben.b.nosp@m.rewe.nosp@m.r@cod.nosp@m.ethi.nosp@m.nk.co.nosp@m..uk

LGPL License Terms libopencm3 License

Author: © 2013 Frantisek Burian BuFra.nosp@m.n@se.nosp@m.znam..nosp@m.cz

Macro Definition Documentation

◆ _REG_BIT

#define _REG_BIT	(	base,
		bit
	)	(((base) << 5) + (bit))

Definition at line 779 of file g4/rcc.h.

◆ RCC_CCIPR2_I2C4_HSI16

#define RCC_CCIPR2_I2C4_HSI16 2

Definition at line 653 of file g4/rcc.h.

◆ RCC_CCIPR2_I2C4_PCLK

#define RCC_CCIPR2_I2C4_PCLK 0

Definition at line 651 of file g4/rcc.h.

◆ RCC_CCIPR2_I2C4_SHIFT

#define RCC_CCIPR2_I2C4_SHIFT 0

Definition at line 654 of file g4/rcc.h.

◆ RCC_CCIPR2_I2C4_SYS

#define RCC_CCIPR2_I2C4_SYS 1

Definition at line 652 of file g4/rcc.h.

◆ RCC_CCIPR2_QSPI_HSI16

#define RCC_CCIPR2_QSPI_HSI16 1

Definition at line 647 of file g4/rcc.h.

◆ RCC_CCIPR2_QSPI_PLLQ

#define RCC_CCIPR2_QSPI_PLLQ 2

Definition at line 648 of file g4/rcc.h.

◆ RCC_CCIPR2_QSPI_SHIFT

#define RCC_CCIPR2_QSPI_SHIFT 20

Definition at line 649 of file g4/rcc.h.

◆ RCC_CCIPR2_QSPI_SYS

#define RCC_CCIPR2_QSPI_SYS 0

Definition at line 646 of file g4/rcc.h.

◆ RCC_CCIPR2_SEL_MASK

#define RCC_CCIPR2_SEL_MASK 0x3

defgroup rcc_ccipr2_values RCC_CCIPR2 - Peripherals independent clock config register 2

Definition at line 644 of file g4/rcc.h.

Enumeration Type Documentation

◆ rcc_clock_3v3

enum rcc_clock_3v3

Enumerator
RCC_CLOCK_3V3_24MHZ
RCC_CLOCK_3V3_48MHZ
RCC_CLOCK_3V3_96MHZ
RCC_CLOCK_3V3_170MHZ
RCC_CLOCK_3V3_END

Definition at line 738 of file g4/rcc.h.

◆ rcc_clock_source

enum rcc_clock_source

Enumerations for core system/bus clocks for user/driver/system access to base bus clocks not directly associated with a peripheral.

Enumerator
RCC_CPUCLK
RCC_SYSCLK
RCC_PERCLK
RCC_SYSTICKCLK
RCC_HCLK3
RCC_AHBCLK
RCC_APB1CLK
RCC_APB2CLK

Definition at line 719 of file g4/rcc.h.

◆ rcc_osc

enum rcc_osc

Enumerator
RCC_HSI48
RCC_PLL
RCC_HSE
RCC_HSI16
RCC_LSE
RCC_LSI

Definition at line 770 of file g4/rcc.h.

◆ rcc_periph_clken

enum rcc_periph_clken

Enumerator
RCC_CRC
RCC_FLASH
RCC_FMAC
RCC_CORDIC
RCC_DMAMUX1
RCC_DMA2
RCC_DMA1
RCC_RNG
RCC_AES
RCC_DAC4
RCC_DAC3
RCC_DAC2
RCC_DAC1
RCC_ADC345
RCC_ADC12
RCC_ADC1
RCC_GPIOG
RCC_GPIOF
RCC_GPIOE
RCC_GPIOD
RCC_GPIOC
RCC_GPIOB
RCC_GPIOA
RCC_QSPI
RCC_FMC
RCC_LPTIM1
RCC_I2C3
RCC_PWR
RCC_FDCAN
RCC_USB
RCC_I2C2
RCC_I2C1
RCC_UART5
RCC_UART4
RCC_USART3
RCC_USART2
RCC_SPI3
RCC_SPI2
RCC_WWDG
RCC_RTCAPB
RCC_CRS
RCC_TIM7
RCC_TIM6
RCC_TIM5
RCC_TIM4
RCC_TIM3
RCC_TIM2
RCC_UCPD1
RCC_I2C4
RCC_LPUART1
RCC_HRTIM1
RCC_SAI1
RCC_TIM20
RCC_TIM17
RCC_TIM16
RCC_TIM15
RCC_SPI4
RCC_USART1
RCC_TIM8
RCC_SPI1
RCC_TIM1
RCC_SYSCFG
SCC_CRC
SCC_SRAM1
SCC_FLASH
SCC_FMAC
SCC_CORDIC
SCC_DMAMUX1
SCC_DMA2
SCC_DMA1
SCC_RNG
SCC_AES
SCC_DAC4
SCC_DAC3
SCC_DAC2
SCC_DAC1
SCC_ADC345
SCC_ADC12
SCC_ADC1
SCC_CCMSRAM
SCC_SRAM2
SCC_GPIOG
SCC_GPIOF
SCC_GPIOE
SCC_GPIOD
SCC_GPIOC
SCC_GPIOB
SCC_GPIOA
SCC_QSPI
SCC_FMC
SCC_LPTIM1
SCC_I2C3
SCC_PWR
SCC_FDCAN
SCC_USB
SCC_I2C2
SCC_I2C1
SCC_UART5
SCC_UART4
SCC_USART3
SCC_USART2
SCC_SPI3
SCC_SPI2
SCC_WWDG
SCC_RTCAPB
SCC_CRS
SCC_TIM7
SCC_TIM6
SCC_TIM5
SCC_TIM4
SCC_TIM3
SCC_TIM2
SCC_UCPD1
SCC_I2C4
SCC_LPUART1
SCC_HRTIM1
SCC_SAI1
SCC_TIM20
SCC_TIM17
SCC_TIM16
SCC_TIM15
SCC_SPI4
SCC_USART1
SCC_TIM8
SCC_SPI1
SCC_TIM1
SCC_SYSCFG

Definition at line 781 of file g4/rcc.h.

◆ rcc_periph_rst

enum rcc_periph_rst

Enumerator
RST_CRC
RST_FLASH
RST_FMAC
RST_CORDIC
RST_DMAMUX1
RST_DMA2
RST_DMA1
RST_RNG
RST_AES
RST_DAC4
RST_DAC3
RST_DAC2
RST_DAC1
RST_ADC345
RST_ADC12
RST_ADC1
RST_GPIOG
RST_GPIOF
RST_GPIOE
RST_GPIOD
RST_GPIOC
RST_GPIOB
RST_GPIOA
RST_QSPI
RST_FMC
RST_LPTIM1
RST_I2C3
RST_PWR
RST_FDCAN
RST_USB
RST_I2C2
RST_I2C1
RST_UART5
RST_UART4
RST_USART3
RST_USART2
RST_SPI3
RST_SPI2
RST_CRS
RST_TIM7
RST_TIM6
RST_TIM5
RST_TIM4
RST_TIM3
RST_TIM2
RST_UCPD1
RST_I2C4
RST_LPUART1
RST_HRTIM1
RST_SAI1
RST_TIM20
RST_TIM17
RST_TIM16
RST_TIM15
RST_SPI4
RST_USART1
RST_TIM8
RST_SPI1
RST_TIM1
RST_SYSCFG

Definition at line 933 of file g4/rcc.h.

Function Documentation

◆ rcc_clock_setup_hse_3v3()

void rcc_clock_setup_hse_3v3 ( const struct rcc_clock_scale * clock )

Setup clocks with the HSE.

Deprecated:: replaced by rcc_clock_setup_pll as a drop in replacement.

See also: rcc_clock_setup_pll which supports HSI16 as well as HSE, using the same clock structures.

Definition at line 747 of file rcc.c.

References rcc_clock_setup_pll().

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◆ rcc_clock_setup_pll()

void rcc_clock_setup_pll ( const struct rcc_clock_scale * clock )

Setup clocks to run from PLL.

The arguments provide the pll source, multipliers, dividers, all that's needed to establish a system clock.

Parameters

clock clock information structure.

Definition at line 665 of file rcc.c.

Referenced by rcc_clock_setup_hse_3v3().

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◆ rcc_css_disable()

void rcc_css_disable ( void )

Definition at line 561 of file rcc.c.

References RCC_CR.

◆ rcc_css_enable()

void rcc_css_enable ( void )

Definition at line 556 of file rcc.c.

References RCC_CR, and RCC_CR_CSSON.

◆ rcc_css_int_clear()

void rcc_css_int_clear ( void )

Definition at line 453 of file rcc.c.

References RCC_CICR, and RCC_CICR_CSSC.

◆ rcc_css_int_flag()

int rcc_css_int_flag ( void )

Definition at line 458 of file rcc.c.

References RCC_CIFR, and RCC_CIFR_CSSF.

◆ rcc_get_div_from_hpre()

uint16_t rcc_get_div_from_hpre ( uint8_t div_val )

This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers.

Parameters

div_val Masked and shifted divider value from register (e.g. RCC_CFGR)

Definition at line 260 of file rcc_common_all.c.

Referenced by rcc_get_clksel_freq().

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◆ rcc_get_usart_clk_freq()

uint32_t rcc_get_usart_clk_freq ( uint32_t usart )

Get the peripheral clock speed for the specified (LP)UxART.

Parameters

usart Base address of USART to get clock frequency for.

Definition at line 783 of file rcc.c.

References cm3_assert_not_reached, LPUART1_BASE, RCC_CCIPR_LPUART1SEL_SHIFT, RCC_CCIPR_UART4SEL_SHIFT, RCC_CCIPR_UART5SEL_SHIFT, RCC_CCIPR_USART1SEL_SHIFT, RCC_CCIPR_USART2SEL_SHIFT, RCC_CCIPR_USART3SEL_SHIFT, rcc_get_clksel_freq(), UART4_BASE, UART5_BASE, USART1_BASE, USART2_BASE, and USART3_BASE.

Referenced by usart_set_baudrate().

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◆ rcc_is_osc_ready()

bool rcc_is_osc_ready ( enum rcc_osc osc )

Is the given oscillator ready?

Parameters

osc	Oscillator ID

Returns: true if the hardware indicates the oscillator is ready.

Definition at line 463 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSERDY, RCC_CR, RCC_CR_HSERDY, RCC_CR_HSIRDY, RCC_CR_PLLRDY, RCC_CRRCR, RCC_CRRCR_HSI48RDY, RCC_CSR, RCC_CSR_LSIRDY, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

Referenced by rcc_wait_for_osc_ready().

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◆ rcc_osc_bypass_disable()

void rcc_osc_bypass_disable ( enum rcc_osc osc )

RCC Disable Bypass.

Re-enable the internal clock (high speed and low speed clocks only). The internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note: The LSE clock is in the backup domain and cannot have bypass removed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect) or the backup domain has been reset (see rcc_backupdomain_reset).

Parameters

[in] osc Oscillator ID. Only HSE and LSE have effect.

Definition at line 238 of file rcc_common_all.c.

References RCC_BDCR, RCC_CR, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_bypass_enable()

void rcc_osc_bypass_enable ( enum rcc_osc osc )

RCC Enable Bypass.

Enable an external clock to bypass the internal clock (high speed and low speed clocks only). The external clock must be enabled (see rcc_osc_on) and the internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note: The LSE clock is in the backup domain and cannot be bypassed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect).

Parameters

[in] osc Oscillator ID. Only HSE and LSE have effect.

Definition at line 208 of file rcc_common_all.c.

References RCC_BDCR, RCC_BDCR_LSEBYP, RCC_CR, RCC_CR_HSEBYP, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_off()

void rcc_osc_off ( enum rcc_osc osc )

Definition at line 532 of file rcc.c.

References RCC_BDCR, RCC_CR, RCC_CRRCR, RCC_CSR, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll().

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◆ rcc_osc_on()

void rcc_osc_on ( enum rcc_osc osc )

Definition at line 508 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSEON, RCC_CR, RCC_CR_HSEON, RCC_CR_HSION, RCC_CR_PLLON, RCC_CRRCR, RCC_CRRCR_HSI48ON, RCC_CSR, RCC_CSR_LSION, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll().

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◆ rcc_osc_ready_int_clear()

void rcc_osc_ready_int_clear ( enum rcc_osc osc )

Definition at line 362 of file rcc.c.

References RCC_CICR, RCC_CICR_HSERDYC, RCC_CICR_HSI48RDYC, RCC_CICR_HSIRDYC, RCC_CICR_LSERDYC, RCC_CICR_LSIRDYC, RCC_CICR_PLLRDYC, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

◆ rcc_osc_ready_int_disable()

void rcc_osc_ready_int_disable ( enum rcc_osc osc )

Definition at line 410 of file rcc.c.

References RCC_CIER, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

◆ rcc_osc_ready_int_enable()

void rcc_osc_ready_int_enable ( enum rcc_osc osc )

Definition at line 386 of file rcc.c.

References RCC_CIER, RCC_CIER_HSERDYIE, RCC_CIER_HSI48RDYIE, RCC_CIER_HSIRDYIE, RCC_CIER_LSERDYIE, RCC_CIER_LSIRDYIE, RCC_CIER_PLLRDYIE, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

◆ rcc_osc_ready_int_flag()

int rcc_osc_ready_int_flag ( enum rcc_osc osc )

Definition at line 434 of file rcc.c.

References RCC_CIFR, RCC_CIFR_HSERDYF, RCC_CIFR_HSI48RDYF, RCC_CIFR_HSIRDYF, RCC_CIFR_LSERDYF, RCC_CIFR_LSIRDYF, RCC_CIFR_PLLRDYF, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

◆ rcc_periph_clock_disable()

void rcc_periph_clock_disable ( enum rcc_periph_clken clken )

Disable Peripheral Clock in running mode.

Disable the clock on particular peripheral.

Parameters

[in] clken rcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 139 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_periph_clock_enable()

void rcc_periph_clock_enable ( enum rcc_periph_clken clken )

Enable Peripheral Clock in running mode.

Enable the clock on particular peripheral.

Parameters

[in] clken rcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 127 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

Referenced by crs_autotrim_usb_enable(), rcc_clock_setup_pll(), and st_usbfs_v2_usbd_init().

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◆ rcc_periph_reset_hold()

void rcc_periph_reset_hold ( enum rcc_periph_rst rst )

Reset Peripheral, hold.

Reset particular peripheral, and hold in reset state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 166 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_pulse()

void rcc_periph_reset_pulse ( enum rcc_periph_rst rst )

Reset Peripheral, pulsed.

Reset particular peripheral, and restore to working state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 152 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_release()

void rcc_periph_reset_release ( enum rcc_periph_rst rst )

Reset Peripheral, release.

Restore peripheral from reset state to working state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 179 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_peripheral_clear_reset()

void rcc_peripheral_clear_reset	(	volatile uint32_t *	reg,
		uint32_t	clear_reset
	)

RCC Remove Reset on Peripherals.

Remove the reset on particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could have the reset removed simultaneously only if they are controlled by the same register.

See also: rcc_periph_reset_release for a less error prone version, if you only need to unreset a single peripheral.; rcc_periph_reset_pulse if you are only going to toggle reset anyway.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	clear_reset	Unsigned int32. Logical OR of all resets to be removed: If register is RCC_AHBRSTR, from RCC_AHBxRSTR reset values (full set) If register is RCC_APB1RSTR, from RCC_APB1RSTRx reset values (full set) If register is RCC_APB2RSTR, from RCC_APB2RSTR reset values

Definition at line 111 of file rcc_common_all.c.

◆ rcc_peripheral_disable_clock()

void rcc_peripheral_disable_clock	(	volatile uint32_t *	reg,
		uint32_t	en
	)

RCC Disable Peripheral Clocks.

Disable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be disabled simultaneously only if they are controlled by the same register.

See also: rcc_periph_clock_disable for a less error prone version, if you only need to disable a single peripheral.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	en	Unsigned int32. Logical OR of all enables to be used for disabling. If register is RCC_AHBENR, from RCC_AHBxENR enable values (full set) If register is RCC_APB1ENR, from RCC_APB1ENRx enable values (full set) If register is RCC_APB2ENR, from RCC_APB2ENR enable values

Definition at line 66 of file rcc_common_all.c.

◆ rcc_peripheral_enable_clock()

void rcc_peripheral_enable_clock	(	volatile uint32_t *	reg,
		uint32_t	en
	)

RCC Enable Peripheral Clocks.

Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be enabled simultaneously only if they are controlled by the same register.

See also: rcc_periph_clock_enable for a less error prone version, if you only need to enable a single peripheral.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	en	Unsigned int32. Logical OR of all enables to be set If register is RCC_AHBENR, from RCC_AHBxENR enable values (full set) If register is RCC_APB1ENR, from RCC_APB1ENRx enable values (full set) If register is RCC_APB2ENR, from RCC_APB2ENR enable values

Definition at line 44 of file rcc_common_all.c.

◆ rcc_peripheral_reset()

void rcc_peripheral_reset	(	volatile uint32_t *	reg,
		uint32_t	reset
	)

RCC Reset Peripherals.

Reset particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could be reset simultaneously only if they are controlled by the same register.

See also: rcc_periph_reset_hold for a less error prone version, if you only need to reset a single peripheral.; rcc_periph_reset_pulse if you are only going to toggle reset anyway.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	reset	Unsigned int32. Logical OR of all resets. If register is RCC_AHBRSTR, from RCC_AHBxRSTR reset values (full set) If register is RCC_APB1RSTR, from RCC_APB1RSTRx reset values (full set) If register is RCC_APB2RSTR, from RCC_APB2RSTR reset values

Definition at line 88 of file rcc_common_all.c.

◆ rcc_set_clock48_source()

void rcc_set_clock48_source ( uint32_t clksel )

Set clock source for 48MHz clock.

The 48 MHz clock is derived from one of the four following sources:

PLLQ VCO (RCC_CCIPR_CLK48_PLLQ)
HSI48 internal oscillator (RCC_CCIPR_CLK48_HSI48)

Parameters

clksel One of the definitions above

Definition at line 760 of file rcc.c.

References RCC_CCIPR, RCC_CCIPR_CLK48SEL_SHIFT, and RCC_CCIPR_SEL_MASK.

◆ rcc_set_hpre()

void rcc_set_hpre ( uint32_t hpre )

Definition at line 602 of file rcc.c.

References rcc_clock_scale::hpre, RCC_CFGR, RCC_CFGR_HPRE_MASK, and RCC_CFGR_HPRE_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_main_pll()

void rcc_set_main_pll	(	uint32_t	pllsrc,
		uint32_t	pllm,
		uint32_t	plln,
		uint32_t	pllp,
		uint32_t	pllq,
		uint32_t	pllr
	)

Reconfigures the main PLL for a HSE source.

Any reserved bits are kept at their reset values.

Parameters

pllsrc	Source for the main PLL input clock
pllm	Divider for the main PLL input clock
plln	Main PLL multiplication factor for VCO
pllp	Main PLL divider for ADC
pllq	Main PLL divider for QUADSPI, FDCAN, USB, SAI & I2S
pllr	Main PLL divider for main system clock