RCC_PLLCFGR - PLL Configuration Register
Collaboration diagram for RCC_PLLCFGR - PLL Configuration Register:
Modules | |
| RCC_PLLCFGR PLLR values | |
| Set these bits correctly not to exceed 170 MHz on this domain. | |
| RCC_PLLCFGR PLLN values | |
| Allowed values 8 <= n <= 127, VCO output limits specified in datasheet. | |
| RCC_PLLCFGR PLLM values | |
| Allowed values 1 <= m <= 16, VCO input limits specified in datasheet. | |
Macros | |
| #define | RCC_PLLCFGR_PLLPDIV_MASK 0x1f |
| #define | RCC_PLLCFGR_PLLPDIV_SHIFT 27 |
| #define | RCC_PLLCFGR_PLLR_SHIFT 25 |
| #define | RCC_PLLCFGR_PLLR_MASK 0x3 |
| #define | RCC_PLLCFGR_PLLREN BIT24 |
| #define | RCC_PLLCFGR_PLLQ_DIV2 0 |
| #define | RCC_PLLCFGR_PLLQ_DIV4 1 |
| #define | RCC_PLLCFGR_PLLQ_DIV6 2 |
| #define | RCC_PLLCFGR_PLLQ_DIV8 3 |
| #define | RCC_PLLCFGR_PLLQ_SHIFT 21 |
| #define | RCC_PLLCFGR_PLLQ_MASK 0x3 |
| #define | RCC_PLLCFGR_PLLQEN BIT20 |
| #define | RCC_PLLCFGR_PLLP BIT17 |
| #define | RCC_PLLCFGR_PLLP_DIV7 0 |
| #define | RCC_PLLCFGR_PLLP_DIV17 RCC_PLLCFGR_PLLP |
| #define | RCC_PLLCFGR_PLLPEN (1 << 16) |
| #define | RCC_PLLCFGR_PLLSRC_NONE 0 |
| #define | RCC_PLLCFGR_PLLSRC_HSI16 2 |
| #define | RCC_PLLCFGR_PLLSRC_HSE 3 |
| #define | RCC_PLLCFGR_PLLSRC_SHIFT 0 |
| #define | RCC_PLLCFGR_PLLSRC_MASK 0x3 |
Detailed Description
Macro Definition Documentation
◆ RCC_PLLCFGR_PLLP
◆ RCC_PLLCFGR_PLLP_DIV17
| #define RCC_PLLCFGR_PLLP_DIV17 RCC_PLLCFGR_PLLP |
