RCC_CICR - Clock interrupt clear register
Collaboration diagram for RCC_CICR - Clock interrupt clear register:
Macros | |
| #define | RCC_CICR_HSI48RDYC (1 << 10) |
| #define | RCC_CICR_LSECSSC (1 << 9) |
| #define | RCC_CICR_CSSC (1 << 8) |
| #define | RCC_CICR_PLLRDYC (1 << 5) |
| #define | RCC_CICR_HSERDYC (1 << 4) |
| #define | RCC_CICR_HSIRDYC (1 << 3) |
| #define | RCC_CICR_LSERDYC (1 << 1) |
| #define | RCC_CICR_LSIRDYC (1 << 0) |
