libopencm3 STM32G4xx Reset and Clock Control More...

Collaboration diagram for RCC peripheral API:

Macros
#define	_RCC_REG(i) MMIO32(RCC_BASE + ((i) >> 5))

#define	_RCC_BIT(i) (1 << ((i) & 0x1f))

Functions
void	rcc_peripheral_enable_clock (volatile uint32_t *reg, uint32_t en)
	RCC Enable Peripheral Clocks. More...

void	rcc_peripheral_disable_clock (volatile uint32_t *reg, uint32_t en)
	RCC Disable Peripheral Clocks. More...

void	rcc_peripheral_reset (volatile uint32_t *reg, uint32_t reset)
	RCC Reset Peripherals. More...

void	rcc_peripheral_clear_reset (volatile uint32_t *reg, uint32_t clear_reset)
	RCC Remove Reset on Peripherals. More...

void	rcc_periph_clock_enable (enum rcc_periph_clken clken)
	Enable Peripheral Clock in running mode. More...

void	rcc_periph_clock_disable (enum rcc_periph_clken clken)
	Disable Peripheral Clock in running mode. More...

void	rcc_periph_reset_pulse (enum rcc_periph_rst rst)
	Reset Peripheral, pulsed. More...

void	rcc_periph_reset_hold (enum rcc_periph_rst rst)
	Reset Peripheral, hold. More...

void	rcc_periph_reset_release (enum rcc_periph_rst rst)
	Reset Peripheral, release. More...

void	rcc_set_mco (uint32_t mcosrc)
	Select the source of Microcontroller Clock Output. More...

void	rcc_osc_bypass_enable (enum rcc_osc osc)
	RCC Enable Bypass. More...

void	rcc_osc_bypass_disable (enum rcc_osc osc)
	RCC Disable Bypass. More...

uint16_t	rcc_get_div_from_hpre (uint8_t div_val)
	This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers. More...

void	rcc_osc_ready_int_clear (enum rcc_osc osc)

void	rcc_osc_ready_int_enable (enum rcc_osc osc)

void	rcc_osc_ready_int_disable (enum rcc_osc osc)

int	rcc_osc_ready_int_flag (enum rcc_osc osc)

void	rcc_css_int_clear (void)

int	rcc_css_int_flag (void)

bool	rcc_is_osc_ready (enum rcc_osc osc)
	Is the given oscillator ready? More...

void	rcc_wait_for_osc_ready (enum rcc_osc osc)
	Wait for Oscillator Ready. More...

void	rcc_wait_for_sysclk_status (enum rcc_osc osc)

void	rcc_osc_on (enum rcc_osc osc)

void	rcc_osc_off (enum rcc_osc osc)

void	rcc_css_enable (void)

void	rcc_css_disable (void)

void	rcc_set_sysclk_source (uint32_t clk)

void	rcc_set_pll_source (uint32_t pllsrc)

void	rcc_set_ppre2 (uint32_t ppre2)

void	rcc_set_ppre1 (uint32_t ppre1)

void	rcc_set_hpre (uint32_t hpre)

void	rcc_set_main_pll (uint32_t pllsrc, uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq, uint32_t pllr)
	Reconfigures the main PLL for a HSE source. More...

uint32_t	rcc_system_clock_source (void)

void	rcc_clock_setup_pll (const struct rcc_clock_scale *clock)
	Setup clocks to run from PLL. More...

void	rcc_clock_setup_hse_3v3 (const struct rcc_clock_scale *clock)
	Setup clocks with the HSE. More...

void	rcc_set_clock48_source (uint32_t clksel)
	Set clock source for 48MHz clock. More...

static uint32_t	rcc_get_clksel_freq (uint8_t shift)

uint32_t	rcc_get_usart_clk_freq (uint32_t usart)
	Get the peripheral clock speed for the specified (LP)UxART. More...

Variables
uint32_t	rcc_ahb_frequency = 16000000

uint32_t	rcc_apb1_frequency = 16000000

uint32_t	rcc_apb2_frequency = 16000000

const struct rcc_clock_scale	rcc_hsi_configs [RCC_CLOCK_3V3_END]

const struct rcc_clock_scale	rcc_hse_8mhz_3v3 [RCC_CLOCK_3V3_END]

const struct rcc_clock_scale	rcc_hse_12mhz_3v3 [RCC_CLOCK_3V3_END]

const struct rcc_clock_scale	rcc_hse_16mhz_3v3 [RCC_CLOCK_3V3_END]

Detailed Description

libopencm3 STM32G4xx Reset and Clock Control

Author: © 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>; © 2009 Uwe Hermann uwe@h.nosp@m.erma.nosp@m.nn-uw.nosp@m.e.de; © 2010 Thomas Otto tommi.nosp@m.@via.nosp@m.dmin..nosp@m.org; © 2013 Frantisek Burian <BuFran at seznam.cz>; © 2020 Sam Kirkham sam.k.nosp@m.irkh.nosp@m.am@co.nosp@m.deth.nosp@m.ink.c.nosp@m.o.uk; © 2020 Ben Brewer ben.b.nosp@m.rewe.nosp@m.r@cod.nosp@m.ethi.nosp@m.nk.co.nosp@m..uk

Date: 30 July 2020

This library supports the Reset and Clock Control System in the STM32 series of ARM Cortex Microcontrollers by ST Microelectronics.

LGPL License Terms libopencm3 License

Macro Definition Documentation

◆ _RCC_BIT

#define _RCC_BIT ( i ) (1 << ((i) & 0x1f))

Definition at line 117 of file rcc_common_all.c.

◆ _RCC_REG

#define _RCC_REG ( i ) MMIO32(RCC_BASE + ((i) >> 5))

Definition at line 116 of file rcc_common_all.c.

Function Documentation

◆ rcc_clock_setup_hse_3v3()

void rcc_clock_setup_hse_3v3 ( const struct rcc_clock_scale * clock )

Setup clocks with the HSE.

Deprecated:: replaced by rcc_clock_setup_pll as a drop in replacement.

See also: rcc_clock_setup_pll which supports HSI16 as well as HSE, using the same clock structures.

Definition at line 747 of file rcc.c.

References rcc_clock_setup_pll().

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◆ rcc_clock_setup_pll()

void rcc_clock_setup_pll ( const struct rcc_clock_scale * clock )

Setup clocks to run from PLL.

The arguments provide the pll source, multipliers, dividers, all that's needed to establish a system clock.

Parameters

clock clock information structure.

Definition at line 665 of file rcc.c.

Referenced by rcc_clock_setup_hse_3v3().

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◆ rcc_css_disable()

void rcc_css_disable ( void )

Definition at line 561 of file rcc.c.

References RCC_CR.

◆ rcc_css_enable()

void rcc_css_enable ( void )

Definition at line 556 of file rcc.c.

References RCC_CR, and RCC_CR_CSSON.

◆ rcc_css_int_clear()

void rcc_css_int_clear ( void )

Definition at line 453 of file rcc.c.

References RCC_CICR, and RCC_CICR_CSSC.

◆ rcc_css_int_flag()

int rcc_css_int_flag ( void )

Definition at line 458 of file rcc.c.

References RCC_CIFR, and RCC_CIFR_CSSF.

◆ rcc_get_clksel_freq()

static uint32_t rcc_get_clksel_freq ( uint8_t shift )

static

Definition at line 766 of file rcc.c.

References cm3_assert_not_reached, rcc_clock_scale::hpre, rcc_ahb_frequency, rcc_apb1_frequency, RCC_CCIPR, RCC_CCIPR_SEL_MASK, RCC_CCIPR_USARTxSEL_HSI16, RCC_CCIPR_USARTxSEL_LSE, RCC_CCIPR_USARTxSEL_PCLK, RCC_CCIPR_USARTxSEL_SYSCLK, RCC_CFGR, RCC_CFGR_HPRE_MASK, RCC_CFGR_HPRE_SHIFT, and rcc_get_div_from_hpre().

Referenced by rcc_get_usart_clk_freq().

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◆ rcc_get_div_from_hpre()

uint16_t rcc_get_div_from_hpre ( uint8_t div_val )

This will return the divisor 1/2/4/8/16/64/128/256/512 which is set as a 4-bit value, typically used for hpre and other prescalers.

Parameters

div_val Masked and shifted divider value from register (e.g. RCC_CFGR)

Definition at line 260 of file rcc_common_all.c.

Referenced by rcc_get_clksel_freq().

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◆ rcc_get_usart_clk_freq()

uint32_t rcc_get_usart_clk_freq ( uint32_t usart )

Get the peripheral clock speed for the specified (LP)UxART.

Parameters

usart Base address of USART to get clock frequency for.

Definition at line 783 of file rcc.c.

References cm3_assert_not_reached, LPUART1_BASE, RCC_CCIPR_LPUART1SEL_SHIFT, RCC_CCIPR_UART4SEL_SHIFT, RCC_CCIPR_UART5SEL_SHIFT, RCC_CCIPR_USART1SEL_SHIFT, RCC_CCIPR_USART2SEL_SHIFT, RCC_CCIPR_USART3SEL_SHIFT, rcc_get_clksel_freq(), UART4_BASE, UART5_BASE, USART1_BASE, USART2_BASE, and USART3_BASE.

Referenced by usart_set_baudrate().

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◆ rcc_is_osc_ready()

bool rcc_is_osc_ready ( enum rcc_osc osc )

Is the given oscillator ready?

Parameters

osc	Oscillator ID

Returns: true if the hardware indicates the oscillator is ready.

Definition at line 463 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSERDY, RCC_CR, RCC_CR_HSERDY, RCC_CR_HSIRDY, RCC_CR_PLLRDY, RCC_CRRCR, RCC_CRRCR_HSI48RDY, RCC_CSR, RCC_CSR_LSIRDY, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

Referenced by rcc_wait_for_osc_ready().

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◆ rcc_osc_bypass_disable()

void rcc_osc_bypass_disable ( enum rcc_osc osc )

RCC Disable Bypass.

Re-enable the internal clock (high speed and low speed clocks only). The internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note: The LSE clock is in the backup domain and cannot have bypass removed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect) or the backup domain has been reset (see rcc_backupdomain_reset).

Parameters

[in] osc Oscillator ID. Only HSE and LSE have effect.

Definition at line 238 of file rcc_common_all.c.

References RCC_BDCR, RCC_CR, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_bypass_enable()

void rcc_osc_bypass_enable ( enum rcc_osc osc )

RCC Enable Bypass.

Enable an external clock to bypass the internal clock (high speed and low speed clocks only). The external clock must be enabled (see rcc_osc_on) and the internal clock must be disabled (see rcc_osc_off) for this to have effect.

Note: The LSE clock is in the backup domain and cannot be bypassed until the backup domain write protection has been removed (see pwr_disable_backup_domain_write_protect).

Parameters

[in] osc Oscillator ID. Only HSE and LSE have effect.

Definition at line 208 of file rcc_common_all.c.

References RCC_BDCR, RCC_BDCR_LSEBYP, RCC_CR, RCC_CR_HSEBYP, RCC_CSR, RCC_HSE, and RCC_LSE.

◆ rcc_osc_off()

void rcc_osc_off ( enum rcc_osc osc )

Definition at line 532 of file rcc.c.

References RCC_BDCR, RCC_CR, RCC_CRRCR, RCC_CSR, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll().

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◆ rcc_osc_on()

void rcc_osc_on ( enum rcc_osc osc )

Definition at line 508 of file rcc.c.

References RCC_BDCR, RCC_BDCR_LSEON, RCC_CR, RCC_CR_HSEON, RCC_CR_HSION, RCC_CR_PLLON, RCC_CRRCR, RCC_CRRCR_HSI48ON, RCC_CSR, RCC_CSR_LSION, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

Referenced by rcc_clock_setup_pll().

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◆ rcc_osc_ready_int_clear()

void rcc_osc_ready_int_clear ( enum rcc_osc osc )

Definition at line 362 of file rcc.c.

References RCC_CICR, RCC_CICR_HSERDYC, RCC_CICR_HSI48RDYC, RCC_CICR_HSIRDYC, RCC_CICR_LSERDYC, RCC_CICR_LSIRDYC, RCC_CICR_PLLRDYC, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

◆ rcc_osc_ready_int_disable()

void rcc_osc_ready_int_disable ( enum rcc_osc osc )

Definition at line 410 of file rcc.c.

References RCC_CIER, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

◆ rcc_osc_ready_int_enable()

void rcc_osc_ready_int_enable ( enum rcc_osc osc )

Definition at line 386 of file rcc.c.

References RCC_CIER, RCC_CIER_HSERDYIE, RCC_CIER_HSI48RDYIE, RCC_CIER_HSIRDYIE, RCC_CIER_LSERDYIE, RCC_CIER_LSIRDYIE, RCC_CIER_PLLRDYIE, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

◆ rcc_osc_ready_int_flag()

int rcc_osc_ready_int_flag ( enum rcc_osc osc )

Definition at line 434 of file rcc.c.

References RCC_CIFR, RCC_CIFR_HSERDYF, RCC_CIFR_HSI48RDYF, RCC_CIFR_HSIRDYF, RCC_CIFR_LSERDYF, RCC_CIFR_LSIRDYF, RCC_CIFR_PLLRDYF, RCC_HSE, RCC_HSI16, RCC_HSI48, RCC_LSE, RCC_LSI, and RCC_PLL.

◆ rcc_periph_clock_disable()

void rcc_periph_clock_disable ( enum rcc_periph_clken clken )

Disable Peripheral Clock in running mode.

Disable the clock on particular peripheral.

Parameters

[in] clken rcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 139 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_periph_clock_enable()

void rcc_periph_clock_enable ( enum rcc_periph_clken clken )

Enable Peripheral Clock in running mode.

Enable the clock on particular peripheral.

Parameters

[in] clken rcc_periph_clken Peripheral RCC

For available constants, see rcc_periph_clken (RCC_UART1 for example)

Definition at line 127 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

Referenced by crs_autotrim_usb_enable(), rcc_clock_setup_pll(), and st_usbfs_v2_usbd_init().

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◆ rcc_periph_reset_hold()

void rcc_periph_reset_hold ( enum rcc_periph_rst rst )

Reset Peripheral, hold.

Reset particular peripheral, and hold in reset state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 166 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_pulse()

void rcc_periph_reset_pulse ( enum rcc_periph_rst rst )

Reset Peripheral, pulsed.

Reset particular peripheral, and restore to working state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 152 of file rcc_common_all.c.

References _RCC_BIT, and _RCC_REG.

◆ rcc_periph_reset_release()

void rcc_periph_reset_release ( enum rcc_periph_rst rst )

Reset Peripheral, release.

Restore peripheral from reset state to working state.

Parameters

[in] rst rcc_periph_rst Peripheral reset

For available constants, see rcc_periph_rst (RST_UART1 for example)

Definition at line 179 of file rcc_common_all.c.

References _RCC_REG.

◆ rcc_peripheral_clear_reset()

void rcc_peripheral_clear_reset	(	volatile uint32_t *	reg,
		uint32_t	clear_reset
	)

RCC Remove Reset on Peripherals.

Remove the reset on particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could have the reset removed simultaneously only if they are controlled by the same register.

See also: rcc_periph_reset_release for a less error prone version, if you only need to unreset a single peripheral.; rcc_periph_reset_pulse if you are only going to toggle reset anyway.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	clear_reset	Unsigned int32. Logical OR of all resets to be removed: If register is RCC_AHBRSTR, from RCC_AHBxRSTR reset values (full set) If register is RCC_APB1RSTR, from RCC_APB1RSTRx reset values (full set) If register is RCC_APB2RSTR, from RCC_APB2RSTR reset values

Definition at line 111 of file rcc_common_all.c.

◆ rcc_peripheral_disable_clock()

void rcc_peripheral_disable_clock	(	volatile uint32_t *	reg,
		uint32_t	en
	)

RCC Disable Peripheral Clocks.

Disable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be disabled simultaneously only if they are controlled by the same register.

See also: rcc_periph_clock_disable for a less error prone version, if you only need to disable a single peripheral.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	en	Unsigned int32. Logical OR of all enables to be used for disabling. If register is RCC_AHBENR, from RCC_AHBxENR enable values (full set) If register is RCC_APB1ENR, from RCC_APB1ENRx enable values (full set) If register is RCC_APB2ENR, from RCC_APB2ENR enable values

Definition at line 66 of file rcc_common_all.c.

◆ rcc_peripheral_enable_clock()

void rcc_peripheral_enable_clock	(	volatile uint32_t *	reg,
		uint32_t	en
	)

RCC Enable Peripheral Clocks.

Enable the clock on particular peripherals. There are three registers involved, each one controlling the enabling of clocks associated with the AHB, APB1 and APB2 respectively. Several peripherals could be enabled simultaneously only if they are controlled by the same register.

See also: rcc_periph_clock_enable for a less error prone version, if you only need to enable a single peripheral.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	en	Unsigned int32. Logical OR of all enables to be set If register is RCC_AHBENR, from RCC_AHBxENR enable values (full set) If register is RCC_APB1ENR, from RCC_APB1ENRx enable values (full set) If register is RCC_APB2ENR, from RCC_APB2ENR enable values

Definition at line 44 of file rcc_common_all.c.

◆ rcc_peripheral_reset()

void rcc_peripheral_reset	(	volatile uint32_t *	reg,
		uint32_t	reset
	)

RCC Reset Peripherals.

Reset particular peripherals. There are three registers involved, each one controlling reset of peripherals associated with the AHB, APB1 and APB2 respectively. Several peripherals could be reset simultaneously only if they are controlled by the same register.

See also: rcc_periph_reset_hold for a less error prone version, if you only need to reset a single peripheral.; rcc_periph_reset_pulse if you are only going to toggle reset anyway.

Parameters

[in]	*reg	Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
[in]	reset	Unsigned int32. Logical OR of all resets. If register is RCC_AHBRSTR, from RCC_AHBxRSTR reset values (full set) If register is RCC_APB1RSTR, from RCC_APB1RSTRx reset values (full set) If register is RCC_APB2RSTR, from RCC_APB2RSTR reset values

Definition at line 88 of file rcc_common_all.c.

◆ rcc_set_clock48_source()

void rcc_set_clock48_source ( uint32_t clksel )

Set clock source for 48MHz clock.

The 48 MHz clock is derived from one of the four following sources:

PLLQ VCO (RCC_CCIPR_CLK48_PLLQ)
HSI48 internal oscillator (RCC_CCIPR_CLK48_HSI48)

Parameters

clksel One of the definitions above

Definition at line 760 of file rcc.c.

References RCC_CCIPR, RCC_CCIPR_CLK48SEL_SHIFT, and RCC_CCIPR_SEL_MASK.

◆ rcc_set_hpre()

void rcc_set_hpre ( uint32_t hpre )

Definition at line 602 of file rcc.c.

References rcc_clock_scale::hpre, RCC_CFGR, RCC_CFGR_HPRE_MASK, and RCC_CFGR_HPRE_SHIFT.

Referenced by rcc_clock_setup_pll().

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◆ rcc_set_main_pll()

void rcc_set_main_pll	(	uint32_t	pllsrc,
		uint32_t	pllm,
		uint32_t	plln,
		uint32_t	pllp,
		uint32_t	pllq,
		uint32_t	pllr
	)

Reconfigures the main PLL for a HSE source.

Any reserved bits are kept at their reset values.

Parameters

pllsrc	Source for the main PLL input clock
pllm	Divider for the main PLL input clock
plln	Main PLL multiplication factor for VCO
pllp	Main PLL divider for ADC
pllq	Main PLL divider for QUADSPI, FDCAN, USB, SAI & I2S
pllr	Main PLL divider for main system clock