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| #define | RCC_CR MMIO32(RCC_BASE + 0x00) |
| |
| #define | RCC_ICSCR MMIO32(RCC_BASE + 0x04) |
| |
| #define | RCC_CFGR MMIO32(RCC_BASE + 0x08) |
| |
| #define | RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c) |
| |
| #define | RCC_CIER MMIO32(RCC_BASE + 0x18) |
| |
| #define | RCC_CIFR MMIO32(RCC_BASE + 0x1c) |
| |
| #define | RCC_CICR MMIO32(RCC_BASE + 0x20) |
| |
| #define | RCC_AHB1RSTR_OFFSET 0x28 |
| |
| #define | RCC_AHB1RSTR MMIO32(RCC_BASE + RCC_AHB1RSTR_OFFSET) |
| |
| #define | RCC_AHB2RSTR_OFFSET 0x2c |
| |
| #define | RCC_AHB2RSTR MMIO32(RCC_BASE + RCC_AHB2RSTR_OFFSET) |
| |
| #define | RCC_AHB3RSTR_OFFSET 0x30 |
| |
| #define | RCC_AHB3RSTR MMIO32(RCC_BASE + RCC_AHB3RSTR_OFFSET) |
| |
| #define | RCC_APB1RSTR1_OFFSET 0x38 |
| |
| #define | RCC_APB1RSTR1 MMIO32(RCC_BASE + RCC_APB1RSTR1_OFFSET) |
| |
| #define | RCC_APB1RSTR2_OFFSET 0x3c |
| |
| #define | RCC_APB1RSTR2 MMIO32(RCC_BASE + RCC_APB1RSTR2_OFFSET) |
| |
| #define | RCC_APB2RSTR_OFFSET 0x40 |
| |
| #define | RCC_APB2RSTR MMIO32(RCC_BASE + RCC_APB2RSTR_OFFSET) |
| |
| #define | RCC_AHB1ENR_OFFSET 0x48 |
| |
| #define | RCC_AHB1ENR MMIO32(RCC_BASE + RCC_AHB1ENR_OFFSET) |
| |
| #define | RCC_AHB2ENR_OFFSET 0x4c |
| |
| #define | RCC_AHB2ENR MMIO32(RCC_BASE + RCC_AHB2ENR_OFFSET) |
| |
| #define | RCC_AHB3ENR_OFFSET 0x50 |
| |
| #define | RCC_AHB3ENR MMIO32(RCC_BASE + RCC_AHB3ENR_OFFSET) |
| |
| #define | RCC_APB1ENR1_OFFSET 0x58 |
| |
| #define | RCC_APB1ENR1 MMIO32(RCC_BASE + RCC_APB1ENR1_OFFSET) |
| |
| #define | RCC_APB1ENR2_OFFSET 0x5c |
| |
| #define | RCC_APB1ENR2 MMIO32(RCC_BASE + RCC_APB1ENR2_OFFSET) |
| |
| #define | RCC_APB2ENR_OFFSET 0x60 |
| |
| #define | RCC_APB2ENR MMIO32(RCC_BASE + RCC_APB2ENR_OFFSET) |
| |
| #define | RCC_AHB1SMENR_OFFSET 0x68 |
| |
| #define | RCC_AHB1SMENR MMIO32(RCC_BASE + RCC_AHB1SMENR_OFFSET) |
| |
| #define | RCC_AHB2SMENR_OFFSET 0x6c |
| |
| #define | RCC_AHB2SMENR MMIO32(RCC_BASE + RCC_AHB2SMENR_OFFSET) |
| |
| #define | RCC_AHB3SMENR_OFFSET 0x70 |
| |
| #define | RCC_AHB3SMENR MMIO32(RCC_BASE + RCC_AHB3SMENR_OFFSET) |
| |
| #define | RCC_APB1SMENR1_OFFSET 0x78 |
| |
| #define | RCC_APB1SMENR1 MMIO32(RCC_BASE + RCC_APB1SMENR1_OFFSET) |
| |
| #define | RCC_APB1SMENR2_OFFSET 0x7c |
| |
| #define | RCC_APB1SMENR2 MMIO32(RCC_BASE + RCC_APB1SMENR2_OFFSET) |
| |
| #define | RCC_APB2SMENR_OFFSET 0x80 |
| |
| #define | RCC_APB2SMENR MMIO32(RCC_BASE + RCC_APB2SMENR_OFFSET) |
| |
| #define | RCC_CCIPR MMIO32(RCC_BASE + 0x88) |
| |
| #define | RCC_BDCR MMIO32(RCC_BASE + 0x90) |
| |
| #define | RCC_CSR MMIO32(RCC_BASE + 0x94) |
| |
| #define | RCC_CRRCR MMIO32(RCC_BASE + 0x98) |
| |
| #define | RCC_CCIPR2 MMIO32(RCC_BASE + 0x9c) |
| |
1.9.4