RCC_APB1RSTR1 reset values
Collaboration diagram for RCC_APB1RSTR1 reset values:
Macros | |
| #define | RCC_APB1RSTR1_LPTIM1RST (1 << 31) |
| #define | RCC_APB1RSTR1_I2C3RST (1 << 30) |
| #define | RCC_APB1RSTR1_PWRRST (1 << 28) |
| #define | RCC_APB1RSTR1_FDCANRST (1 << 25) |
| #define | RCC_APB1RSTR1_USBRST (1 << 23) |
| #define | RCC_APB1RSTR1_I2C2RST (1 << 22) |
| #define | RCC_APB1RSTR1_I2C1RST (1 << 21) |
| #define | RCC_APB1RSTR1_UART5RST (1 << 20) |
| #define | RCC_APB1RSTR1_UART4RST (1 << 19) |
| #define | RCC_APB1RSTR1_USART3RST (1 << 18) |
| #define | RCC_APB1RSTR1_USART2RST (1 << 17) |
| #define | RCC_APB1RSTR1_SPI3RST (1 << 15) |
| #define | RCC_APB1RSTR1_SPI2RST (1 << 14) |
| #define | RCC_APB1RSTR1_CRSRST (1 << 8) |
| #define | RCC_APB1RSTR1_TIM7RST (1 << 5) |
| #define | RCC_APB1RSTR1_TIM6RST (1 << 4) |
| #define | RCC_APB1RSTR1_TIM5RST (1 << 3) |
| #define | RCC_APB1RSTR1_TIM4RST (1 << 2) |
| #define | RCC_APB1RSTR1_TIM3RST (1 << 1) |
| #define | RCC_APB1RSTR1_TIM2RST (1 << 0) |
