Collaboration diagram for CFGR1 ADC configuration register 1:

Modules
	EXTEN: External trigger enable and polarity selection for regular channels

	RES: Data resolution

Macros
#define	ADC_CFGR1_AWD1CH_SHIFT 26

#define	ADC_CFGR1_AWD1CH (0x1F << ADC_CFGR1_AWD1CH_SHIFT)

#define	ADC_CFGR1_AWD1CH_VAL(x) ((x) << ADC_CFGR1_AWD1CH_SHIFT)
	AWD1CH: Analog watchdog 1 channel selection. More...

#define	ADC_CFGR1_AWD1EN (1 << 23)
	AWD1EN: Analog watchdog 1 enable on regular channels. More...

#define	ADC_CFGR1_AWD1SGL (1 << 22)
	AWD1SGL: Enable the watchdog 1 on a single channel or on all channels. More...

#define	ADC_CFGR1_DISCEN (1 << 16)
	DISCEN: Discontinuous mode for regular channels. More...

#define	ADC_CFGR1_AUTDLY (1 << 14)
	AUTDLY: Delayed conversion mode. More...

#define	ADC_CFGR1_CONT (1 << 13)
	CONT: Single / continuous conversion mode for regular conversions. More...

#define	ADC_CFGR1_OVRMOD (1 << 12)
	OVRMOD: Overrun Mode. More...

#define	ADC_CFGR1_EXTEN_MASK (0x3 << 10)

#define	ADC_CFGR1_RES_MASK (0x3 << 3)

#define	ADC_CFGR1_DMACFG (1 << 1)
	DMACFG: Direct memory access configuration. More...

#define	ADC_CFGR1_DMAEN (1 << 0)
	DMAEN: Direct memory access enable. More...

Detailed Description

Macro Definition Documentation

◆ ADC_CFGR1_AUTDLY

#define ADC_CFGR1_AUTDLY (1 << 14)

AUTDLY: Delayed conversion mode.

Definition at line 138 of file adc_common_v2.h.

◆ ADC_CFGR1_AWD1CH

#define ADC_CFGR1_AWD1CH (0x1F << ADC_CFGR1_AWD1CH_SHIFT)

Definition at line 127 of file adc_common_v2.h.

◆ ADC_CFGR1_AWD1CH_SHIFT

#define ADC_CFGR1_AWD1CH_SHIFT 26

Definition at line 126 of file adc_common_v2.h.

◆ ADC_CFGR1_AWD1CH_VAL

#define ADC_CFGR1_AWD1CH_VAL ( x ) ((x) << ADC_CFGR1_AWD1CH_SHIFT)

AWD1CH: Analog watchdog 1 channel selection.

Definition at line 129 of file adc_common_v2.h.

◆ ADC_CFGR1_AWD1EN

#define ADC_CFGR1_AWD1EN (1 << 23)

AWD1EN: Analog watchdog 1 enable on regular channels.

Definition at line 132 of file adc_common_v2.h.

◆ ADC_CFGR1_AWD1SGL

#define ADC_CFGR1_AWD1SGL (1 << 22)

AWD1SGL: Enable the watchdog 1 on a single channel or on all channels.

Definition at line 134 of file adc_common_v2.h.

◆ ADC_CFGR1_CONT

#define ADC_CFGR1_CONT (1 << 13)

CONT: Single / continuous conversion mode for regular conversions.

Definition at line 140 of file adc_common_v2.h.

◆ ADC_CFGR1_DISCEN

#define ADC_CFGR1_DISCEN (1 << 16)

DISCEN: Discontinuous mode for regular channels.

Definition at line 136 of file adc_common_v2.h.

◆ ADC_CFGR1_DMACFG

#define ADC_CFGR1_DMACFG (1 << 1)

DMACFG: Direct memory access configuration.

Definition at line 163 of file adc_common_v2.h.

◆ ADC_CFGR1_DMAEN

#define ADC_CFGR1_DMAEN (1 << 0)

DMAEN: Direct memory access enable.

Definition at line 166 of file adc_common_v2.h.

◆ ADC_CFGR1_EXTEN_MASK

#define ADC_CFGR1_EXTEN_MASK (0x3 << 10)

Definition at line 144 of file adc_common_v2.h.

◆ ADC_CFGR1_OVRMOD

#define ADC_CFGR1_OVRMOD (1 << 12)

OVRMOD: Overrun Mode.

Definition at line 142 of file adc_common_v2.h.

◆ ADC_CFGR1_RES_MASK

#define ADC_CFGR1_RES_MASK (0x3 << 3)

Definition at line 153 of file adc_common_v2.h.

Modules

Macros