Defined Constants and Types for the STM32G4xx Analog to Digital converter More...

Collaboration diagram for ADC Defines:

Modules
	ADC register base addresses

	ADC Sample Time Selection values

	ADC Multi mode selection

	ADC Channel Numbers

	ADC registers

	ISR ADC interrupt status register

	IER ADC interrupt enable register

	CR ADC control register

	CFGR1 ADC configuration register 1

	SMPR ADC sample time register

	CFGR2 ADC configuration register 2

	TR1 ADC watchdog threshold register 1

	CCR ADC common configuration register

Macros
#define	ADC_GCOMP(adc) MMIO32((adc) + 0xC0)
	ADC_GCOMP Gain compensation Register. More...

#define	ADC_CR_DEEPPWD (1 << 29)

#define	ADC_CR_ADVREGEN (1 << 28)
	ADVREGEN: ADC voltage regulator enable bit. More...

#define	ADC_CFGR1_ALIGN (1 << 15)
	ALIGN: Data alignment. More...

#define	ADC_CFGR1_EXTSEL_SHIFT 5
	EXTSEL[4:0]: External trigger selection for regular group. More...

#define	ADC_CFGR1_EXTSEL_MASK (0x1f << ADC_CFGR1_EXTSEL_SHIFT)

#define	ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT)

#define	ADC12_CFGR1_EXTSEL_TIM1_CC1 ADC_CFGR1_EXTSEL_VAL(0)
	CFGR1: ADC configuration register. More...

#define	ADC12_CFGR1_EXTSEL_TIM1_CC2 ADC_CFGR1_EXTSEL_VAL(1)

#define	ADC12_CFGR1_EXTSEL_TIM1_CC3 ADC_CFGR1_EXTSEL_VAL(2)

#define	ADC12_CFGR1_EXTSEL_TIM2_CC2 ADC_CFGR1_EXTSEL_VAL(3)

#define	ADC12_CFGR1_EXTSEL_TIM3_TRGO ADC_CFGR1_EXTSEL_VAL(4)

#define	ADC12_CFGR1_EXTSEL_TIM4_CC4 ADC_CFGR1_EXTSEL_VAL(5)

#define	ADC12_CFGR1_EXTSEL_EXTI11 ADC_CFGR1_EXTSEL_VAL(6)

#define	ADC12_CFGR1_EXTSEL_TIM8_TRGO ADC_CFGR1_EXTSEL_VAL(7)

#define	ADC12_CFGR1_EXTSEL_TIM8_TRGO2 ADC_CFGR1_EXTSEL_VAL(8)

#define	ADC12_CFGR1_EXTSEL_TIM1_TRGO ADC_CFGR1_EXTSEL_VAL(9)

#define	ADC12_CFGR1_EXTSEL_TIM1_TRGO2 ADC_CFGR1_EXTSEL_VAL(10)

#define	ADC12_CFGR1_EXTSEL_TIM2_TRGO ADC_CFGR1_EXTSEL_VAL(11)

#define	ADC12_CFGR1_EXTSEL_TIM4_TRGO ADC_CFGR1_EXTSEL_VAL(12)

#define	ADC12_CFGR1_EXTSEL_TIM6_TRGO ADC_CFGR1_EXTSEL_VAL(13)

#define	ADC12_CFGR1_EXTSEL_TIM15_TRGO ADC_CFGR1_EXTSEL_VAL(14)

#define	ADC12_CFGR1_EXTSEL_TIM3_CC4 ADC_CFGR1_EXTSEL_VAL(15)

#define	ADC12_CFGR1_EXTSEL_TIM20_TRGO ADC_CFGR1_EXTSEL_VAL(16)

#define	ADC12_CFGR1_EXTSEL_TIM20_TRGO2 ADC_CFGR1_EXTSEL_VAL(17)

#define	ADC12_CFGR1_EXTSEL_TIM20_CC1 ADC_CFGR1_EXTSEL_VAL(18)

#define	ADC12_CFGR1_EXTSEL_TIM20_CC2 ADC_CFGR1_EXTSEL_VAL(19)

#define	ADC12_CFGR1_EXTSEL_TIM20_CC3 ADC_CFGR1_EXTSEL_VAL(20)

#define	ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG1 ADC_CFGR1_EXTSEL_VAL(21)

#define	ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG3 ADC_CFGR1_EXTSEL_VAL(22)

#define	ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG5 ADC_CFGR1_EXTSEL_VAL(23)

#define	ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG6 ADC_CFGR1_EXTSEL_VAL(24)

#define	ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG7 ADC_CFGR1_EXTSEL_VAL(25)

#define	ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG8 ADC_CFGR1_EXTSEL_VAL(26)

#define	ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG9 ADC_CFGR1_EXTSEL_VAL(27)

#define	ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG10 ADC_CFGR1_EXTSEL_VAL(28)

#define	ADC12_CFGR1_EXTSEL_LPTIMOUT ADC_CFGR1_EXTSEL_VAL(29)

#define	ADC12_CFGR1_EXTSEL_TIM7_TRGO ADC_CFGR1_EXTSEL_VAL(30)

#define	ADC345_CFGR1_EXTSEL_TIM3_CC1 ADC_CFGR1_EXTSEL_VAL(0)

#define	ADC345_CFGR1_EXTSEL_TIM2_CC3 ADC_CFGR1_EXTSEL_VAL(1)

#define	ADC345_CFGR1_EXTSEL_TIM1_CC3 ADC_CFGR1_EXTSEL_VAL(2)

#define	ADC345_CFGR1_EXTSEL_TIM8_CC1 ADC_CFGR1_EXTSEL_VAL(3)

#define	ADC345_CFGR1_EXTSEL_TIM3_TRGO ADC_CFGR1_EXTSEL_VAL(4)

#define	ADC345_CFGR1_EXTSEL_EXTI2 ADC_CFGR1_EXTSEL_VAL(5)

#define	ADC345_CFGR1_EXTSEL_TIM4_CC1 ADC_CFGR1_EXTSEL_VAL(6)

#define	ADC345_CFGR1_EXTSEL_TIM8_TRGO ADC_CFGR1_EXTSEL_VAL(7)

#define	ADC345_CFGR1_EXTSEL_TIM8_TRGO2 ADC_CFGR1_EXTSEL_VAL(8)

#define	ADC345_CFGR1_EXTSEL_TIM1_TRGO ADC_CFGR1_EXTSEL_VAL(9)

#define	ADC345_CFGR1_EXTSEL_TIM1_TRGO2 ADC_CFGR1_EXTSEL_VAL(10)

#define	ADC345_CFGR1_EXTSEL_TIM2_TRGO ADC_CFGR1_EXTSEL_VAL(11)

#define	ADC345_CFGR1_EXTSEL_TIM4_TRGO ADC_CFGR1_EXTSEL_VAL(12)

#define	ADC345_CFGR1_EXTSEL_TIM6_TRGO ADC_CFGR1_EXTSEL_VAL(13)

#define	ADC345_CFGR1_EXTSEL_TIM15_TRGO ADC_CFGR1_EXTSEL_VAL(14)

#define	ADC345_CFGR1_EXTSEL_TIM2_CC1 ADC_CFGR1_EXTSEL_VAL(15)

#define	ADC345_CFGR1_EXTSEL_TIM20_TRGO ADC_CFGR1_EXTSEL_VAL(16)

#define	ADC345_CFGR1_EXTSEL_TIM20_TRGO2 ADC_CFGR1_EXTSEL_VAL(17)

#define	ADC345_CFGR1_EXTSEL_TIM20_CC1 ADC_CFGR1_EXTSEL_VAL(18)

#define	ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG2 ADC_CFGR1_EXTSEL_VAL(19)

#define	ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG4 ADC_CFGR1_EXTSEL_VAL(20)

#define	ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG1 ADC_CFGR1_EXTSEL_VAL(21)

#define	ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG3 ADC_CFGR1_EXTSEL_VAL(22)

#define	ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG5 ADC_CFGR1_EXTSEL_VAL(23)

#define	ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG6 ADC_CFGR1_EXTSEL_VAL(24)

#define	ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG7 ADC_CFGR1_EXTSEL_VAL(25)

#define	ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG8 ADC_CFGR1_EXTSEL_VAL(26)

#define	ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG9 ADC_CFGR1_EXTSEL_VAL(27)

#define	ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG10 ADC_CFGR1_EXTSEL_VAL(28)

#define	ADC345_CFGR1_EXTSEL_LPTIMOUT ADC_CFGR1_EXTSEL_VAL(29)

#define	ADC345_CFGR1_EXTSEL_TIM7_TRGO ADC_CFGR1_EXTSEL_VAL(30)

#define	ADC_CFGR2_ROVSE (1 << 0)
	ROVSE: Regular Oversampling Enable. More...

#define	ADC_CFGR2_JOVSE (1 << 1)
	JOVSE: Injected Oversampling Enable. More...

#define	ADC_CFGR2_OVSR_SHIFT 2
	OVSR[2:0]: Oversampling ratio. More...

#define	ADC_CFGR2_OVSR_MASK (0x7 << ADC_CFGR2_OVSR_SHIFT)

#define	ADC_CFGR2_OVSR_VAL(x) ((x) << ADC_CFGR2_OVSR_SHIFT)

#define	ADC_CFGR2_OVSR_2x ADC_CFGR2_OVSR_VAL(0)

#define	ADC_CFGR2_OVSR_4x ADC_CFGR2_OVSR_VAL(1)

#define	ADC_CFGR2_OVSR_8x ADC_CFGR2_OVSR_VAL(2)

#define	ADC_CFGR2_OVSR_16x ADC_CFGR2_OVSR_VAL(3)

#define	ADC_CFGR2_OVSR_32x ADC_CFGR2_OVSR_VAL(4)

#define	ADC_CFGR2_OVSR_64x ADC_CFGR2_OVSR_VAL(5)

#define	ADC_CFGR2_OVSR_128x ADC_CFGR2_OVSR_VAL(6)

#define	ADC_CFGR2_OVSR_256x ADC_CFGR2_OVSR_VAL(7)

#define	ADC_CFGR2_OVSS_SHIFT 5
	OVSS[3:0]: Oversampling shift. More...

#define	ADC_CFGR2_OVSS_MASK (0xf << ADC_CFGR2_OVSS_SHIFT)

#define	ADC_CFGR2_OVSS_VAL(x) ((x) << ADC_CFGR2_OVSS_SHIFT)

#define	ADC_CFGR2_TROVS (1 << 9)
	TROVS: Triggered Regular Oversampling. More...

#define	ADC_CFGR2_ROVSM (1 << 10)
	ROVSM: Regular Oversampling mode. More...

#define	ADC_CFGR2_GCOMP (1 << 16)
	GCOMP: Gain compensation mode. More...

#define	ADC_CFGR2_SWTRIG (1 << 25)
	SWTRIG: Software trigger bit for sampling time control trigger mode. More...

#define	ADC_CFGR2_BULB (1 << 26)
	BULB: Bulb sampling mode. More...

#define	ADC_CFGR2_SMPTRIG (1 << 27)
	SMPTRIG: Sampling time control trigger mode. More...

#define	ADC_JSQR_JL_LSB 0

#define	ADC_JSQR_JL_SHIFT 0

#define	ADC_JSQR_JSQ4_LSB 27

#define	ADC_JSQR_JSQ3_LSB 21

#define	ADC_JSQR_JSQ2_LSB 15

#define	ADC_JSQR_JSQ1_LSB 9

#define	ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 6 + 8))

#define	ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_SHIFT)

#define	ADC_JSQR_JEXTEN_DISABLED (0x0 << 7)

#define	ADC_JSQR_JEXTEN_RISING_EDGE (0x1 << 7)

#define	ADC_JSQR_JEXTEN_FALLING_EDGE (0x2 << 7)

#define	ADC_JSQR_JEXTEN_BOTH_EDGES (0x3 << 7)

#define	ADC_JSQR_JEXTEN_MASK (0x3 << 7)

#define	ADC_JSQR_JEXTSEL_SHIFT 2

#define	ADC12_JSQR_JEXTSEL_TIM1_TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM1_CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM2_TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM2_CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM3_CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM4_TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_EXTI15 (6 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM8_CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM1_TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM8_TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM8_TRGO2 (10 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM3_CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM3_TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM3_CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM6_TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM15_TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM20_TRGO (16 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM20_TRGO2 (17 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM20_CC4 (18 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG2 (19 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG4 (20 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG5 (21 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG6 (22 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG7 (23 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG8 (24 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG9 (25 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG10 (26 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM16_CC1 (27 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_LPTIMOUT (29 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC12_JSQR_JEXTSEL_TIM7_TRGO (30 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM1_TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM1_CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM2_TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM8_CC2 (3 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM4_CC3 (4 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM4_TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM4_CC4 (6 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM8_CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM1_TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM8_TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM8_TRGO2 (10 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM1_CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM3_TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_EXTI3 (13 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM6_TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM15_TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM20_TRGO (16 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM20_TRGO2 (17 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM20_CC2 (18 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG2 (19 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG4 (20 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG5 (21 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG6 (22 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG7 (23 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG8 (24 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG9 (25 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG10 (26 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG1 (27 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG3 (28 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_LPTIMOUT (29 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC345_JSQR_JEXTSEL_TIM7_TRGO (30 << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC_JSQR_JEXTSEL_MASK (0x1F << ADC_JSQR_JEXTSEL_SHIFT)

#define	ADC_JSQR_JL_1_CONVERSION (0x0 << 0)

#define	ADC_JSQR_JL_2_CONVERSIONS (0x1 << 0)

#define	ADC_JSQR_JL_3_CONVERSIONS (0x2 << 0)

#define	ADC_JSQR_JL_4_CONVERSIONS (0x3 << 0)

#define	ADC_OFR1_OFFSET1_EN (1 << 31)

#define	ADC_OFR2_OFFSET2_EN (1 << 31)

#define	ADC_OFR3_OFFSET3_EN (1 << 31)

#define	ADC_OFR4_OFFSET4_EN (1 << 31)

#define	ADC_CSR_JQOVF_SLV (1 << 26)

#define	ADC_CSR_AWD3_SLV (1 << 25)

#define	ADC_CSR_AWD2_SLV (1 << 24)

#define	ADC_CSR_AWD1_SLV (1 << 23)

#define	ADC_CSR_JEOS_SLV (1 << 22)

#define	ADC_CSR_JEOC_SLV (1 << 21)

#define	ADC_CSR_OVR_SLV (1 << 20)

#define	ADC_CSR_EOS_SLV (1 << 19)

#define	ADC_CSR_EOC_SLV (1 << 18)

#define	ADC_CSR_EOSMP_SLV (1 << 17)

#define	ADC_CSR_ADRDY_SLV (1 << 16)

#define	ADC_CSR_JQOVF_MST (1 << 10)

#define	ADC_CSR_AWD3_MST (1 << 9)

#define	ADC_CSR_AWD2_MST (1 << 8)

#define	ADC_CSR_AWD1_MST (1 << 7)

#define	ADC_CSR_JEOS_MST (1 << 6)

#define	ADC_CSR_JEOC_MST (1 << 5)

#define	ADC_CSR_OVR_MST (1 << 4)

#define	ADC_CSR_EOS_MST (1 << 3)

#define	ADC_CSR_EOC_MST (1 << 2)

#define	ADC_CSR_EOSMP_MST (1 << 1)

#define	ADC_CSR_ADRDY_MST (1 << 0)

#define	ADC_CCR_DUAL_MASK (0x1f)

#define	ADC_CCR_DUAL_SHIFT 0

#define	ADC_CHANNEL_COUNT 19

#define	ADC_CHANNEL_IS_FAST(x) ((x) <= 5)

#define	ADC_ISR_JQOVF (1 << 10)

#define	ADC_ISR_AWD3 (1 << 9)

#define	ADC_ISR_AWD2 (1 << 8)

#define	ADC_ISR_JEOS (1 << 6)

#define	ADC_ISR_JEOC (1 << 5)

#define	ADC_IER_JQOVFIE (1 << 10)

#define	ADC_IER_AWD3IE (1 << 9)

#define	ADC_IER_AWD2IE (1 << 8)

#define	ADC_IER_JEOSIE (1 << 6)

#define	ADC_IER_JEOCIE (1 << 5)

#define	ADC_CR_ADCALDIF (1 << 30)

#define	ADC_CR_JADSTP (1 << 5)

#define	ADC_CR_JADSTART (1 << 3)

#define	ADC_CFGR1_JAUTO (1 << 25)

#define	ADC_CFGR1_JAWD1EN (1 << 24)

#define	ADC_CFGR1_JQM (1 << 21)

#define	ADC_CFGR1_JDISCEN (1 << 20)

#define	ADC_CFGR1_DISCNUM_SHIFT 17

#define	ADC_CFGR1_DISCNUM_MASK (0x7 << ADC_CFGR1_DISCNUM_SHIFT)

#define	ADC_CFGR1_DISCNUM_VAL(x) (((x) - 1) << ADC_CFGR1_DISCNUM_SHIFT)

#define	ADC_SQR1_L_SHIFT 0

#define	ADC_SQR1_L_MASK 0xf

#define	ADC_SQRx_SQx_MASK 0x1f

#define	ADC_SQR1_SQ1_SHIFT 6

#define	ADC_SQR1_SQ2_SHIFT 12

#define	ADC_SQR1_SQ3_SHIFT 18

#define	ADC_SQR1_SQ4_SHIFT 24

#define	ADC_SQR2_SQ5_SHIFT 0

#define	ADC_SQR2_SQ6_SHIFT 6

#define	ADC_SQR2_SQ7_SHIFT 12

#define	ADC_SQR2_SQ8_SHIFT 18

#define	ADC_SQR2_SQ9_SHIFT 24

#define	ADC_SQR3_SQ10_SHIFT 0

#define	ADC_SQR3_SQ11_SHIFT 6

#define	ADC_SQR3_SQ12_SHIFT 12

#define	ADC_SQR3_SQ13_SHIFT 18

#define	ADC_SQR3_SQ14_SHIFT 24

#define	ADC_SQR4_SQ15_SHIFT 0

#define	ADC_SQR4_SQ16_SHIFT 6

Functions
void	adc_enable_analog_watchdog_regular (uint32_t adc)
	ADC Enable Analog Watchdog for Regular Conversions. More...

void	adc_disable_analog_watchdog_regular (uint32_t adc)
	ADC Enable Analog Watchdog for Regular Conversions. More...

void	adc_enable_analog_watchdog_injected (uint32_t adc)
	ADC Enable Analog Watchdog for Injected Conversions. More...

void	adc_disable_analog_watchdog_injected (uint32_t adc)
	ADC Disable Analog Watchdog for Injected Conversions. More...

void	adc_enable_discontinuous_mode_regular (uint32_t adc, uint8_t length)
	ADC Enable Discontinuous Mode for Regular Conversions. More...

void	adc_disable_discontinuous_mode_regular (uint32_t adc)
	ADC Disable Discontinuous Mode for Regular Conversions. More...

void	adc_enable_discontinuous_mode_injected (uint32_t adc)
	ADC Enable Discontinuous Mode for Injected Conversions. More...

void	adc_disable_discontinuous_mode_injected (uint32_t adc)
	ADC Disable Discontinuous Mode for Injected Conversions. More...

void	adc_enable_automatic_injected_group_conversion (uint32_t adc)
	ADC Enable Automatic Injected Conversions. More...

void	adc_disable_automatic_injected_group_conversion (uint32_t adc)
	ADC Disable Automatic Injected Conversions. More...

void	adc_enable_analog_watchdog_on_all_channels (uint32_t adc)
	ADC Enable Analog Watchdog for All Regular and/or Injected Channels. More...

void	adc_enable_analog_watchdog_on_selected_channel (uint32_t adc, uint8_t channel)
	ADC Enable Analog Watchdog for a Selected Channel. More...

void	adc_enable_eoc_interrupt_injected (uint32_t adc)
	ADC Enable Injected End-Of-Conversion Interrupt. More...

void	adc_disable_eoc_interrupt_injected (uint32_t adc)
	ADC Disable Injected End-Of-Conversion Interrupt. More...

void	adc_enable_eos_interrupt_injected (uint32_t adc)
	ADC Enable Injected End-Of-Sequence Interrupt. More...

void	adc_disable_eos_interrupt_injected (uint32_t adc)
	ADC Disable Injected End-Of-Sequence Interrupt. More...

void	adc_enable_all_awd_interrupt (uint32_t adc)
	ADC Enable Analog Watchdog Interrupt. More...

void	adc_disable_all_awd_interrupt (uint32_t adc)
	ADC Disable Analog Watchdog Interrupt. More...

void	adc_enable_eos_interrupt (uint32_t adc)
	ADC Enable Regular End-Of-Sequence Interrupt. More...

void	adc_disable_eos_interrupt (uint32_t adc)
	ADC Disable Regular End-Of-Sequence Interrupt. More...

void	adc_start_conversion_injected (uint32_t adc)
	ADC Software Triggered Conversion on Injected Channels. More...

void	adc_disable_external_trigger_regular (uint32_t adc)
	ADC Disable an External Trigger for Regular Channels. More...

void	adc_disable_external_trigger_injected (uint32_t adc)
	ADC Disable an External Trigger for Injected Channels. More...

void	adc_set_watchdog_high_threshold (uint32_t adc, uint16_t threshold)
	ADC Set Analog Watchdog Upper Threshold. More...

void	adc_set_watchdog_low_threshold (uint32_t adc, uint16_t threshold)
	ADC Set Analog Watchdog Lower Threshold. More...

void	adc_set_injected_sequence (uint32_t adc, uint8_t length, uint8_t channel[])
	ADC Set an Injected Channel Conversion Sequence. More...

bool	adc_eoc_injected (uint32_t adc)
	ADC Read the End-of-Conversion Flag for Injected Conversion. More...

bool	adc_eos_injected (uint32_t adc)
	ADC Read the End-of-Sequence Flag for Injected Conversions. More...

uint32_t	adc_read_injected (uint32_t adc, uint8_t reg)
	ADC Read from an Injected Conversion Result Register. More...

void	adc_set_injected_offset (uint32_t adc, uint8_t reg, uint32_t offset)
	ADC Set the Injected Channel Data Offset. More...

void	adc_set_clk_source (uint32_t adc, uint32_t source)
	ADC Set Clock Source. More...

void	adc_set_clk_prescale (uint32_t adc, uint32_t prescale)
	ADC Set Clock Prescale. More...

void	adc_set_multi_mode (uint32_t adc, uint32_t mode)
	ADC set multi mode. More...

void	adc_enable_external_trigger_regular (uint32_t adc, uint32_t trigger, uint32_t polarity)
	ADC Enable an External Trigger for Regular Channels. More...

void	adc_enable_external_trigger_injected (uint32_t adc, uint32_t trigger, uint32_t polarity)
	ADC Enable an External Trigger for Injected Channels. More...

bool	adc_awd (uint32_t adc)
	ADC Read the Analog Watchdog Flag. More...

void	adc_enable_deeppwd (uint32_t adc)
	ADC Enable Deep-Power-Down Mdoe. More...

void	adc_disable_deeppwd (uint32_t adc)
	ADC Disable Deep-Power-Down Mdoe. More...

void	adc_power_on_async (uint32_t adc)
	Turn on the ADC (async) More...

void	adc_power_on (uint32_t adc)
	Turn on the ADC. More...

bool	adc_is_power_on (uint32_t adc)
	Is the ADC powered up and ready? More...

void	adc_power_off_async (uint32_t adc)
	Turn off the ADC (async) This will actually block if it needs to turn off a currently running conversion, as per ref man. More...

void	adc_power_off (uint32_t adc)
	Turn off the ADC This will actually block if it needs to turn off a currently running conversion, as per ref man. More...

bool	adc_is_power_off (uint32_t adc)
	Is the ADC powered down? More...

void	adc_calibrate_async (uint32_t adc)
	Start the ADC calibration and immediately return. More...

bool	adc_is_calibrating (uint32_t adc)
	Is the ADC Calibrating? More...

void	adc_calibrate (uint32_t adc)
	Start ADC calibration and wait for it to finish. More...

void	adc_set_continuous_conversion_mode (uint32_t adc)
	Enable Continuous Conversion Mode In this mode the ADC starts a new conversion of a single channel or a channel group immediately following completion of the previous channel group conversion. More...

void	adc_set_single_conversion_mode (uint32_t adc)
	Enable Single Conversion Mode In this mode the ADC performs a conversion of one channel or a channel group and stops. More...

void	adc_set_regular_sequence (uint32_t adc, uint8_t length, uint8_t channel[])
	ADC Set a Regular Channel Conversion Sequence. More...

void	adc_set_sample_time_on_all_channels (uint32_t adc, uint8_t time)
	ADC Set the Sample Time for All Channels. More...

void	adc_enable_temperature_sensor (void)
	Enable the temperature sensor (only) The channel this is available on is unfortunately not consistent, even though the bit used to enable it is. More...

void	adc_disable_temperature_sensor (void)
	Disable the temperature sensor (only) More...

void	adc_enable_vrefint (void)
	Enable the internal voltage reference (only) The channel this is available on is unfortunately not consistent, even though the bit used to enable it is. More...

void	adc_disable_vrefint (void)
	Disable the internal voltage reference (only) More...

void	adc_set_resolution (uint32_t adc, uint16_t resolution)
	ADC Set Resolution. More...

void	adc_set_left_aligned (uint32_t adc)
	ADC Set the Data as Left Aligned. More...

void	adc_set_right_aligned (uint32_t adc)
	ADC Set the Data as Right Aligned. More...

void	adc_enable_dma (uint32_t adc)
	ADC Enable DMA Transfers. More...

void	adc_disable_dma (uint32_t adc)
	ADC Disable DMA Transfers. More...

bool	adc_eoc (uint32_t adc)
	ADC Read the End-of-Conversion Flag. More...

bool	adc_eos (uint32_t adc)
	ADC Read the End-of-Sequence Flag for Regular Conversions. More...

void	adc_enable_eoc_interrupt (uint32_t adc)
	ADC Enable Regular End-Of-Conversion Interrupt. More...

void	adc_disable_eoc_interrupt (uint32_t adc)
	ADC Disable Regular End-Of-Conversion Interrupt. More...

void	adc_enable_overrun_interrupt (uint32_t adc)
	ADC Enable the Overrun Interrupt. More...

void	adc_disable_overrun_interrupt (uint32_t adc)
	ADC Disable the Overrun Interrupt. More...

bool	adc_get_overrun_flag (uint32_t adc)
	ADC Read the Overrun Flag. More...

void	adc_clear_overrun_flag (uint32_t adc)
	ADC Clear Overrun Flags. More...

uint32_t	adc_read_regular (uint32_t adc)
	ADC Read from the Regular Conversion Result Register. More...

void	adc_start_conversion_regular (uint32_t adc)
	ADC Software Triggered Conversion on Regular Channels. More...

void	adc_enable_dma_circular_mode (uint32_t adc)
	Enable circular mode for DMA transfers. More...

void	adc_disable_dma_circular_mode (uint32_t adc)
	Disable circular mode for DMA transfers. More...

void	adc_enable_delayed_conversion_mode (uint32_t adc)
	Enable Delayed Conversion Mode. More...

void	adc_disable_delayed_conversion_mode (uint32_t adc)
	Enable Delayed Conversion Mode. More...

void	adc_set_sample_time (uint32_t adc, uint8_t channel, uint8_t time)
	ADC Set the Sample Time for a Single Channel. More...

void	adc_enable_regulator (uint32_t adc)
	Enable the ADC Voltage regulator Before any use of the ADC, the ADC Voltage regulator must be enabled. More...

void	adc_disable_regulator (uint32_t adc)
	Disable the ADC Voltage regulator You can disable the adc vreg when not in use to save power. More...

Detailed Description

Defined Constants and Types for the STM32G4xx Analog to Digital converter

Version: 1.0.0

Date: 10 Jul 2020

LGPL License Terms libopencm3 License

Author: © 2015 Karl Palsson karlp.nosp@m.@twe.nosp@m.ak.ne.nosp@m.t.au

Macro Definition Documentation

◆ ADC12_CFGR1_EXTSEL_EXTI11

#define ADC12_CFGR1_EXTSEL_EXTI11 ADC_CFGR1_EXTSEL_VAL(6)

Definition at line 79 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG1

#define ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG1 ADC_CFGR1_EXTSEL_VAL(21)

Definition at line 94 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG10

#define ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG10 ADC_CFGR1_EXTSEL_VAL(28)

Definition at line 101 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG3

#define ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG3 ADC_CFGR1_EXTSEL_VAL(22)

Definition at line 95 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG5

#define ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG5 ADC_CFGR1_EXTSEL_VAL(23)

Definition at line 96 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG6

#define ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG6 ADC_CFGR1_EXTSEL_VAL(24)

Definition at line 97 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG7

#define ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG7 ADC_CFGR1_EXTSEL_VAL(25)

Definition at line 98 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG8

#define ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG8 ADC_CFGR1_EXTSEL_VAL(26)

Definition at line 99 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG9

#define ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG9 ADC_CFGR1_EXTSEL_VAL(27)

Definition at line 100 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_LPTIMOUT

#define ADC12_CFGR1_EXTSEL_LPTIMOUT ADC_CFGR1_EXTSEL_VAL(29)

Definition at line 102 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_TIM15_TRGO

#define ADC12_CFGR1_EXTSEL_TIM15_TRGO ADC_CFGR1_EXTSEL_VAL(14)

Definition at line 87 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_TIM1_CC1

#define ADC12_CFGR1_EXTSEL_TIM1_CC1 ADC_CFGR1_EXTSEL_VAL(0)

CFGR1: ADC configuration register.

Definition at line 73 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_TIM1_CC2

#define ADC12_CFGR1_EXTSEL_TIM1_CC2 ADC_CFGR1_EXTSEL_VAL(1)

Definition at line 74 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_TIM1_CC3

#define ADC12_CFGR1_EXTSEL_TIM1_CC3 ADC_CFGR1_EXTSEL_VAL(2)

Definition at line 75 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_TIM1_TRGO

#define ADC12_CFGR1_EXTSEL_TIM1_TRGO ADC_CFGR1_EXTSEL_VAL(9)

Definition at line 82 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_TIM1_TRGO2

#define ADC12_CFGR1_EXTSEL_TIM1_TRGO2 ADC_CFGR1_EXTSEL_VAL(10)

Definition at line 83 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_TIM20_CC1

#define ADC12_CFGR1_EXTSEL_TIM20_CC1 ADC_CFGR1_EXTSEL_VAL(18)

Definition at line 91 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_TIM20_CC2

#define ADC12_CFGR1_EXTSEL_TIM20_CC2 ADC_CFGR1_EXTSEL_VAL(19)

Definition at line 92 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_TIM20_CC3

#define ADC12_CFGR1_EXTSEL_TIM20_CC3 ADC_CFGR1_EXTSEL_VAL(20)

Definition at line 93 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_TIM20_TRGO

#define ADC12_CFGR1_EXTSEL_TIM20_TRGO ADC_CFGR1_EXTSEL_VAL(16)

Definition at line 89 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_TIM20_TRGO2

#define ADC12_CFGR1_EXTSEL_TIM20_TRGO2 ADC_CFGR1_EXTSEL_VAL(17)

Definition at line 90 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_TIM2_CC2

#define ADC12_CFGR1_EXTSEL_TIM2_CC2 ADC_CFGR1_EXTSEL_VAL(3)

Definition at line 76 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_TIM2_TRGO

#define ADC12_CFGR1_EXTSEL_TIM2_TRGO ADC_CFGR1_EXTSEL_VAL(11)

Definition at line 84 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_TIM3_CC4

#define ADC12_CFGR1_EXTSEL_TIM3_CC4 ADC_CFGR1_EXTSEL_VAL(15)

Definition at line 88 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_TIM3_TRGO

#define ADC12_CFGR1_EXTSEL_TIM3_TRGO ADC_CFGR1_EXTSEL_VAL(4)

Definition at line 77 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_TIM4_CC4

#define ADC12_CFGR1_EXTSEL_TIM4_CC4 ADC_CFGR1_EXTSEL_VAL(5)

Definition at line 78 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_TIM4_TRGO

#define ADC12_CFGR1_EXTSEL_TIM4_TRGO ADC_CFGR1_EXTSEL_VAL(12)

Definition at line 85 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_TIM6_TRGO

#define ADC12_CFGR1_EXTSEL_TIM6_TRGO ADC_CFGR1_EXTSEL_VAL(13)

Definition at line 86 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_TIM7_TRGO

#define ADC12_CFGR1_EXTSEL_TIM7_TRGO ADC_CFGR1_EXTSEL_VAL(30)

Definition at line 103 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_TIM8_TRGO

#define ADC12_CFGR1_EXTSEL_TIM8_TRGO ADC_CFGR1_EXTSEL_VAL(7)

Definition at line 80 of file g4/adc.h.

◆ ADC12_CFGR1_EXTSEL_TIM8_TRGO2

#define ADC12_CFGR1_EXTSEL_TIM8_TRGO2 ADC_CFGR1_EXTSEL_VAL(8)

Definition at line 81 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_EXTI15

#define ADC12_JSQR_JEXTSEL_EXTI15 (6 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 262 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG10

#define ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG10 (26 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 282 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG2

#define ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG2 (19 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 275 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG4

#define ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG4 (20 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 276 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG5

#define ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG5 (21 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 277 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG6

#define ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG6 (22 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 278 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG7

#define ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG7 (23 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 279 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG8

#define ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG8 (24 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 280 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG9

#define ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG9 (25 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 281 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_LPTIMOUT

#define ADC12_JSQR_JEXTSEL_LPTIMOUT (29 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 284 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_TIM15_TRGO

#define ADC12_JSQR_JEXTSEL_TIM15_TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 271 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_TIM16_CC1

#define ADC12_JSQR_JEXTSEL_TIM16_CC1 (27 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 283 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_TIM1_CC4

#define ADC12_JSQR_JEXTSEL_TIM1_CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 257 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_TIM1_TRGO

#define ADC12_JSQR_JEXTSEL_TIM1_TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 256 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_TIM1_TRGO2

#define ADC12_JSQR_JEXTSEL_TIM1_TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 264 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_TIM20_CC4

#define ADC12_JSQR_JEXTSEL_TIM20_CC4 (18 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 274 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_TIM20_TRGO

#define ADC12_JSQR_JEXTSEL_TIM20_TRGO (16 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 272 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_TIM20_TRGO2

#define ADC12_JSQR_JEXTSEL_TIM20_TRGO2 (17 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 273 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_TIM2_CC1

#define ADC12_JSQR_JEXTSEL_TIM2_CC1 (3 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 259 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_TIM2_TRGO

#define ADC12_JSQR_JEXTSEL_TIM2_TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 258 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_TIM3_CC1

#define ADC12_JSQR_JEXTSEL_TIM3_CC1 (13 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 269 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_TIM3_CC3

#define ADC12_JSQR_JEXTSEL_TIM3_CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 267 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_TIM3_CC4

#define ADC12_JSQR_JEXTSEL_TIM3_CC4 (4 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 260 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_TIM3_TRGO

#define ADC12_JSQR_JEXTSEL_TIM3_TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 268 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_TIM4_TRGO

#define ADC12_JSQR_JEXTSEL_TIM4_TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 261 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_TIM6_TRGO

#define ADC12_JSQR_JEXTSEL_TIM6_TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 270 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_TIM7_TRGO

#define ADC12_JSQR_JEXTSEL_TIM7_TRGO (30 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 285 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_TIM8_CC4

#define ADC12_JSQR_JEXTSEL_TIM8_CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 263 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_TIM8_TRGO

#define ADC12_JSQR_JEXTSEL_TIM8_TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 265 of file g4/adc.h.

◆ ADC12_JSQR_JEXTSEL_TIM8_TRGO2

#define ADC12_JSQR_JEXTSEL_TIM8_TRGO2 (10 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 266 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_EXTI2

#define ADC345_CFGR1_EXTSEL_EXTI2 ADC_CFGR1_EXTSEL_VAL(5)

Definition at line 110 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG1

#define ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG1 ADC_CFGR1_EXTSEL_VAL(21)

Definition at line 126 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG10

#define ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG10 ADC_CFGR1_EXTSEL_VAL(28)

Definition at line 133 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG2

#define ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG2 ADC_CFGR1_EXTSEL_VAL(19)

Definition at line 124 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG3

#define ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG3 ADC_CFGR1_EXTSEL_VAL(22)

Definition at line 127 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG4

#define ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG4 ADC_CFGR1_EXTSEL_VAL(20)

Definition at line 125 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG5

#define ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG5 ADC_CFGR1_EXTSEL_VAL(23)

Definition at line 128 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG6

#define ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG6 ADC_CFGR1_EXTSEL_VAL(24)

Definition at line 129 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG7

#define ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG7 ADC_CFGR1_EXTSEL_VAL(25)

Definition at line 130 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG8

#define ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG8 ADC_CFGR1_EXTSEL_VAL(26)

Definition at line 131 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG9

#define ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG9 ADC_CFGR1_EXTSEL_VAL(27)

Definition at line 132 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_LPTIMOUT

#define ADC345_CFGR1_EXTSEL_LPTIMOUT ADC_CFGR1_EXTSEL_VAL(29)

Definition at line 134 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_TIM15_TRGO

#define ADC345_CFGR1_EXTSEL_TIM15_TRGO ADC_CFGR1_EXTSEL_VAL(14)

Definition at line 119 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_TIM1_CC3

#define ADC345_CFGR1_EXTSEL_TIM1_CC3 ADC_CFGR1_EXTSEL_VAL(2)

Definition at line 107 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_TIM1_TRGO

#define ADC345_CFGR1_EXTSEL_TIM1_TRGO ADC_CFGR1_EXTSEL_VAL(9)

Definition at line 114 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_TIM1_TRGO2

#define ADC345_CFGR1_EXTSEL_TIM1_TRGO2 ADC_CFGR1_EXTSEL_VAL(10)

Definition at line 115 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_TIM20_CC1

#define ADC345_CFGR1_EXTSEL_TIM20_CC1 ADC_CFGR1_EXTSEL_VAL(18)

Definition at line 123 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_TIM20_TRGO

#define ADC345_CFGR1_EXTSEL_TIM20_TRGO ADC_CFGR1_EXTSEL_VAL(16)

Definition at line 121 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_TIM20_TRGO2

#define ADC345_CFGR1_EXTSEL_TIM20_TRGO2 ADC_CFGR1_EXTSEL_VAL(17)

Definition at line 122 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_TIM2_CC1

#define ADC345_CFGR1_EXTSEL_TIM2_CC1 ADC_CFGR1_EXTSEL_VAL(15)

Definition at line 120 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_TIM2_CC3

#define ADC345_CFGR1_EXTSEL_TIM2_CC3 ADC_CFGR1_EXTSEL_VAL(1)

Definition at line 106 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_TIM2_TRGO

#define ADC345_CFGR1_EXTSEL_TIM2_TRGO ADC_CFGR1_EXTSEL_VAL(11)

Definition at line 116 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_TIM3_CC1

#define ADC345_CFGR1_EXTSEL_TIM3_CC1 ADC_CFGR1_EXTSEL_VAL(0)

Definition at line 105 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_TIM3_TRGO

#define ADC345_CFGR1_EXTSEL_TIM3_TRGO ADC_CFGR1_EXTSEL_VAL(4)

Definition at line 109 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_TIM4_CC1

#define ADC345_CFGR1_EXTSEL_TIM4_CC1 ADC_CFGR1_EXTSEL_VAL(6)

Definition at line 111 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_TIM4_TRGO

#define ADC345_CFGR1_EXTSEL_TIM4_TRGO ADC_CFGR1_EXTSEL_VAL(12)

Definition at line 117 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_TIM6_TRGO

#define ADC345_CFGR1_EXTSEL_TIM6_TRGO ADC_CFGR1_EXTSEL_VAL(13)

Definition at line 118 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_TIM7_TRGO

#define ADC345_CFGR1_EXTSEL_TIM7_TRGO ADC_CFGR1_EXTSEL_VAL(30)

Definition at line 135 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_TIM8_CC1

#define ADC345_CFGR1_EXTSEL_TIM8_CC1 ADC_CFGR1_EXTSEL_VAL(3)

Definition at line 108 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_TIM8_TRGO

#define ADC345_CFGR1_EXTSEL_TIM8_TRGO ADC_CFGR1_EXTSEL_VAL(7)

Definition at line 112 of file g4/adc.h.

◆ ADC345_CFGR1_EXTSEL_TIM8_TRGO2

#define ADC345_CFGR1_EXTSEL_TIM8_TRGO2 ADC_CFGR1_EXTSEL_VAL(8)

Definition at line 113 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_EXTI3

#define ADC345_JSQR_JEXTSEL_EXTI3 (13 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 300 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG1

#define ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG1 (27 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 314 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG10

#define ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG10 (26 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 313 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG2

#define ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG2 (19 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 306 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG3

#define ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG3 (28 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 315 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG4

#define ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG4 (20 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 307 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG5

#define ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG5 (21 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 308 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG6

#define ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG6 (22 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 309 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG7

#define ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG7 (23 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 310 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG8

#define ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG8 (24 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 311 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG9

#define ADC345_JSQR_JEXTSEL_HRTIM_ADC_TRG9 (25 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 312 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_LPTIMOUT

#define ADC345_JSQR_JEXTSEL_LPTIMOUT (29 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 316 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_TIM15_TRGO

#define ADC345_JSQR_JEXTSEL_TIM15_TRGO (15 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 302 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_TIM1_CC3

#define ADC345_JSQR_JEXTSEL_TIM1_CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 298 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_TIM1_CC4

#define ADC345_JSQR_JEXTSEL_TIM1_CC4 (1 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 288 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_TIM1_TRGO

#define ADC345_JSQR_JEXTSEL_TIM1_TRGO (0 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 287 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_TIM1_TRGO2

#define ADC345_JSQR_JEXTSEL_TIM1_TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 295 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_TIM20_CC2

#define ADC345_JSQR_JEXTSEL_TIM20_CC2 (18 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 305 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_TIM20_TRGO

#define ADC345_JSQR_JEXTSEL_TIM20_TRGO (16 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 303 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_TIM20_TRGO2

#define ADC345_JSQR_JEXTSEL_TIM20_TRGO2 (17 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 304 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_TIM2_TRGO

#define ADC345_JSQR_JEXTSEL_TIM2_TRGO (2 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 289 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_TIM3_TRGO

#define ADC345_JSQR_JEXTSEL_TIM3_TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 299 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_TIM4_CC3

#define ADC345_JSQR_JEXTSEL_TIM4_CC3 (4 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 291 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_TIM4_CC4

#define ADC345_JSQR_JEXTSEL_TIM4_CC4 (6 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 293 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_TIM4_TRGO

#define ADC345_JSQR_JEXTSEL_TIM4_TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 292 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_TIM6_TRGO

#define ADC345_JSQR_JEXTSEL_TIM6_TRGO (14 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 301 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_TIM7_TRGO

#define ADC345_JSQR_JEXTSEL_TIM7_TRGO (30 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 317 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_TIM8_CC2

#define ADC345_JSQR_JEXTSEL_TIM8_CC2 (3 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 290 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_TIM8_CC4

#define ADC345_JSQR_JEXTSEL_TIM8_CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 294 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_TIM8_TRGO

#define ADC345_JSQR_JEXTSEL_TIM8_TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 296 of file g4/adc.h.

◆ ADC345_JSQR_JEXTSEL_TIM8_TRGO2

#define ADC345_JSQR_JEXTSEL_TIM8_TRGO2 (10 << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 297 of file g4/adc.h.

◆ ADC_CCR_DUAL_MASK

#define ADC_CCR_DUAL_MASK (0x1f)

Definition at line 542 of file g4/adc.h.

◆ ADC_CCR_DUAL_SHIFT

#define ADC_CCR_DUAL_SHIFT 0

Definition at line 543 of file g4/adc.h.

◆ ADC_CFGR1_ALIGN

#define ADC_CFGR1_ALIGN (1 << 15)

ALIGN: Data alignment.

Definition at line 65 of file g4/adc.h.

◆ ADC_CFGR1_DISCNUM_MASK

#define ADC_CFGR1_DISCNUM_MASK (0x7 << ADC_CFGR1_DISCNUM_SHIFT)

Definition at line 143 of file adc_common_v2_multi.h.

◆ ADC_CFGR1_DISCNUM_SHIFT

#define ADC_CFGR1_DISCNUM_SHIFT 17

Definition at line 142 of file adc_common_v2_multi.h.

◆ ADC_CFGR1_DISCNUM_VAL

#define ADC_CFGR1_DISCNUM_VAL ( x ) (((x) - 1) << ADC_CFGR1_DISCNUM_SHIFT)

Definition at line 144 of file adc_common_v2_multi.h.

◆ ADC_CFGR1_EXTSEL_MASK

#define ADC_CFGR1_EXTSEL_MASK (0x1f << ADC_CFGR1_EXTSEL_SHIFT)

Definition at line 69 of file g4/adc.h.

◆ ADC_CFGR1_EXTSEL_SHIFT

#define ADC_CFGR1_EXTSEL_SHIFT 5

EXTSEL[4:0]: External trigger selection for regular group.

Definition at line 68 of file g4/adc.h.

◆ ADC_CFGR1_EXTSEL_VAL

#define ADC_CFGR1_EXTSEL_VAL ( x ) ((x) << ADC_CFGR1_EXTSEL_SHIFT)

Definition at line 70 of file g4/adc.h.

◆ ADC_CFGR1_JAUTO

#define ADC_CFGR1_JAUTO (1 << 25)

Definition at line 130 of file adc_common_v2_multi.h.

◆ ADC_CFGR1_JAWD1EN

#define ADC_CFGR1_JAWD1EN (1 << 24)

Definition at line 133 of file adc_common_v2_multi.h.

◆ ADC_CFGR1_JDISCEN

#define ADC_CFGR1_JDISCEN (1 << 20)

Definition at line 139 of file adc_common_v2_multi.h.

◆ ADC_CFGR1_JQM

#define ADC_CFGR1_JQM (1 << 21)

Definition at line 136 of file adc_common_v2_multi.h.

◆ ADC_CFGR2_BULB

#define ADC_CFGR2_BULB (1 << 26)

BULB: Bulb sampling mode.

Definition at line 177 of file g4/adc.h.

◆ ADC_CFGR2_GCOMP

#define ADC_CFGR2_GCOMP (1 << 16)

GCOMP: Gain compensation mode.

Definition at line 171 of file g4/adc.h.

◆ ADC_CFGR2_JOVSE

#define ADC_CFGR2_JOVSE (1 << 1)

JOVSE: Injected Oversampling Enable.

Definition at line 143 of file g4/adc.h.

◆ ADC_CFGR2_OVSR_128x

#define ADC_CFGR2_OVSR_128x ADC_CFGR2_OVSR_VAL(6)

Definition at line 156 of file g4/adc.h.

◆ ADC_CFGR2_OVSR_16x

#define ADC_CFGR2_OVSR_16x ADC_CFGR2_OVSR_VAL(3)

Definition at line 153 of file g4/adc.h.

◆ ADC_CFGR2_OVSR_256x

#define ADC_CFGR2_OVSR_256x ADC_CFGR2_OVSR_VAL(7)

Definition at line 157 of file g4/adc.h.

◆ ADC_CFGR2_OVSR_2x

#define ADC_CFGR2_OVSR_2x ADC_CFGR2_OVSR_VAL(0)

Definition at line 150 of file g4/adc.h.

◆ ADC_CFGR2_OVSR_32x

#define ADC_CFGR2_OVSR_32x ADC_CFGR2_OVSR_VAL(4)

Definition at line 154 of file g4/adc.h.

◆ ADC_CFGR2_OVSR_4x

#define ADC_CFGR2_OVSR_4x ADC_CFGR2_OVSR_VAL(1)

Definition at line 151 of file g4/adc.h.

◆ ADC_CFGR2_OVSR_64x

#define ADC_CFGR2_OVSR_64x ADC_CFGR2_OVSR_VAL(5)

Definition at line 155 of file g4/adc.h.

◆ ADC_CFGR2_OVSR_8x

#define ADC_CFGR2_OVSR_8x ADC_CFGR2_OVSR_VAL(2)

Definition at line 152 of file g4/adc.h.

◆ ADC_CFGR2_OVSR_MASK

#define ADC_CFGR2_OVSR_MASK (0x7 << ADC_CFGR2_OVSR_SHIFT)

Definition at line 147 of file g4/adc.h.

◆ ADC_CFGR2_OVSR_SHIFT

#define ADC_CFGR2_OVSR_SHIFT 2

OVSR[2:0]: Oversampling ratio.

Definition at line 146 of file g4/adc.h.

◆ ADC_CFGR2_OVSR_VAL

#define ADC_CFGR2_OVSR_VAL ( x ) ((x) << ADC_CFGR2_OVSR_SHIFT)

Definition at line 148 of file g4/adc.h.

◆ ADC_CFGR2_OVSS_MASK

#define ADC_CFGR2_OVSS_MASK (0xf << ADC_CFGR2_OVSS_SHIFT)

Definition at line 161 of file g4/adc.h.

◆ ADC_CFGR2_OVSS_SHIFT

#define ADC_CFGR2_OVSS_SHIFT 5

OVSS[3:0]: Oversampling shift.

Definition at line 160 of file g4/adc.h.

◆ ADC_CFGR2_OVSS_VAL

#define ADC_CFGR2_OVSS_VAL ( x ) ((x) << ADC_CFGR2_OVSS_SHIFT)

Definition at line 162 of file g4/adc.h.

◆ ADC_CFGR2_ROVSE

#define ADC_CFGR2_ROVSE (1 << 0)

ROVSE: Regular Oversampling Enable.

Definition at line 140 of file g4/adc.h.

◆ ADC_CFGR2_ROVSM

#define ADC_CFGR2_ROVSM (1 << 10)

ROVSM: Regular Oversampling mode.

Definition at line 168 of file g4/adc.h.

◆ ADC_CFGR2_SMPTRIG

#define ADC_CFGR2_SMPTRIG (1 << 27)

SMPTRIG: Sampling time control trigger mode.

Definition at line 180 of file g4/adc.h.

◆ ADC_CFGR2_SWTRIG

#define ADC_CFGR2_SWTRIG (1 << 25)

SWTRIG: Software trigger bit for sampling time control trigger mode.

Definition at line 174 of file g4/adc.h.

◆ ADC_CFGR2_TROVS

#define ADC_CFGR2_TROVS (1 << 9)

TROVS: Triggered Regular Oversampling.

Definition at line 165 of file g4/adc.h.

◆ ADC_CHANNEL_COUNT

#define ADC_CHANNEL_COUNT 19

Definition at line 561 of file g4/adc.h.

◆ ADC_CHANNEL_IS_FAST

#define ADC_CHANNEL_IS_FAST ( x ) ((x) <= 5)

Definition at line 562 of file g4/adc.h.

◆ ADC_CR_ADCALDIF

#define ADC_CR_ADCALDIF (1 << 30)

Definition at line 121 of file adc_common_v2_multi.h.

◆ ADC_CR_ADVREGEN

#define ADC_CR_ADVREGEN (1 << 28)

ADVREGEN: ADC voltage regulator enable bit.

Definition at line 60 of file g4/adc.h.

◆ ADC_CR_DEEPPWD

#define ADC_CR_DEEPPWD (1 << 29)

Definition at line 57 of file g4/adc.h.

◆ ADC_CR_JADSTART

#define ADC_CR_JADSTART (1 << 3)

Definition at line 125 of file adc_common_v2_multi.h.

◆ ADC_CR_JADSTP

#define ADC_CR_JADSTP (1 << 5)

Definition at line 123 of file adc_common_v2_multi.h.

◆ ADC_CSR_ADRDY_MST

#define ADC_CSR_ADRDY_MST (1 << 0)

Definition at line 459 of file g4/adc.h.

◆ ADC_CSR_ADRDY_SLV

#define ADC_CSR_ADRDY_SLV (1 << 16)

Definition at line 426 of file g4/adc.h.

◆ ADC_CSR_AWD1_MST

#define ADC_CSR_AWD1_MST (1 << 7)

Definition at line 438 of file g4/adc.h.

◆ ADC_CSR_AWD1_SLV

#define ADC_CSR_AWD1_SLV (1 << 23)

Definition at line 405 of file g4/adc.h.

◆ ADC_CSR_AWD2_MST

#define ADC_CSR_AWD2_MST (1 << 8)

Definition at line 435 of file g4/adc.h.

◆ ADC_CSR_AWD2_SLV

#define ADC_CSR_AWD2_SLV (1 << 24)

Definition at line 402 of file g4/adc.h.

◆ ADC_CSR_AWD3_MST

#define ADC_CSR_AWD3_MST (1 << 9)

Definition at line 432 of file g4/adc.h.

◆ ADC_CSR_AWD3_SLV

#define ADC_CSR_AWD3_SLV (1 << 25)

Definition at line 399 of file g4/adc.h.

◆ ADC_CSR_EOC_MST

#define ADC_CSR_EOC_MST (1 << 2)

Definition at line 453 of file g4/adc.h.

◆ ADC_CSR_EOC_SLV

#define ADC_CSR_EOC_SLV (1 << 18)

Definition at line 420 of file g4/adc.h.

◆ ADC_CSR_EOS_MST

#define ADC_CSR_EOS_MST (1 << 3)

Definition at line 450 of file g4/adc.h.

◆ ADC_CSR_EOS_SLV

#define ADC_CSR_EOS_SLV (1 << 19)

Definition at line 417 of file g4/adc.h.

◆ ADC_CSR_EOSMP_MST

#define ADC_CSR_EOSMP_MST (1 << 1)

Definition at line 456 of file g4/adc.h.

◆ ADC_CSR_EOSMP_SLV

#define ADC_CSR_EOSMP_SLV (1 << 17)

Definition at line 423 of file g4/adc.h.

◆ ADC_CSR_JEOC_MST

#define ADC_CSR_JEOC_MST (1 << 5)

Definition at line 444 of file g4/adc.h.

◆ ADC_CSR_JEOC_SLV

#define ADC_CSR_JEOC_SLV (1 << 21)

Definition at line 411 of file g4/adc.h.

◆ ADC_CSR_JEOS_MST

#define ADC_CSR_JEOS_MST (1 << 6)

Definition at line 441 of file g4/adc.h.

◆ ADC_CSR_JEOS_SLV

#define ADC_CSR_JEOS_SLV (1 << 22)

Definition at line 408 of file g4/adc.h.

◆ ADC_CSR_JQOVF_MST

#define ADC_CSR_JQOVF_MST (1 << 10)

Definition at line 429 of file g4/adc.h.

◆ ADC_CSR_JQOVF_SLV

#define ADC_CSR_JQOVF_SLV (1 << 26)

Definition at line 396 of file g4/adc.h.

◆ ADC_CSR_OVR_MST

#define ADC_CSR_OVR_MST (1 << 4)

Definition at line 447 of file g4/adc.h.

◆ ADC_CSR_OVR_SLV

#define ADC_CSR_OVR_SLV (1 << 20)

Definition at line 414 of file g4/adc.h.

◆ ADC_GCOMP

#define ADC_GCOMP ( adc ) MMIO32((adc) + 0xC0)

ADC_GCOMP Gain compensation Register.

Definition at line 52 of file g4/adc.h.

◆ ADC_IER_AWD2IE

#define ADC_IER_AWD2IE (1 << 8)

Definition at line 112 of file adc_common_v2_multi.h.

◆ ADC_IER_AWD3IE

#define ADC_IER_AWD3IE (1 << 9)

Definition at line 110 of file adc_common_v2_multi.h.

◆ ADC_IER_JEOCIE

#define ADC_IER_JEOCIE (1 << 5)

Definition at line 116 of file adc_common_v2_multi.h.

◆ ADC_IER_JEOSIE

#define ADC_IER_JEOSIE (1 << 6)

Definition at line 114 of file adc_common_v2_multi.h.

◆ ADC_IER_JQOVFIE

#define ADC_IER_JQOVFIE (1 << 10)

Definition at line 108 of file adc_common_v2_multi.h.

◆ ADC_ISR_AWD2

#define ADC_ISR_AWD2 (1 << 8)

Definition at line 99 of file adc_common_v2_multi.h.

◆ ADC_ISR_AWD3

#define ADC_ISR_AWD3 (1 << 9)

Definition at line 97 of file adc_common_v2_multi.h.

◆ ADC_ISR_JEOC

#define ADC_ISR_JEOC (1 << 5)

Definition at line 103 of file adc_common_v2_multi.h.

◆ ADC_ISR_JEOS

#define ADC_ISR_JEOS (1 << 6)

Definition at line 101 of file adc_common_v2_multi.h.

◆ ADC_ISR_JQOVF

#define ADC_ISR_JQOVF (1 << 10)

Definition at line 95 of file adc_common_v2_multi.h.

◆ ADC_JSQR_JEXTEN_BOTH_EDGES

#define ADC_JSQR_JEXTEN_BOTH_EDGES (0x3 << 7)

Definition at line 249 of file g4/adc.h.

◆ ADC_JSQR_JEXTEN_DISABLED

#define ADC_JSQR_JEXTEN_DISABLED (0x0 << 7)

Definition at line 246 of file g4/adc.h.

◆ ADC_JSQR_JEXTEN_FALLING_EDGE

#define ADC_JSQR_JEXTEN_FALLING_EDGE (0x2 << 7)

Definition at line 248 of file g4/adc.h.

◆ ADC_JSQR_JEXTEN_MASK

#define ADC_JSQR_JEXTEN_MASK (0x3 << 7)

Definition at line 251 of file g4/adc.h.

◆ ADC_JSQR_JEXTEN_RISING_EDGE

#define ADC_JSQR_JEXTEN_RISING_EDGE (0x1 << 7)

Definition at line 247 of file g4/adc.h.

◆ ADC_JSQR_JEXTSEL_MASK

#define ADC_JSQR_JEXTSEL_MASK (0x1F << ADC_JSQR_JEXTSEL_SHIFT)

Definition at line 319 of file g4/adc.h.

◆ ADC_JSQR_JEXTSEL_SHIFT

#define ADC_JSQR_JEXTSEL_SHIFT 2

Definition at line 254 of file g4/adc.h.

◆ ADC_JSQR_JL_1_CONVERSION

#define ADC_JSQR_JL_1_CONVERSION (0x0 << 0)

Definition at line 322 of file g4/adc.h.

◆ ADC_JSQR_JL_2_CONVERSIONS

#define ADC_JSQR_JL_2_CONVERSIONS (0x1 << 0)

Definition at line 323 of file g4/adc.h.

◆ ADC_JSQR_JL_3_CONVERSIONS

#define ADC_JSQR_JL_3_CONVERSIONS (0x2 << 0)

Definition at line 324 of file g4/adc.h.

◆ ADC_JSQR_JL_4_CONVERSIONS

#define ADC_JSQR_JL_4_CONVERSIONS (0x3 << 0)

Definition at line 325 of file g4/adc.h.

◆ ADC_JSQR_JL_LSB

#define ADC_JSQR_JL_LSB 0

Definition at line 224 of file g4/adc.h.

◆ ADC_JSQR_JL_SHIFT

#define ADC_JSQR_JL_SHIFT 0

Definition at line 225 of file g4/adc.h.

◆ ADC_JSQR_JL_VAL

#define ADC_JSQR_JL_VAL ( val ) (((val) - 1) << ADC_JSQR_JL_SHIFT)

Definition at line 232 of file g4/adc.h.

◆ ADC_JSQR_JSQ1_LSB

#define ADC_JSQR_JSQ1_LSB 9

Definition at line 229 of file g4/adc.h.

◆ ADC_JSQR_JSQ2_LSB

#define ADC_JSQR_JSQ2_LSB 15

Definition at line 228 of file g4/adc.h.

◆ ADC_JSQR_JSQ3_LSB

#define ADC_JSQR_JSQ3_LSB 21

Definition at line 227 of file g4/adc.h.

◆ ADC_JSQR_JSQ4_LSB

#define ADC_JSQR_JSQ4_LSB 27

Definition at line 226 of file g4/adc.h.

◆ ADC_JSQR_JSQ_VAL

#define ADC_JSQR_JSQ_VAL	(	n,
		val
	)	((val) << (((n) - 1) * 6 + 8))

Definition at line 231 of file g4/adc.h.

◆ ADC_OFR1_OFFSET1_EN

#define ADC_OFR1_OFFSET1_EN (1 << 31)

Definition at line 330 of file g4/adc.h.

◆ ADC_OFR2_OFFSET2_EN

#define ADC_OFR2_OFFSET2_EN (1 << 31)

Definition at line 343 of file g4/adc.h.

◆ ADC_OFR3_OFFSET3_EN

#define ADC_OFR3_OFFSET3_EN (1 << 31)

Definition at line 356 of file g4/adc.h.

◆ ADC_OFR4_OFFSET4_EN

#define ADC_OFR4_OFFSET4_EN (1 << 31)

Definition at line 369 of file g4/adc.h.

◆ ADC_SQR1_L_MASK

#define ADC_SQR1_L_MASK 0xf

Definition at line 149 of file adc_common_v2_multi.h.

◆ ADC_SQR1_L_SHIFT

#define ADC_SQR1_L_SHIFT 0

Definition at line 148 of file adc_common_v2_multi.h.

◆ ADC_SQR1_SQ1_SHIFT

#define ADC_SQR1_SQ1_SHIFT 6

Definition at line 151 of file adc_common_v2_multi.h.

◆ ADC_SQR1_SQ2_SHIFT

#define ADC_SQR1_SQ2_SHIFT 12

Definition at line 152 of file adc_common_v2_multi.h.

◆ ADC_SQR1_SQ3_SHIFT

#define ADC_SQR1_SQ3_SHIFT 18

Definition at line 153 of file adc_common_v2_multi.h.

◆ ADC_SQR1_SQ4_SHIFT

#define ADC_SQR1_SQ4_SHIFT 24

Definition at line 154 of file adc_common_v2_multi.h.

◆ ADC_SQR2_SQ5_SHIFT

#define ADC_SQR2_SQ5_SHIFT 0

Definition at line 155 of file adc_common_v2_multi.h.

◆ ADC_SQR2_SQ6_SHIFT

#define ADC_SQR2_SQ6_SHIFT 6

Definition at line 156 of file adc_common_v2_multi.h.

◆ ADC_SQR2_SQ7_SHIFT

#define ADC_SQR2_SQ7_SHIFT 12

Definition at line 157 of file adc_common_v2_multi.h.

◆ ADC_SQR2_SQ8_SHIFT

#define ADC_SQR2_SQ8_SHIFT 18

Definition at line 158 of file adc_common_v2_multi.h.

◆ ADC_SQR2_SQ9_SHIFT

#define ADC_SQR2_SQ9_SHIFT 24

Definition at line 159 of file adc_common_v2_multi.h.

◆ ADC_SQR3_SQ10_SHIFT

#define ADC_SQR3_SQ10_SHIFT 0

Definition at line 160 of file adc_common_v2_multi.h.

◆ ADC_SQR3_SQ11_SHIFT

#define ADC_SQR3_SQ11_SHIFT 6

Definition at line 161 of file adc_common_v2_multi.h.

◆ ADC_SQR3_SQ12_SHIFT

#define ADC_SQR3_SQ12_SHIFT 12

Definition at line 162 of file adc_common_v2_multi.h.

◆ ADC_SQR3_SQ13_SHIFT

#define ADC_SQR3_SQ13_SHIFT 18

Definition at line 163 of file adc_common_v2_multi.h.

◆ ADC_SQR3_SQ14_SHIFT

#define ADC_SQR3_SQ14_SHIFT 24

Definition at line 164 of file adc_common_v2_multi.h.

◆ ADC_SQR4_SQ15_SHIFT

#define ADC_SQR4_SQ15_SHIFT 0

Definition at line 165 of file adc_common_v2_multi.h.

◆ ADC_SQR4_SQ16_SHIFT

#define ADC_SQR4_SQ16_SHIFT 6

Definition at line 166 of file adc_common_v2_multi.h.

◆ ADC_SQRx_SQx_MASK

#define ADC_SQRx_SQx_MASK 0x1f

Definition at line 150 of file adc_common_v2_multi.h.

Function Documentation

◆ adc_awd()

bool adc_awd ( uint32_t adc )

ADC Read the Analog Watchdog Flag.

This flag is set when the converted voltage crosses the high or low thresholds.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Returns: bool. AWD flag.

Definition at line 658 of file adc.c.

References ADC_ISR, ADC_ISR_AWD1, ADC_ISR_AWD2, and ADC_ISR_AWD3.

◆ adc_calibrate()

void adc_calibrate ( uint32_t adc )

Start ADC calibration and wait for it to finish.

Parameters

adc	ADC Block register address base ADC register base addresses

Definition at line 175 of file adc_common_v2.c.

References adc_calibrate_async(), and adc_is_calibrating().

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◆ adc_calibrate_async()

void adc_calibrate_async ( uint32_t adc )

Start the ADC calibration and immediately return.

See also: adc_calibrate; adc_is_calibrating

Parameters

adc	ADC Block register address base ADC register base addresses

Definition at line 156 of file adc_common_v2.c.

References ADC_CR, and ADC_CR_ADCAL.

Referenced by adc_calibrate().

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◆ adc_clear_overrun_flag()

void adc_clear_overrun_flag ( uint32_t adc )

ADC Clear Overrun Flags.

The overrun flag is cleared. Note that if an overrun occurs, DMA is terminated. The flag must be cleared and the DMA stream and ADC reinitialised to resume conversions (see the reference manual).

Parameters

[in] adc Unsigned int32. ADC base address (ADC register base addresses)

Definition at line 299 of file adc_common_v2.c.

References ADC_ISR, and ADC_ISR_OVR.

◆ adc_disable_all_awd_interrupt()

void adc_disable_all_awd_interrupt ( uint32_t adc )

ADC Disable Analog Watchdog Interrupt.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 306 of file adc.c.

References ADC_IER.

◆ adc_disable_analog_watchdog_injected()

void adc_disable_analog_watchdog_injected ( uint32_t adc )

ADC Disable Analog Watchdog for Injected Conversions.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 88 of file adc.c.

References ADC_CFGR1.

◆ adc_disable_analog_watchdog_regular()

void adc_disable_analog_watchdog_regular ( uint32_t adc )

ADC Enable Analog Watchdog for Regular Conversions.

The analog watchdog allows the monitoring of an analog signal between two threshold levels. The thresholds must be preset. Comparison is done before data alignment takes place, so the thresholds are left-aligned.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 60 of file adc.c.

References ADC_CFGR1.

◆ adc_disable_automatic_injected_group_conversion()

void adc_disable_automatic_injected_group_conversion ( uint32_t adc )

ADC Disable Automatic Injected Conversions.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 180 of file adc.c.

References ADC_CFGR1.

◆ adc_disable_deeppwd()

void adc_disable_deeppwd ( uint32_t adc )

void adc_disable_external_trigger_injected ( uint32_t adc )

ADC Disable an External Trigger for Injected Channels.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 641 of file adc.c.

References ADC_JSQR.

Referenced by adc_enable_automatic_injected_group_conversion().

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◆ adc_disable_external_trigger_regular()

void adc_disable_external_trigger_regular ( uint32_t adc )

ADC Disable an External Trigger for Regular Channels.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 605 of file adc.c.

References ADC_CFGR1.

◆ adc_disable_overrun_interrupt()

void adc_disable_overrun_interrupt ( uint32_t adc )

ADC Disable the Overrun Interrupt.

Parameters

[in] adc Unsigned int32. ADC base address (ADC register base addresses)

Definition at line 272 of file adc_common_v2.c.

References ADC_IER.

◆ adc_disable_regulator()

void adc_disable_regulator ( uint32_t adc )

Disable the ADC Voltage regulator You can disable the adc vreg when not in use to save power.

Parameters

[in] adc ADC block register address base

See also: adc_enable_regulator

Definition at line 712 of file adc.c.

References ADC_CR.

◆ adc_disable_temperature_sensor()

void adc_disable_temperature_sensor ( void )

Disable the temperature sensor (only)

See also: adc_enable_temperature_sensor

Definition at line 351 of file adc_common_v2.c.

References ADC1, and ADC_CCR.

◆ adc_disable_vrefint()

void adc_disable_vrefint ( void )

Disable the internal voltage reference (only)

See also: adc_enable_vrefint

Definition at line 372 of file adc_common_v2.c.

References ADC1, and ADC_CCR.

◆ adc_enable_all_awd_interrupt()

void adc_enable_all_awd_interrupt ( uint32_t adc )

ADC Enable Analog Watchdog Interrupt.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 292 of file adc.c.

References ADC_IER, ADC_IER_AWD1IE, ADC_IER_AWD2IE, and ADC_IER_AWD3IE.

◆ adc_enable_analog_watchdog_injected()

void adc_enable_analog_watchdog_injected ( uint32_t adc )

ADC Enable Analog Watchdog for Injected Conversions.

The analog watchdog allows the monitoring of an analog signal between two threshold levels. The thresholds must be preset. Comparison is done before data alignment takes place, so the thresholds are left-aligned.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 76 of file adc.c.

References ADC_CFGR1, and ADC_CFGR1_JAWD1EN.

◆ adc_enable_analog_watchdog_on_all_channels()

void adc_enable_analog_watchdog_on_all_channels ( uint32_t adc )

ADC Enable Analog Watchdog for All Regular and/or Injected Channels.

The analog watchdog allows the monitoring of an analog signal between two threshold levels. The thresholds must be preset. Comparison is done before data alignment takes place, so the thresholds are left-aligned.

Note: The analog watchdog must be enabled for either or both of the regular or injected channels. If neither are enabled, the analog watchdog feature will be disabled.

adc_enable_analog_watchdog_injected, adc_enable_analog_watchdog_regular.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 202 of file adc.c.

References ADC_CFGR1.

◆ adc_enable_analog_watchdog_on_selected_channel()

void adc_enable_analog_watchdog_on_selected_channel	(	uint32_t	adc,
		uint8_t	channel
	)

ADC Enable Analog Watchdog for a Selected Channel.

The analog watchdog allows the monitoring of an analog signal between two threshold levels. The thresholds must be preset. Comparison is done before data alignment takes place, so the thresholds are left-aligned.

Note: The analog watchdog must be enabled for either or both of the regular or injected channels. If neither are enabled, the analog watchdog feature will be disabled. If both are enabled, the same channel number is monitored adc_enable_analog_watchdog_injected, adc_enable_analog_watchdog_regular.

Parameters

[in]	adc	Unsigned int32. ADC block register address base ADC register base addresses
[in]	channel	Unsigned int8. ADC channel numbe adc_watchdog_channel

Definition at line 226 of file adc.c.

References ADC_CFGR1, ADC_CFGR1_AWD1CH_VAL, ADC_CFGR1_AWD1EN, and ADC_CFGR1_AWD1SGL.

◆ adc_enable_analog_watchdog_regular()

void adc_enable_analog_watchdog_regular ( uint32_t adc )

ADC Enable Analog Watchdog for Regular Conversions.

The analog watchdog allows the monitoring of an analog signal between two threshold levels. The thresholds must be preset. Comparison is done before data alignment takes place, so the thresholds are left-aligned.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 45 of file adc.c.

References ADC_CFGR1, and ADC_CFGR1_AWD1EN.

◆ adc_enable_automatic_injected_group_conversion()

void adc_enable_automatic_injected_group_conversion ( uint32_t adc )

ADC Enable Automatic Injected Conversions.

The ADC converts a defined injected group of channels immediately after the regular channels have been converted. The external trigger on the injected channels is disabled as required.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 167 of file adc.c.

References ADC_CFGR1, ADC_CFGR1_JAUTO, and adc_disable_external_trigger_injected().

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◆ adc_enable_deeppwd()

void adc_enable_deeppwd ( uint32_t adc )

ADC Enable Deep-Power-Down Mdoe.

Deep-power-down mode allows additional power saving by internally switching off to reduce leakage currents.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 674 of file adc.c.

References ADC_CR, and ADC_CR_DEEPPWD.

◆ adc_enable_delayed_conversion_mode()

void adc_enable_delayed_conversion_mode ( uint32_t adc )

Enable Delayed Conversion Mode.

Parameters

[in] adc ADC block register address base ADC register base addresses

Definition at line 416 of file adc_common_v2.c.

References ADC_CFGR1, and ADC_CFGR1_AUTDLY.

◆ adc_enable_discontinuous_mode_injected()

void adc_enable_discontinuous_mode_injected ( uint32_t adc )

ADC Enable Discontinuous Mode for Injected Conversions.

In this mode the ADC converts sequentially one channel of the defined group of injected channels, cycling back to the first channel in the group once the entire group has been converted.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 139 of file adc.c.

References ADC_CFGR1, and ADC_CFGR1_JDISCEN.

◆ adc_enable_discontinuous_mode_regular()

void adc_enable_discontinuous_mode_regular	(	uint32_t	adc,
		uint8_t	length
	)

ADC Enable Discontinuous Mode for Regular Conversions.

In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the defined regular channel group. The subgroup is defined by the number of consecutive channels to be converted. After a subgroup has been converted the next trigger will start conversion of the immediately following subgroup of the same length or until the whole group has all been converted. When the whole group has been converted, the next trigger will restart conversion of the subgroup at the beginning of the whole group.

Parameters

[in]	adc	ADC block register address base ADC register base addresses
[in]	length	Number of channels in the group adc_cr1_discnum

Definition at line 107 of file adc.c.

References ADC_CFGR1, ADC_CFGR1_DISCEN, and ADC_CFGR1_DISCNUM_SHIFT.

◆ adc_enable_dma()

void adc_enable_dma ( uint32_t adc )

ADC Enable DMA Transfers.

Parameters

[in] adc Unsigned int32. ADC base address (ADC register base addresses)

Definition at line 241 of file adc_common_v2.c.

References ADC_CFGR1, and ADC_CFGR1_DMAEN.

◆ adc_enable_dma_circular_mode()

void adc_enable_dma_circular_mode ( uint32_t adc )

Enable circular mode for DMA transfers.

For this to work it needs to be ebabled on the DMA side as well.

Parameters

[in] adc Unsigned int32. ADC base address (ADC register base addresses)

Definition at line 398 of file adc_common_v2.c.

References ADC_CFGR1, and ADC_CFGR1_DMACFG.

◆ adc_enable_eoc_interrupt()

void adc_enable_eoc_interrupt ( uint32_t adc )

ADC Enable Regular End-Of-Conversion Interrupt.

Parameters

[in] adc Unsigned int32. ADC base address (ADC register base addresses)

Definition at line 308 of file adc_common_v2.c.

References ADC_IER, and ADC_IER_EOCIE.

◆ adc_enable_eoc_interrupt_injected()

void adc_enable_eoc_interrupt_injected ( uint32_t adc )

ADC Enable Injected End-Of-Conversion Interrupt.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 243 of file adc.c.

References ADC_IER, and ADC_IER_JEOCIE.

◆ adc_enable_eos_interrupt()

void adc_enable_eos_interrupt ( uint32_t adc )

ADC Enable Regular End-Of-Sequence Interrupt.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 320 of file adc.c.

References ADC_IER, and ADC_IER_EOSIE.

◆ adc_enable_eos_interrupt_injected()

void adc_enable_eos_interrupt_injected ( uint32_t adc )

ADC Enable Injected End-Of-Sequence Interrupt.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 267 of file adc.c.

References ADC_IER, and ADC_IER_JEOSIE.

◆ adc_enable_external_trigger_injected()

void adc_enable_external_trigger_injected	(	uint32_t	adc,
		uint32_t	trigger,
		uint32_t	polarity
	)

ADC Enable an External Trigger for Injected Channels.

This enables an external trigger for set of defined injected channels, and sets the polarity of the trigger event: rising or falling edge or both.

Parameters

[in]	adc	Unsigned int32. ADC block register address base ADC register base addresses
[in]	trigger	Unsigned int8. Trigger identifier adc_trigger_injected
[in]	polarity	Unsigned int32. Trigger polarity adc_trigger_polarity_injected

Definition at line 624 of file adc.c.

References ADC_JSQR, ADC_JSQR_JEXTEN_MASK, and ADC_JSQR_JEXTSEL_MASK.

◆ adc_enable_external_trigger_regular()

void adc_enable_external_trigger_regular	(	uint32_t	adc,
		uint32_t	trigger,
		uint32_t	polarity
	)

ADC Enable an External Trigger for Regular Channels.

This enables an external trigger for set of defined regular channels, and sets the polarity of the trigger event: rising or falling edge or both. Note that if the trigger polarity is zero, triggering is disabled.

Parameters

[in]	adc	Unsigned int32. ADC block register address base ADC register base addresses
[in]	trigger	Unsigned int32. Trigger identifier adc_trigger_regular
[in]	polarity	Unsigned int32. Trigger polarity adc_trigger_polarity_regular

Definition at line 588 of file adc.c.

References ADC_CFGR1, ADC_CFGR1_EXTEN_MASK, and ADC_CFGR1_EXTSEL_MASK.

◆ adc_enable_overrun_interrupt()

void adc_enable_overrun_interrupt ( uint32_t adc )

ADC Enable the Overrun Interrupt.

The overrun interrupt is generated when data is not read from a result register before the next conversion is written. If DMA is enabled, all transfers are terminated and any conversion sequence is aborted.

Parameters

[in] adc Unsigned int32. ADC base address (ADC register base addresses)

Definition at line 263 of file adc_common_v2.c.

References ADC_IER, and ADC_IER_OVRIE.

◆ adc_enable_regulator()

void adc_enable_regulator ( uint32_t adc )

Enable the ADC Voltage regulator Before any use of the ADC, the ADC Voltage regulator must be enabled.

You must wait up to 10uSecs afterwards before trying anything else.

Parameters

[in] adc ADC block register address base

See also: adc_disable_regulator

Definition at line 701 of file adc.c.

References ADC_CR, and ADC_CR_ADVREGEN.

◆ adc_enable_temperature_sensor()

void adc_enable_temperature_sensor ( void )

Enable the temperature sensor (only) The channel this is available on is unfortunately not consistent, even though the bit used to enable it is.

See also: adc_disable_temperature_sensor

Definition at line 342 of file adc_common_v2.c.

References ADC1, ADC_CCR, and ADC_CCR_TSEN.

◆ adc_enable_vrefint()

void adc_enable_vrefint ( void )

Enable the internal voltage reference (only) The channel this is available on is unfortunately not consistent, even though the bit used to enable it is.

FIXME - on f3, you can actually have it on ADC34 as well!

See also: adc_disable_vrefint

Definition at line 363 of file adc_common_v2.c.

References ADC1, ADC_CCR, and ADC_CCR_VREFEN.

◆ adc_eoc()

bool adc_eoc ( uint32_t adc )

ADC Read the End-of-Conversion Flag.

This flag is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADCx_DR register.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Returns: bool. End of conversion flag.

Definition at line 49 of file adc_common_v2.c.

References ADC_ISR, and ADC_ISR_EOC.

◆ adc_eoc_injected()

bool adc_eoc_injected ( uint32_t adc )

ADC Read the End-of-Conversion Flag for Injected Conversion.

This flag is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADCx_JDRy register.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Returns: bool. End of conversion flag.

Definition at line 437 of file adc.c.

References ADC_ISR, and ADC_ISR_JEOC.

◆ adc_eos()

bool adc_eos ( uint32_t adc )

ADC Read the End-of-Sequence Flag for Regular Conversions.

This flag is set after all channels of an regular group have been converted.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Returns: bool. End of conversion flag.

Definition at line 63 of file adc_common_v2.c.

References ADC_ISR, and ADC_ISR_EOS.

◆ adc_eos_injected()

bool adc_eos_injected ( uint32_t adc )

ADC Read the End-of-Sequence Flag for Injected Conversions.

This flag is set after all channels of an injected group have been converted.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Returns: bool. End of conversion flag.

Definition at line 452 of file adc.c.

References ADC_ISR, and ADC_ISR_JEOS.

◆ adc_get_overrun_flag()

bool adc_get_overrun_flag ( uint32_t adc )

ADC Read the Overrun Flag.

The overrun flag is set when data is not read from a result register before the next conversion is written. If DMA is enabled, all transfers are terminated and any conversion sequence is aborted.

Parameters

[in] adc Unsigned int32. ADC base address (ADC register base addresses)

Definition at line 285 of file adc_common_v2.c.

References ADC_ISR, and ADC_ISR_OVR.

◆ adc_is_calibrating()

bool adc_is_calibrating ( uint32_t adc )

Is the ADC Calibrating?

Parameters

adc	ADC Block register address base ADC register base addresses

Returns: true if the adc is currently calibrating

Definition at line 166 of file adc_common_v2.c.

References ADC_CR, and ADC_CR_ADCAL.

Referenced by adc_calibrate().

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◆ adc_is_power_off()

bool adc_is_power_off ( uint32_t adc )

Is the ADC powered down?

See also: adc_power_off_async

Parameters

adc	ADC Block register address base ADC register base addresses

Definition at line 132 of file adc_common_v2.c.

References ADC_CR, and ADC_CR_ADEN.

Referenced by adc_power_off(), and adc_power_off_async().

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◆ adc_is_power_on()

bool adc_is_power_on ( uint32_t adc )

Is the ADC powered up and ready?

See also: adc_power_on_async

Parameters

adc	ADC Block register address base ADC register base addresses

Returns: true if adc is ready for use

Definition at line 84 of file adc_common_v2.c.

References ADC_ISR, and ADC_ISR_ADRDY.

Referenced by adc_power_on().

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◆ adc_power_off()

void adc_power_off ( uint32_t adc )

Turn off the ADC This will actually block if it needs to turn off a currently running conversion, as per ref man.

See also: adc_power_off_async

Parameters

adc	ADC Block register address base ADC register base addresses

Definition at line 144 of file adc_common_v2.c.

References adc_is_power_off(), and adc_power_off_async().

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◆ adc_power_off_async()

void adc_power_off_async ( uint32_t adc )

Turn off the ADC (async) This will actually block if it needs to turn off a currently running conversion, as per ref man.

(Handles injected on hardware that supports injected conversions.

See also: adc_wait_power_off

Parameters

adc	ADC Block register address base ADC register base addresses

Definition at line 108 of file adc_common_v2.c.

References ADC_CR, ADC_CR_ADDIS, ADC_CR_ADSTART, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_JADSTP, and adc_is_power_off().

Referenced by adc_power_off().

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◆ adc_power_on()

void adc_power_on ( uint32_t adc )

Turn on the ADC.

See also: adc_power_on_async

Parameters

adc	ADC Block register address base ADC register base addresses

Definition at line 94 of file adc_common_v2.c.

References adc_is_power_on(), and adc_power_on_async().

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◆ adc_power_on_async()

void adc_power_on_async ( uint32_t adc )

Turn on the ADC (async)

See also: adc_wait_power_on

Parameters

adc	ADC Block register address base ADC register base addresses

Definition at line 73 of file adc_common_v2.c.

References ADC_CR, and ADC_CR_ADEN.

Referenced by adc_power_on().

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◆ adc_read_injected()

uint32_t adc_read_injected	(	uint32_t	adc,
		uint8_t	reg
	)

ADC Read from an Injected Conversion Result Register.

The result read back from the selected injected result register (one of four) is 12 bits, right or left aligned within the first 16 bits. The result can have a negative value if the injected channel offset has been set

See also: adc_set_injected_offset.

Parameters

[in]	adc	Unsigned int32. ADC block register address base ADC register base addresses
[in]	reg	Unsigned int8. Register number (1 ... 4).

Returns: Unsigned int32 conversion result.

Definition at line 472 of file adc.c.

References ADC_JDR1, ADC_JDR2, ADC_JDR3, and ADC_JDR4.

◆ adc_read_regular()

uint32_t adc_read_regular ( uint32_t adc )

ADC Read from the Regular Conversion Result Register.

The result read back is 12 bits, right or left aligned within the first 16 bits.

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Returns: Unsigned int32 conversion result.

Definition at line 331 of file adc_common_v2.c.

References ADC_DR.

◆ adc_set_clk_prescale()

void adc_set_clk_prescale	(	uint32_t	adc,
		uint32_t	prescale
	)

ADC Set Clock Prescale.

The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8.

Parameters

	adc	peripheral of choice ADC register base addresses
[in]	prescale	Prescale value for ADC Clock ADC clock prescaler

Definition at line 545 of file adc.c.

References ADC_CCR, ADC_CCR_PRESC_MASK, and ADC_CCR_PRESC_SHIFT.

◆ adc_set_clk_source()

void adc_set_clk_source	(	uint32_t	adc,
		uint32_t	source
	)

ADC Set Clock Source.

The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8.

Parameters

	adc	peripheral of choice ADC register base addresses
[in]	source	Unsigned int32. Source value for ADC Clock adc_ccr_adcpre

Definition at line 531 of file adc.c.

References ADC_CCR.

◆ adc_set_continuous_conversion_mode()

void adc_set_continuous_conversion_mode ( uint32_t adc )

Enable Continuous Conversion Mode In this mode the ADC starts a new conversion of a single channel or a channel group immediately following completion of the previous channel group conversion.

Parameters

[in] adc ADC block register address base ADC register base addresses

Definition at line 189 of file adc_common_v2.c.

References ADC_CFGR1, and ADC_CFGR1_CONT.

◆ adc_set_injected_offset()

void adc_set_injected_offset	(	uint32_t	adc,
		uint8_t	reg,
		uint32_t	offset
	)

ADC Set the Injected Channel Data Offset.

This value is subtracted from the injected channel results after conversion is complete, and can result in negative results. A separate value can be specified for each injected data register.

Parameters

[in]	adc	Unsigned int32. ADC block register address base ADC register base addresses
[in]	reg	Unsigned int8. Register number (1 ... 4).
[in]	offset	Unsigned int32.

Definition at line 500 of file adc.c.

References ADC_OFR1, ADC_OFR1_OFFSET1_EN, ADC_OFR2, ADC_OFR2_OFFSET2_EN, ADC_OFR3, ADC_OFR3_OFFSET3_EN, ADC_OFR4, and ADC_OFR4_OFFSET4_EN.

◆ adc_set_injected_sequence()

void adc_set_injected_sequence	(	uint32_t	adc,
		uint8_t	length,
		uint8_t	channel[]
	)

ADC Set an Injected Channel Conversion Sequence.

Defines a sequence of channels to be converted as an injected group with a length from 1 to 4 channels. If this is called during conversion, the current conversion is reset and conversion begins again with the newly defined group.

Parameters

[in]	adc	Unsigned int32. ADC block register address base ADC register base addresses
[in]	length	Unsigned int8. Number of channels in the group.
[in]	channel	Unsigned int8[]. Set of channels in sequence, integers 0..18

Definition at line 407 of file adc.c.

References ADC_JSQR, ADC_JSQR_JL_VAL, and ADC_JSQR_JSQ_VAL.

◆ adc_set_left_aligned()

void adc_set_left_aligned ( uint32_t adc )

ADC Set the Data as Left Aligned.

Parameters

[in] adc Unsigned int32. ADC base address (ADC register base addresses)

Definition at line 223 of file adc_common_v2.c.

References ADC_CFGR1, and ADC_CFGR1_ALIGN.

◆ adc_set_multi_mode()

void adc_set_multi_mode	(	uint32_t	adc,
		uint32_t	mode
	)

ADC set multi mode.

The multiple mode can uses these arrangement:

ADC1 as master and ADC2 as slave
ADC3 as master and ADC4 as slave

This setting is applied to ADC master only (ADC1 or ADC3).

The various modes possible are described in the reference manual.

Parameters

	adc	peripheral of choice ADC register base addresses
[in]	mode	Multiple mode selection from ADC Multi mode selection

Definition at line 567 of file adc.c.

References ADC_CCR, ADC_CCR_DUAL_MASK, and ADC_CCR_DUAL_SHIFT.

◆ adc_set_regular_sequence()

void adc_set_regular_sequence	(	uint32_t	adc,
		uint8_t	length,
		uint8_t	channel[]
	)

ADC Set a Regular Channel Conversion Sequence.

Define a sequence of channels to be converted as a regular group with a length from 1 to 16 channels. If this is called during conversion, the current conversion is reset and conversion begins again with the newly defined group.

Parameters

[in]	adc	ADC block register address base ADC register base addresses
[in]	length	Number of channels in the group, range 0..16
[in]	channel	Set of channels in sequence, range ADC Channel Numbers

Definition at line 100 of file adc_common_v2_multi.c.

References ADC_SQR1, ADC_SQR1_L_SHIFT, ADC_SQR2, ADC_SQR3, and ADC_SQR4.

◆ adc_set_resolution()

void adc_set_resolution	(	uint32_t	adc,
		uint16_t	resolution
	)

ADC Set Resolution.

ADC Resolution can be reduced from 12 bits to 10, 8 or 6 bits for a corresponding reduction in conversion time.

Parameters

[in]	adc	Unsigned int32. ADC base address (ADC register base addresses)
[in]	resolution	Unsigned int16. Resolution value (adc_api_res)

Definition at line 214 of file adc_common_v2.c.

References ADC_CFGR1.

◆ adc_set_right_aligned()

void adc_set_right_aligned ( uint32_t adc )

ADC Set the Data as Right Aligned.

Parameters

[in] adc Unsigned int32. ADC base address (ADC register base addresses)

Definition at line 232 of file adc_common_v2.c.

References ADC_CFGR1.

◆ adc_set_sample_time()

void adc_set_sample_time	(	uint32_t	adc,
		uint8_t	channel,
		uint8_t	time
	)

ADC Set the Sample Time for a Single Channel.

The sampling time can be selected in ADC clock cycles, exact values depend on the device.

Parameters

[in]	adc	ADC block register address base ADC register base addresses
[in]	channel	ADC Channel integer ADC Channel Numbers
[in]	time	Sampling time selection from ADC Sample Time Selection values

Definition at line 47 of file adc_common_v2_multi.c.

References ADC_SMPR1, and ADC_SMPR2.

◆ adc_set_sample_time_on_all_channels()

void adc_set_sample_time_on_all_channels	(	uint32_t	adc,
		uint8_t	time
	)

ADC Set the Sample Time for All Channels.

The sampling time can be selected in ADC clock cycles, exact values depend on the device.

Parameters

[in]	adc	ADC block register address base ADC register base addresses
[in]	time	Sampling time selection from ADC Sample Time Selection values

Definition at line 72 of file adc_common_v2_multi.c.

References ADC_SMPR1, and ADC_SMPR2.

◆ adc_set_single_conversion_mode()

void adc_set_single_conversion_mode ( uint32_t adc )

Enable Single Conversion Mode In this mode the ADC performs a conversion of one channel or a channel group and stops.

Parameters

[in] adc ADC block register address base ADC register base addresses

Definition at line 201 of file adc_common_v2.c.

References ADC_CFGR1.

◆ adc_set_watchdog_high_threshold()

void adc_set_watchdog_high_threshold	(	uint32_t	adc,
		uint16_t	threshold
	)

ADC Set Analog Watchdog Upper Threshold.

Parameters

[in]	adc	ADC block register address base ADC register base addresses
[in]	threshold	Upper threshold value

Definition at line 362 of file adc.c.

References ADC_TR1, ADC_TR2, and ADC_TR3.

◆ adc_set_watchdog_low_threshold()

void adc_set_watchdog_low_threshold	(	uint32_t	adc,
		uint16_t	threshold
	)

ADC Set Analog Watchdog Lower Threshold.

Parameters

[in]	adc	ADC block register address base ADC register base addresses
[in]	threshold	Lower threshold value

Definition at line 380 of file adc.c.

References ADC_TR1, ADC_TR2, and ADC_TR3.

◆ adc_start_conversion_injected()

void adc_start_conversion_injected ( uint32_t adc )

ADC Software Triggered Conversion on Injected Channels.

This starts conversion on a set of defined injected channels. Depending on the configuration bits JEXTEN, a conversion will start immediately (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration).

Parameters

[in] adc Unsigned int32. ADC block register address base ADC register base addresses

Definition at line 350 of file adc.c.

References ADC_CR, and ADC_CR_JADSTART.

◆ adc_start_conversion_regular()

void adc_start_conversion_regular ( uint32_t adc )

ADC Software Triggered Conversion on Regular Channels.

This starts conversion on a set of defined regular channels. Depending on the configuration bits EXTEN, a conversion will start immediately (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration)

Parameters

[in] adc ADC block register address base ADC register base addresses

Definition at line 386 of file adc_common_v2.c.

References ADC_CR, and ADC_CR_ADSTART.

Modules

Macros

Functions

Detailed Description

Macro Definition Documentation

◆ ADC12_CFGR1_EXTSEL_EXTI11

◆ ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG1

◆ ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG10

◆ ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG3

◆ ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG5

◆ ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG6

◆ ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG7

◆ ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG8

◆ ADC12_CFGR1_EXTSEL_HRTIM_ADC_TRG9

◆ ADC12_CFGR1_EXTSEL_LPTIMOUT

◆ ADC12_CFGR1_EXTSEL_TIM15_TRGO

◆ ADC12_CFGR1_EXTSEL_TIM1_CC1

◆ ADC12_CFGR1_EXTSEL_TIM1_CC2

◆ ADC12_CFGR1_EXTSEL_TIM1_CC3

◆ ADC12_CFGR1_EXTSEL_TIM1_TRGO

◆ ADC12_CFGR1_EXTSEL_TIM1_TRGO2

◆ ADC12_CFGR1_EXTSEL_TIM20_CC1

◆ ADC12_CFGR1_EXTSEL_TIM20_CC2

◆ ADC12_CFGR1_EXTSEL_TIM20_CC3

◆ ADC12_CFGR1_EXTSEL_TIM20_TRGO

◆ ADC12_CFGR1_EXTSEL_TIM20_TRGO2

◆ ADC12_CFGR1_EXTSEL_TIM2_CC2

◆ ADC12_CFGR1_EXTSEL_TIM2_TRGO

◆ ADC12_CFGR1_EXTSEL_TIM3_CC4

◆ ADC12_CFGR1_EXTSEL_TIM3_TRGO

◆ ADC12_CFGR1_EXTSEL_TIM4_CC4

◆ ADC12_CFGR1_EXTSEL_TIM4_TRGO

◆ ADC12_CFGR1_EXTSEL_TIM6_TRGO

◆ ADC12_CFGR1_EXTSEL_TIM7_TRGO

◆ ADC12_CFGR1_EXTSEL_TIM8_TRGO

◆ ADC12_CFGR1_EXTSEL_TIM8_TRGO2

◆ ADC12_JSQR_JEXTSEL_EXTI15

◆ ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG10

◆ ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG2

◆ ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG4

◆ ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG5

◆ ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG6

◆ ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG7

◆ ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG8

◆ ADC12_JSQR_JEXTSEL_HRTIM_ADC_TRG9

◆ ADC12_JSQR_JEXTSEL_LPTIMOUT

◆ ADC12_JSQR_JEXTSEL_TIM15_TRGO

◆ ADC12_JSQR_JEXTSEL_TIM16_CC1

◆ ADC12_JSQR_JEXTSEL_TIM1_CC4

◆ ADC12_JSQR_JEXTSEL_TIM1_TRGO

◆ ADC12_JSQR_JEXTSEL_TIM1_TRGO2

◆ ADC12_JSQR_JEXTSEL_TIM20_CC4

◆ ADC12_JSQR_JEXTSEL_TIM20_TRGO

◆ ADC12_JSQR_JEXTSEL_TIM20_TRGO2

◆ ADC12_JSQR_JEXTSEL_TIM2_CC1

◆ ADC12_JSQR_JEXTSEL_TIM2_TRGO

◆ ADC12_JSQR_JEXTSEL_TIM3_CC1

◆ ADC12_JSQR_JEXTSEL_TIM3_CC3

◆ ADC12_JSQR_JEXTSEL_TIM3_CC4

◆ ADC12_JSQR_JEXTSEL_TIM3_TRGO

◆ ADC12_JSQR_JEXTSEL_TIM4_TRGO

◆ ADC12_JSQR_JEXTSEL_TIM6_TRGO

◆ ADC12_JSQR_JEXTSEL_TIM7_TRGO

◆ ADC12_JSQR_JEXTSEL_TIM8_CC4

◆ ADC12_JSQR_JEXTSEL_TIM8_TRGO

◆ ADC12_JSQR_JEXTSEL_TIM8_TRGO2

◆ ADC345_CFGR1_EXTSEL_EXTI2

◆ ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG1

◆ ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG10

◆ ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG2

◆ ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG3

◆ ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG4

◆ ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG5

◆ ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG6

◆ ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG7

◆ ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG8

◆ ADC345_CFGR1_EXTSEL_HRTIM_ADC_TRG9

◆ ADC345_CFGR1_EXTSEL_LPTIMOUT

◆ ADC345_CFGR1_EXTSEL_TIM15_TRGO

◆ ADC345_CFGR1_EXTSEL_TIM1_CC3