ADC registers

Collaboration diagram for ADC registers:

Macros
#define	ADC_ISR(adc)   MMIO32((adc) + 0x00)
	ADC interrupt and status register. More...
#define	ADC_IER(adc)   MMIO32((adc) + 0x04)
	Interrupt Enable Register. More...
#define	ADC_CR(adc)   MMIO32((adc) + 0x08)
	Control Register. More...
#define	ADC_CFGR1(adc)   MMIO32((adc) + 0x0C)
	Configuration Register 1. More...
#define	ADC_CFGR2(adc)   MMIO32((adc) + 0x10)
	Configuration Register 2. More...
#define	ADC_SMPR1(adc)   MMIO32((adc) + 0x14)
	Sample Time Register 1. More...
#define	ADC_TR1(adc)   MMIO32((adc) + 0x20)
	Watchdog Threshold Register 1. More...
#define	ADC_DR(adc)   MMIO32((adc) + 0x40)
	Regular Data Register. More...
#define	ADC_CCR(adc)   MMIO32((adc) + 0x300 + 0x8)
	Common Configuration register. More...
#define	ADC_SMPR2(adc)   MMIO32((adc) + 0x18)
#define	ADC_TR2(adc)   MMIO32((adc) + 0x24)
#define	ADC_TR3(adc)   MMIO32((adc) + 0x28)
#define	ADC_SQR1(adc)   MMIO32((adc) + 0x30)
#define	ADC_SQR2(adc)   MMIO32((adc) + 0x34)
#define	ADC_SQR3(adc)   MMIO32((adc) + 0x38)
#define	ADC_SQR4(adc)   MMIO32((adc) + 0x3C)
#define	ADC_JSQR(adc)   MMIO32((adc) + 0x4c)
#define	ADC_OFR1(adc)   MMIO32((adc) + 0x60)
#define	ADC_OFR2(adc)   MMIO32((adc) + 0x64)
#define	ADC_OFR3(adc)   MMIO32((adc) + 0x68)
#define	ADC_OFR4(adc)   MMIO32((adc) + 0x6C)
#define	ADC_JDR1(adc)   MMIO32((adc) + 0x80)
#define	ADC_JDR2(adc)   MMIO32((adc) + 0x84)
#define	ADC_JDR3(adc)   MMIO32((adc) + 0x88)
#define	ADC_JDR4(adc)   MMIO32((adc) + 0x8C)
#define	ADC_AWD2CR(adc)   MMIO32((adc) + 0xA0)
#define	ADC_AWD3CR(adc)   MMIO32((adc) + 0xA4)
#define	ADC_DIFSEL(adc)   MMIO32((adc) + 0xB0)
#define	ADC_CALFACT(adc)   MMIO32((adc) + 0xB4)
#define	ADC_CSR(adc)   MMIO32((adc) + 0x300 + 0x0)
#define	ADC_CDR(adc)   MMIO32((adc) + 0x300 + 0xc)

Detailed Description

Macro Definition Documentation

ADC_AWD2CR

#define ADC_AWD2CR

(

adc

)

MMIO32((adc) + 0xA0)

Definition at line 76 of file adc_common_v2_multi.h.

ADC_AWD3CR

#define ADC_AWD3CR

(

adc

)

MMIO32((adc) + 0xA4)

Definition at line 78 of file adc_common_v2_multi.h.

ADC_CALFACT

#define ADC_CALFACT

(

adc

)

MMIO32((adc) + 0xB4)

Definition at line 84 of file adc_common_v2_multi.h.

ADC_CCR

#define ADC_CCR

(

adc

)

MMIO32((adc) + 0x300 + 0x8)

Common Configuration register.

Definition at line 60 of file adc_common_v2.h.

ADC_CDR

#define ADC_CDR

(

adc

)

MMIO32((adc) + 0x300 + 0xc)

Definition at line 88 of file adc_common_v2_multi.h.

ADC_CFGR1

#define ADC_CFGR1

(

adc

)

MMIO32((adc) + 0x0C)

Configuration Register 1.

Definition at line 48 of file adc_common_v2.h.

ADC_CFGR2

#define ADC_CFGR2

(

adc

)

MMIO32((adc) + 0x10)

Configuration Register 2.

Definition at line 50 of file adc_common_v2.h.

ADC_CR

#define ADC_CR

(

adc

)

MMIO32((adc) + 0x08)

Control Register.

Definition at line 46 of file adc_common_v2.h.

ADC_CSR

#define ADC_CSR

(

adc

)

MMIO32((adc) + 0x300 + 0x0)

Definition at line 87 of file adc_common_v2_multi.h.

ADC_DIFSEL

#define ADC_DIFSEL

(

adc

)

MMIO32((adc) + 0xB0)

Definition at line 81 of file adc_common_v2_multi.h.

ADC_DR

#define ADC_DR

(

adc

)

MMIO32((adc) + 0x40)

Regular Data Register.

Definition at line 56 of file adc_common_v2.h.

ADC_IER

#define ADC_IER

(

adc

)

MMIO32((adc) + 0x04)

Interrupt Enable Register.

Definition at line 44 of file adc_common_v2.h.

ADC_ISR

#define ADC_ISR

(

adc

)

MMIO32((adc) + 0x00)

ADC interrupt and status register.

Definition at line 42 of file adc_common_v2.h.

ADC_JDR1

#define ADC_JDR1

(

adc

)

MMIO32((adc) + 0x80)

Definition at line 70 of file adc_common_v2_multi.h.

ADC_JDR2

#define ADC_JDR2

(

adc

)

MMIO32((adc) + 0x84)

Definition at line 71 of file adc_common_v2_multi.h.

ADC_JDR3

#define ADC_JDR3

(

adc

)

MMIO32((adc) + 0x88)

Definition at line 72 of file adc_common_v2_multi.h.

ADC_JDR4

#define ADC_JDR4

(

adc

)

MMIO32((adc) + 0x8C)

Definition at line 73 of file adc_common_v2_multi.h.

ADC_JSQR

#define ADC_JSQR

(

adc

)

MMIO32((adc) + 0x4c)

Definition at line 61 of file adc_common_v2_multi.h.

ADC_OFR1

#define ADC_OFR1

(

adc

)

MMIO32((adc) + 0x60)

Definition at line 64 of file adc_common_v2_multi.h.

ADC_OFR2

#define ADC_OFR2

(

adc

)

MMIO32((adc) + 0x64)

Definition at line 65 of file adc_common_v2_multi.h.

ADC_OFR3

#define ADC_OFR3

(

adc

)

MMIO32((adc) + 0x68)

Definition at line 66 of file adc_common_v2_multi.h.

ADC_OFR4

#define ADC_OFR4

(

adc

)

MMIO32((adc) + 0x6C)

Definition at line 67 of file adc_common_v2_multi.h.

ADC_SMPR1

#define ADC_SMPR1

(

adc

)

MMIO32((adc) + 0x14)

Sample Time Register 1.

Definition at line 52 of file adc_common_v2.h.

ADC_SMPR2

#define ADC_SMPR2

(

adc

)

MMIO32((adc) + 0x18)

Definition at line 49 of file adc_common_v2_multi.h.

ADC_SQR1

#define ADC_SQR1

(

adc

)

MMIO32((adc) + 0x30)

Definition at line 55 of file adc_common_v2_multi.h.

ADC_SQR2

#define ADC_SQR2

(

adc

)

MMIO32((adc) + 0x34)

Definition at line 56 of file adc_common_v2_multi.h.

ADC_SQR3

#define ADC_SQR3

(

adc

)

MMIO32((adc) + 0x38)

Definition at line 57 of file adc_common_v2_multi.h.

ADC_SQR4

#define ADC_SQR4

(

adc

)

MMIO32((adc) + 0x3C)

Definition at line 58 of file adc_common_v2_multi.h.

ADC_TR1

#define ADC_TR1

(

adc

)

MMIO32((adc) + 0x20)

Watchdog Threshold Register 1.

Definition at line 54 of file adc_common_v2.h.

ADC_TR2

#define ADC_TR2

(

adc

)

MMIO32((adc) + 0x24)

Definition at line 51 of file adc_common_v2_multi.h.

ADC_TR3

#define ADC_TR3

(

adc

)

MMIO32((adc) + 0x28)

Definition at line 53 of file adc_common_v2_multi.h.