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#define | DAC_SR_DMAUDR1 (1 << 13) |
| DAC channel 1 DMA underrun flag. More...
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#define | DAC_SR_DMAUDR2 (1 << 29) |
| DAC channel 2 DMA underrun flag. More...
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#define | DAC_SR_BWST2 (1 << 31) |
| DAC channel2 busy writing sample time flag. More...
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#define | DAC_SR_CAL_FLAG2 (1 << 30) |
| DAC channel2 calibration offset status. More...
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#define | DAC_SR_DMAUDR2 (1 << 29) |
| DAC channel2 DMA underrun flag. More...
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#define | DAC_SR_DORSTAT2 (1 << 28) |
| DAC channel2 output register status bit. More...
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#define | DAC_SR_DAC2RDY (1 << 27) |
| DAC channel2 ready status bit. More...
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#define | DAC_SR_BWST1 (1 << 15) |
| DAC channel1 busy writing sample time flag. More...
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#define | DAC_SR_CAL_FLAG1 (1 << 14) |
| DAC channel1 calibration offset status. More...
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#define | DAC_SR_DMAUDR1 (1 << 13) |
| DAC channel1 DMA underrun flag. More...
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#define | DAC_SR_DORSTAT1 (1 << 12) |
| DAC channel1 output register status bit. More...
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#define | DAC_SR_DAC1RDY (1 << 11) |
| DAC channel1 ready status bit. More...
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