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#define | QUADSPI_CR MMIO32(QUADSPI_BASE + 0x0U) |
| QUADSPI Control register. More...
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#define | QUADSPI_DCR MMIO32(QUADSPI_BASE + 0x4U) |
| QUADSPI Device Configuration. More...
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#define | QUADSPI_SR MMIO32(QUADSPI_BASE + 0x8U) |
| QUADSPI Status Register. More...
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#define | QUADSPI_FCR MMIO32(QUADSPI_BASE + 0xCU) |
| QUADSPI Flag Clear Register. More...
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#define | QUADSPI_DLR MMIO32(QUADSPI_BASE + 0x10U) |
| QUADSPI Data Length Register. More...
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#define | QUADSPI_CCR MMIO32(QUADSPI_BASE + 0x14U) |
| QUADSPI Communication Configuration Register. More...
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#define | QUADSPI_AR MMIO32(QUADSPI_BASE + 0x18U) |
| QUADSPI address register. More...
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#define | QUADSPI_ABR MMIO32(QUADSPI_BASE + 0x1CU) |
| QUADSPI alternate bytes register. More...
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#define | QUADSPI_DR MMIO32(QUADSPI_BASE + 0x20U) |
| QUADSPI data register. More...
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#define | QUADSPI_BYTE_DR MMIO8(QUADSPI_BASE + 0x20U) |
| BYTE addressable version for fetching bytes from the interface. More...
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#define | QUADSPI_PSMKR MMIO32(QUADSPI_BASE + 0x24U) |
| QUADSPI polling status. More...
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#define | QUADSPI_PSMAR MMIO32(QUADSPI_BASE + 0x28U) |
| QUADSPI polling status match. More...
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#define | QUADSPI_PIR MMIO32(QUADSPI_BASE + 0x2CU) |
| QUADSPI polling interval register. More...
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#define | QUADSPI_LPTR MMIO32(QUADSPI_BASE + 0x30U |
| QUADSPI low power timeout. More...
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