|
| #define | CAN_MSG_BASE FDCAN1_RAM_BASE |
| |
| #define | FDCAN_RXFIS_BASE 0x0090 |
| |
| #define | FDCAN_RXFIA_BASE 0x0094 |
| |
| #define | FDCAN_RXFI_OFFSET 0x0008 |
| |
| #define | FDCAN_RXGFC(can_base) MMIO32(can_base + 0x0080) |
| |
| #define | FDCAN_XIDAM(can_base) MMIO32(can_base + 0x0084) |
| |
| #define | FDCAN_HPMS(can_base) MMIO32(can_base + 0x0088) |
| |
| #define | FDCAN_TXBRP(can_base) MMIO32(can_base + 0x00C8) |
| |
| #define | FDCAN_TXBAR(can_base) MMIO32(can_base + 0x00CC) |
| |
| #define | FDCAN_TXBCR(can_base) MMIO32(can_base + 0x00D0) |
| |
| #define | FDCAN_TXBTO(can_base) MMIO32(can_base + 0x00D4) |
| |
| #define | FDCAN_TXBCF(can_base) MMIO32(can_base + 0x00D8) |
| |
| #define | FDCAN_TXBTIE(can_base) MMIO32(can_base + 0x00DC) |
| |
| #define | FDCAN_TXBCIE(can_base) MMIO32(can_base + 0x00E0) |
| |
| #define | FDCAN_TXEFS(can_base) MMIO32(can_base + 0x00E4) |
| |
| #define | FDCAN_TXEFA(can_base) MMIO32(can_base + 0x00E8) |
| |
| #define | FDCAN_CKDIV(can_base) MMIO32(can_base + 0x0100) |
| |
| #define | FDCAN_RXGFC_RRFE (1 << 0) |
| |
| #define | FDCAN_RXGFC_RRFS (1 << 1) |
| |
| #define | FDCAN_RXGFC_ANFE_SHIFT 2 |
| | ANFE[1:0]: Accept non-matching frames w/ extended ID. More...
|
| |
| #define | FDCAN_RXGFC_ANFE_MASK 0x3 |
| |
| #define | FDCAN_RXGFC_ANFS_SHIFT 4 |
| | ANFS[1:0]: Accept non-matching frames w/ standard ID. More...
|
| |
| #define | FDCAN_RXGFC_ANFS_MASK 0x3 |
| |
| #define | FDCAN_RXGFC_F1OM (1 << 8) |
| |
| #define | FDCAN_RXGFC_F0OM (1 << 9) |
| |
| #define | FDCAN_RXGFC_LSS_SHIFT 16 |
| | LSS[4:0]: List size of standard ID filters. More...
|
| |
| #define | FDCAN_RXGFC_LSS_MASK 0x1F |
| |
| #define | FDCAN_RXGFC_LSE_SHIFT 24 |
| | LSE[3:0]: List size of extended ID filters. More...
|
| |
| #define | FDCAN_RXGFC_LSE_MASK 0xF |
| |
| #define | FDCAN_RXFIFO_FL_MASK 0xF |
| |
| #define | FDCAN_RXFIFO_GI_MASK 0x3 |
| |
| #define | FDCAN_RXFIFO_PI_MASK 0x3 |
| |
| #define | FDCAN_RXFIFO_AI_MASK 0x3 |
| |
| #define | FDCAN_TXFQS_TFFL_MASK 0x7 |
| |
| #define | FDCAN_TXFQS_TFGI_MASK 0x3 |
| |
| #define | FDCAN_TXFQS_TFQPI_MASK 0x3 |
| |
| #define | FDCAN_TXEFS_EFFL_MASK 0x7 |
| |
| #define | FDCAN_TXEFS_EFGI_MASK 0x3 |
| |
| #define | FDCAN_TXEFS_EFPI_MASK 0x3 |
| |
| #define | FDCAN_CKDIV_PDIV_SHIFT 0 |
| |
| #define | FDCAN_CKDIV_PDIV_MASK 0xF |
| |
| #define | FDCAN_SFT_MAX_NR 28 |
| | Amount of standard filters allocated in Message RAM This number may vary between devices. More...
|
| |
| #define | FDCAN_EFT_MAX_NR 8 |
| | Amount of extended filters allocated in Message RAM This number may vary between devices. More...
|
| |
| #define | FDCAN_LFSSA_OFFSET(can_base) ((FDCAN_BLOCK_ID(can_base) * 0x0350) + 0x0000) |
| |
| #define | FDCAN_LFESA_OFFSET(can_base) ((FDCAN_BLOCK_ID(can_base) * 0x0350) + 0x0070) |
| |
| #define | FDCAN_RXFIFOS_OFFSET(can_base) ((FDCAN_BLOCK_ID(can_base) * 0x0350) + 0x00B0) |
| |
| #define | FDCAN_RXFIFO_OFFSET(can_base, fifo_id) (FDCAN_RXFIFOS_OFFSET(can_base) + (0x00D8 * (fifo_id))) |
| |
| #define | FDCAN_TXEVT_OFFSET(can_base) ((FDCAN_BLOCK_ID(can_base) * 0x0350) + 0x0260) |
| |
| #define | FDCAN_TXBUF_OFFSET(can_base) ((FDCAN_BLOCK_ID(can_base) * 0x0350) + 0x0278) |
| |
| #define | FDCAN_BLOCK_ID(can_base) (((can_base) - CAN1)/(CAN2 - CAN1)) |
| |
| #define | FDCAN_CREL(can_base) MMIO32(can_base + 0x0000) |
| |
| #define | FDCAN_ENDN(can_base) MMIO32(can_base + 0x0004) |
| |
| #define | FDCAN_DBTP(can_base) MMIO32(can_base + 0x000C) |
| |
| #define | FDCAN_TEST(can_base) MMIO32(can_base + 0x0010) |
| |
| #define | FDCAN_RWD(can_base) MMIO32(can_base + 0x0014) |
| |
| #define | FDCAN_CCCR(can_base) MMIO32(can_base + 0x0018) |
| |
| #define | FDCAN_NBTP(can_base) MMIO32(can_base + 0x001C) |
| |
| #define | FDCAN_TSCC(can_base) MMIO32(can_base + 0x0020) |
| |
| #define | FDCAN_TSCV(can_base) MMIO32(can_base + 0x0024) |
| |
| #define | FDCAN_TOCC(can_base) MMIO32(can_base + 0x0028) |
| |
| #define | FDCAN_TOCV(can_base) MMIO32(can_base + 0x002C) |
| |
| #define | FDCAN_ECR(can_base) MMIO32(can_base + 0x0040) |
| |
| #define | FDCAN_PSR(can_base) MMIO32(can_base + 0x0044) |
| |
| #define | FDCAN_TDCR(can_base) MMIO32(can_base + 0x0048) |
| |
| #define | FDCAN_IR(can_base) MMIO32(can_base + 0x0050) |
| |
| #define | FDCAN_IE(can_base) MMIO32(can_base + 0x0054) |
| |
| #define | FDCAN_ILS(can_base) MMIO32(can_base + 0x0058) |
| |
| #define | FDCAN_ILE(can_base) MMIO32(can_base + 0x005C) |
| |
| #define | FDCAN_RXFIS(can_base, fifo_id) MMIO32(can_base + FDCAN_RXFIS_BASE + (FDCAN_RXFI_OFFSET * fifo_id)) |
| | Generic access to Rx FIFO status registers. More...
|
| |
| #define | FDCAN_RXF0S(can_base) FDCAN_RXFIS(can_base, 0) |
| |
| #define | FDCAN_RXF1S(can_base) FDCAN_RXFIS(can_base, 1) |
| |
| #define | FDCAN_RXFIA(can_base, fifo_id) MMIO32(can_base + FDCAN_RXFIA_BASE + (FDCAN_RXFI_OFFSET * fifo_id)) |
| | Generic access to Rx FIFO acknowledge registers. More...
|
| |
| #define | FDCAN_RXF0A(can_base) FDCAN_RXFIA(can_base, 0) |
| |
| #define | FDCAN_RXF1A(can_base) FDCAN_RXFIA(can_base, 1) |
| |
| #define | FDCAN_TXBC(can_base) MMIO32(can_base + 0x00C0) |
| |
| #define | FDCAN_TXFQS(can_base) MMIO32(can_base + 0x00C4) |
| |
| #define | FDCAN_CREL_DAY_SHIFT 0 |
| | DAY[7:0]: FDCAN core revision date. More...
|
| |
| #define | FDCAN_CREL_DAY_MASK 0xFF |
| |
| #define | FDCAN_CREL_MON_SHIFT 8 |
| | MON[7:0]: FDCAN core revision month. More...
|
| |
| #define | FDCAN_CREL_MON_MASK 0xFF |
| |
| #define | FDCAN_CREL_YEAR_SHIFT 16 |
| | YEAR[3:0]: FDCAN core revision year. More...
|
| |
| #define | FDCAN_CREL_YEAR_MASK 0xF |
| |
| #define | FDCAN_CREL_SUBSTEP_SHIFT 20 |
| | SUBSTEP[3:0]: FDCAN core release sub stepping. More...
|
| |
| #define | FDCAN_CREL_SUBSTEP_MASK 0xF |
| |
| #define | FDCAN_CREL_STEP_SHIFT 24 |
| | STEP[3:0]: FDCAN core release stepping. More...
|
| |
| #define | FDCAN_CREL_STEP_MASK 0xF |
| |
| #define | FDCAN_CREL_REL_SHIFT 28 |
| | REL[3:0]: FDCAN core release number. More...
|
| |
| #define | FDCAN_CREL_REL_MASK 0xF |
| |
| #define | FDCAN_DBTP_DSJW_SHIFT 0 |
| | DSJW[3:0]: Synchronization jump width. More...
|
| |
| #define | FDCAN_DBTP_DSJW_MASK 0xF |
| |
| #define | FDCAN_DBTP_DTSEG2_SHIFT 4 |
| | DTSEG2[3:0]: Data time segment after sample point. More...
|
| |
| #define | FDCAN_DBTP_DTSEG2_MASK 0xF |
| |
| #define | FDCAN_DBTP_DTSEG1_SHIFT 8 |
| | DTSEG1[4:0]: Data time segment before sample point. More...
|
| |
| #define | FDCAN_DBTP_DTSEG1_MASK 0x1F |
| |
| #define | FDCAN_DBTP_DBRP_SHIFT 16 |
| | DBRP[4:0]: Data bit rate prescaler. More...
|
| |
| #define | FDCAN_DBTP_DBRP_MASK 0x1F |
| |
| #define | FDCAN_DBTP_TDC (1 << 23) |
| |
| #define | FDCAN_TEST_LBCK (1 << 4) |
| |
| #define | FDCAN_TEST_TX_SHIFT 5 |
| | TX[1:0]: Control of transmit pin. More...
|
| |
| #define | FDCAN_TEST_TX_MASK 0x3 |
| |
| #define | FDCAN_TEST_RX (1 << 7) |
| |
| #define | FDCAN_RWD_WDC_SHIFT 0 |
| | WDC[7:0]: RAM watchdog configuration. More...
|
| |
| #define | FDCAN_RWD_WDC_MASK 0xFF |
| |
| #define | FDCAN_RWD_WDV_SHIFT 7 |
| | WDV[7:0]: RAM watchdog actual value. More...
|
| |
| #define | FDCAN_RWD_WDV_MASK 0xFF |
| |
| #define | FDCAN_CCCR_INIT_TIMEOUT 0x0000FFFF |
| | Timeout for FDCAN_CCCR register INIT bit to accept set value. More...
|
| |
| #define | FDCAN_NBTP_NTSEG2_SHIFT 0 |
| | NTSEG2[6:0]: Nominal timing segment after sample point length. More...
|
| |
| #define | FDCAN_NBTP_NTSEG2_MASK 0x7F |
| |
| #define | FDCAN_NBTP_NTSEG1_SHIFT 8 |
| | NTSEG1[7:0]: Nominal timing segment before sample point length. More...
|
| |
| #define | FDCAN_NBTP_NTSEG1_MASK 0xFF |
| |
| #define | FDCAN_NBTP_NBRP_SHIFT 16 |
| | NBRP[8:0]: Norminal timing bit rate prescaler. More...
|
| |
| #define | FDCAN_NBTP_NBRP_MASK 0x1FF |
| |
| #define | FDCAN_NBTP_NSJW_SHIFT 25 |
| | NSJW[6:0]: Norminal timing resynchronization jumb width. More...
|
| |
| #define | FDCAN_NBTP_NSJW_MASK 0x7F |
| |
| #define | FDCAN_TSCC_TSS_SHIFT 0 |
| | TSS[1:0]: Timestamp select. More...
|
| |
| #define | FDCAN_TSCC_TSS_MASK 0x3 |
| |
| #define | FDCAN_TSCC_TCP_SHIFT 16 |
| | TCP[3:0]: Timestamp counter prescaler. More...
|
| |
| #define | FDCAN_TSCC_TCP_MASK 0xF |
| |
| #define | FDCAN_TSCV_TSC_SHIFT 0 |
| | TSC[15:0]: Timestamp counter value. More...
|
| |
| #define | FDCAN_TSCV_TSC_MASK 0xFFFF |
| |
| #define | FDCAN_TOCC_ETOC (1 << 0) |
| |
| #define | FDCAN_TOCC_TOS_SHIFT 1 |
| | TOS[1:0]: Timeout select. More...
|
| |
| #define | FDCAN_TOCC_TOS_MASK 0x3 |
| |
| #define | FDCAN_TOCC_TOP_SHIFT 16 |
| | TOP[15:0]: Timeout period. More...
|
| |
| #define | FDCAN_TOCC_TOP_MASK 0xFFFF |
| |
| #define | FDCAN_TOCV_TOC_SHIFT 0 |
| | TOC[15:0]: Timeout counter. More...
|
| |
| #define | FDCAN_TOCV_TOC_MASK 0xFFFF |
| |
| #define | FDCAN_ECR_TEC_SHIFT 0 |
| | TEC[7:0]: Transmit error counter. More...
|
| |
| #define | FDCAN_ECR_TEC_MASK 0xFF |
| |
| #define | FDCAN_ECR_REC_SHIFT 8 |
| | REC[6:0]: Receive error counter. More...
|
| |
| #define | FDCAN_ECR_REC_MASK 0x7F |
| |
| #define | FDCAN_ECR_RP (1 << 15) |
| |
| #define | FDCAN_ECR_CEL_SHIFT 16 |
| | CEL[7:0]: CAN error logging. More...
|
| |
| #define | FDCAN_ECR_CEL_MASK 0xFF |
| |
| #define | FDCAN_PSR_LEC_SHIFT 0 |
| | LEC[2:0]: Last error code. More...
|
| |
| #define | FDCAN_PSR_LEC_MASK 0x7 |
| |
| #define | FDCAN_PSR_ACT_SHIFT 3 |
| | ACT[1:0]: CAN block activity. More...
|
| |
| #define | FDCAN_PSR_ACT_MASK 0x3 |
| |
| #define | FDCAN_PSR_EP (1 << 5) |
| |
| #define | FDCAN_PSR_EW (1 << 6) |
| |
| #define | FDCAN_PSR_BO (1 << 7) |
| |
| #define | FDCAN_PSR_DLEC_SHIFT 8 |
| | DLEC[2:0]: Last error code in data section. More...
|
| |
| #define | FDCAN_PSR_DLEC_MASK 0x7 |
| |
| #define | FDCAN_PSR_RESI (1 << 11) |
| |
| #define | FDCAN_PSR_RBRSRESI1 (1 << 12) |
| |
| #define | FDCAN_PSR_REDL (1 << 13) |
| |
| #define | FDCAN_PSR_PXE (1 << 14) |
| |
| #define | FDCAN_PSR_TDCV_SHIFT 16 |
| | TDCV[6:0]: Transmitter delay compensation value. More...
|
| |
| #define | FDCAN_PSR_TDCV_MASK 0x7F |
| |
| #define | FDCAN_TDCR_TDCF_SHIFT 0 |
| | TDCF[6:0]: Transmitter delay compensation filter window length. More...
|
| |
| #define | FDCAN_TDCR_TDCF_MASK 0x7F |
| |
| #define | FDCAN_TDCR_TDCO_SHIFT 8 |
| | TDCO[6:0]: Transmitter delay compensation offset. More...
|
| |
| #define | FDCAN_TDCR_TDCO_MASK 0x7F |
| |
| #define | FDCAN_ILE_INT0 (1 << 0) |
| |
| #define | FDCAN_ILE_INT1 (1 << 1) |
| |
| #define | FDCAN_XIDAM_EIDM_SHIFT 0 |
| | EIDM[28:0]: Extended ID mask for filtering. More...
|
| |
| #define | FDCAN_XIDAM_EIDM_MASK 0x1FFFFFFF |
| |
| #define | FDCAN_HPMS_BIDX_SHIFT 0 |
| | BIDX[2:0]: Buffer index. More...
|
| |
| #define | FDCAN_HPMS_BIDX_MASK 0x7 |
| |
| #define | FDCAN_HPMS_MSI_SHIFT 6 |
| | MSI[1:0]: Message storage indicator. More...
|
| |
| #define | FDCAN_HPMS_MSI_MASK 0x3 |
| |
| #define | FDCAN_HPMS_FIDX_SHIFT 8 |
| | FIDX[4:0]: Filter index. More...
|
| |
| #define | FDCAN_HPMS_FIDX_MASK 0x1F |
| |
| #define | FDCAN_HPMS_FLS (1 << 15) |
| |
| #define | FDCAN_RXFIFO_FL_SHIFT 0 |
| | Fill level of Rx FIFOs. More...
|
| |
| #define | FDCAN_RXFIFO_GI_SHIFT 8 |
| | Get index of Rx FIFOs. More...
|
| |
| #define | FDCAN_RXFIFO_PI_SHIFT 16 |
| | Put index of Rx FIFOs. More...
|
| |
| #define | FDCAN_RXFIFO_FF (1 << 24) |
| |
| #define | FDCAN_RXFIFO_RFL (1 << 25) |
| |
| #define | FDCAN_RXF0S_F0FL_SHIFT FDCAN_RXFIFO_FL_SHIFT |
| | F0FL[3:0]: Fill level of Rx FIFO 0. More...
|
| |
| #define | FDCAN_RXF0S_F0FL_MASK FDCAN_RXFIFO_FL_MASK |
| |
| #define | FDCAN_RXF0S_F0GI_SHIFT FDCAN_RXFIFO_GI_SHIFT |
| | F0GI[1:0]: Get index of Rx FIFO 0. More...
|
| |
| #define | FDCAN_RXF0S_F0GI_MASK FDCAN_RXFIFO_GI_MASK |
| |
| #define | FDCAN_RXF0S_F0PI_SHIFT FDCAN_RXFIFO_PI_SHIFT |
| | F0PI[1:0]: Put index of Rx FIFO 0. More...
|
| |
| #define | FDCAN_RXF0S_F0PI_MASK FDCAN_RXFIFO_PI_MASK |
| |
| #define | FDCAN_RXF0S_F0F FDCAN_RXFIFO_FF |
| |
| #define | FDCAN_RXF0S_RF0L FDCAN_RXFIFO_RFL |
| |
| #define | FDCAN_RXFIFO_AI_SHIFT 0 |
| | Rx FIFOs acknowledge index. More...
|
| |
| #define | FDCAN_RXF0A_R0AI_SHIFT FDCAN_RXFIFO_AI_SHIFT |
| | R0AI[2:0]: Rx FIFO 0 acknowledge index. More...
|
| |
| #define | FDCAN_RXF0A_R0AI_MASK FDCAN_RXFIFO_AI_MASK |
| |
| #define | FDCAN_RXF1S_F1FL_SHIFT FDCAN_RXFIFO_FL_SHIFT |
| | F1FL[3:1]: Fill level of Rx FIFO 1. More...
|
| |
| #define | FDCAN_RXF1S_F1FL_MASK FDCAN_RXFIFO_FL_MASK |
| |
| #define | FDCAN_RXF1S_F1GI_SHIFT FDCAN_RXFIFO_GI_SHIFT |
| | F1GI[1:1]: Get index of Rx FIFO 1. More...
|
| |
| #define | FDCAN_RXF1S_F1GI_MASK FDCAN_RXFIFO_GI_MASK |
| |
| #define | FDCAN_RXF1S_F1PI_SHIFT FDCAN_RXFIFO_PI_SHIFT |
| | F1PI[1:1]: Put index of Rx FIFO 1. More...
|
| |
| #define | FDCAN_RXF1S_F1PI_MASK FDCAN_RXFIFO_PI_MASK |
| |
| #define | FDCAN_RXF1S_F1F FDCAN_RXFIFO_FF |
| |
| #define | FDCAN_RXF1S_RF1L FDCAN_RXFIFO_RFL |
| |
| #define | FDCAN_RXF1A_R1AI_SHIFT FDCAN_RXFIFO_AI_SHIFT |
| | R1AI[2:0]: Rx FIFO 1 acknowledge index. More...
|
| |
| #define | FDCAN_RXF1A_R1AI_MASK FDCAN_RXFIFO_AI_MASK |
| |
| #define | FDCAN_TXBC_TFQM (1 << 24) |
| |
| #define | FDCAN_TXFQS_TFFL_SHIFT 0 |
| | TFFL[2:0]: Tx FIFO free level. More...
|
| |
| #define | FDCAN_TXFQS_TFGI_SHIFT 8 |
| | TFGI[1:0]: Tx FIFO get index. More...
|
| |
| #define | FDCAN_TXFQS_TFQPI_SHIFT 16 |
| | TFQPI[1:0]: Tx FIFO put index. More...
|
| |
| #define | FDCAN_TXFQS_TFQF (1 << 21) |
| |
| #define | FDCAN_TXEFS_EFFL_SHIFT 0 |
| | EFFL[2:0]: Event FIFO fill level. More...
|
| |
| #define | FDCAN_TXEFS_EFGI_SHIFT 8 |
| | EFG[1:0]: Event FIFO get index. More...
|
| |
| #define | FDCAN_TXEFS_EFPI_SHIFT 16 |
| | EFPI[1:0]: Event FIFO put index. More...
|
| |
| #define | FDCAN_TXEFS_EFF (1 << 24) |
| |
| #define | FDCAN_TXEFS_TEF (1 << 25) |
| |
| #define | FDCAN_TXEFA_EFAI_SHIFT 0 |
| | EFAI[1:0]: Event FIFO acknowledge index. More...
|
| |
| #define | FDCAN_TXEFA_EFAI_MASK 0x3 |
| |
| #define | FDCAN_SFT_SHIFT 30 |
| |
| #define | FDCAN_SFT_MASK 0x3 |
| |
| #define | FDCAN_SFEC_SHIFT 27 |
| |
| #define | FDCAN_SFEC_MASK 0x7 |
| |
| #define | FDCAN_SFID1_SHIFT 16 |
| |
| #define | FDCAN_SFID1_MASK 0x7FF |
| |
| #define | FDCAN_SFID2_SHIFT 0 |
| |
| #define | FDCAN_SFID2_MASK 0x7FF |
| |
| #define | FDCAN_EFEC_SHIFT 29 |
| |
| #define | FDCAN_EFEC_MASK 0x7 |
| |
| #define | FDCAN_EFID1_SHIFT 0 |
| |
| #define | FDCAN_EFID1_MASK 0x1FFFFFFF |
| |
| #define | FDCAN_EFT_SHIFT 30 |
| |
| #define | FDCAN_EFT_MASK 0x3 |
| |
| #define | FDCAN_EFID2_SHIFT 0 |
| |
| #define | FDCAN_EFID2_MASK 0x1FFFFFFF |
| |
| #define | FDCAN_FIFO_EID_SHIFT 0 |
| |
| #define | FDCAN_FIFO_EID_MASK 0x1FFFFFFF |
| |
| #define | FDCAN_FIFO_SID_SHIFT 18 |
| |
| #define | FDCAN_FIFO_SID_MASK 0x7FF |
| |
| #define | FDCAN_FIFO_DLC_SHIFT 16 |
| |
| #define | FDCAN_FIFO_DLC_MASK 0xF |
| |
| #define | FDCAN_FIFO_MM_SHIFT 24 |
| |
| #define | FDCAN_FIFO_MM_MASK 0xFF |
| |
| #define | FDCAN_FIFO_ANMF (1 << 31) |
| |
| #define | FDCAN_FIFO_FIDX_SHIFT 24 |
| |
| #define | FDCAN_FIFO_FIDX_MASK 0x7F |
| |
| #define | FDCAN_FIFO_RXTS_SHIFT 0 |
| |
| #define | FDCAN_FIFO_RXTS_MASK 0xFFFF |
| |
1.9.4