Defined Constants and Types for the STM32G4xx Power Control
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Defined Constants and Types for the STM32G4xx Power Control
- Version
- 1.0.0
- Author
- © 2016 Benjamin Levine benja.nosp@m.min@.nosp@m.jesco.nosp@m..kar.nosp@m.oo.co.nosp@m..uk
-
© 2019 Guillaume Revaillot g.rev.nosp@m.aill.nosp@m.ot@gm.nosp@m.ail..nosp@m.com
-
© 2020 Ben Brewer ben.b.nosp@m.rewe.nosp@m.r@cod.nosp@m.ethi.nosp@m.nk.co.nosp@m..uk
- Date
- 29 July 2020
LGPL License Terms libopencm3 License
◆ PWR_CR1
◆ PWR_CR1_DBP
| #define PWR_CR1_DBP (1 << 8) |
◆ PWR_CR1_LPMS_MASK
| #define PWR_CR1_LPMS_MASK 0x07 |
◆ PWR_CR1_LPMS_SHIFT
| #define PWR_CR1_LPMS_SHIFT 0 |
◆ PWR_CR1_LPMS_SHUTDOWN
| #define PWR_CR1_LPMS_SHUTDOWN 4 |
◆ PWR_CR1_LPMS_STANDBY
| #define PWR_CR1_LPMS_STANDBY 3 |
◆ PWR_CR1_LPMS_STOP_0
| #define PWR_CR1_LPMS_STOP_0 0 |
◆ PWR_CR1_LPMS_STOP_1
| #define PWR_CR1_LPMS_STOP_1 1 |
◆ PWR_CR1_LPMS_STOP_2
| #define PWR_CR1_LPMS_STOP_2 2 |
◆ PWR_CR1_LPR
| #define PWR_CR1_LPR (1 << 14) |
◆ PWR_CR1_VOS_MASK
| #define PWR_CR1_VOS_MASK 0x3 |
◆ PWR_CR1_VOS_RANGE_1
| #define PWR_CR1_VOS_RANGE_1 1 |
◆ PWR_CR1_VOS_RANGE_2
| #define PWR_CR1_VOS_RANGE_2 2 |
◆ PWR_CR1_VOS_SHIFT
| #define PWR_CR1_VOS_SHIFT 9 |
◆ PWR_CR2
◆ PWR_CR2_PLS_MASK
| #define PWR_CR2_PLS_MASK 0x07 |
◆ PWR_CR2_PLS_SHIFT
| #define PWR_CR2_PLS_SHIFT 1 |
◆ PWR_CR2_PVDE
| #define PWR_CR2_PVDE (1 << 0) |
◆ PWR_CR2_PVMEN1
| #define PWR_CR2_PVMEN1 (1 << 6) |
◆ PWR_CR2_PVMEN2
| #define PWR_CR2_PVMEN2 (1 << 7) |
◆ PWR_CR3
◆ PWR_CR3_APC
| #define PWR_CR3_APC (1 << 10) |
◆ PWR_CR3_EIWUL
| #define PWR_CR3_EIWUL (1 << 15) |
◆ PWR_CR3_EWUP1
| #define PWR_CR3_EWUP1 (1 << 0) |
◆ PWR_CR3_EWUP2
| #define PWR_CR3_EWUP2 (1 << 1) |
◆ PWR_CR3_EWUP3
| #define PWR_CR3_EWUP3 (1 << 2) |
◆ PWR_CR3_EWUP4
| #define PWR_CR3_EWUP4 (1 << 3) |
◆ PWR_CR3_EWUP5
| #define PWR_CR3_EWUP5 (1 << 4) |
◆ PWR_CR3_RRS
| #define PWR_CR3_RRS (1 << 8) |
◆ PWR_CR3_UCPD1_DBDIS
| #define PWR_CR3_UCPD1_DBDIS (1 << 14) |
◆ PWR_CR3_UCPD1_STDBY
| #define PWR_CR3_UCPD1_STDBY (1 << 13) |
◆ PWR_CR4
◆ PWR_CR4_VBE
| #define PWR_CR4_VBE (1 << 8) |
◆ PWR_CR4_VBRS
| #define PWR_CR4_VBRS (1 << 9) |
◆ PWR_CR4_WP1
| #define PWR_CR4_WP1 (1 << 0) |
◆ PWR_CR4_WP2
| #define PWR_CR4_WP2 (1 << 1) |
◆ PWR_CR4_WP3
| #define PWR_CR4_WP3 (1 << 2) |
◆ PWR_CR4_WP4
| #define PWR_CR4_WP4 (1 << 3) |
◆ PWR_CR4_WP5
| #define PWR_CR4_WP5 (1 << 4) |
◆ PWR_CR5
◆ PWR_CR5_R1MODE
◆ PWR_CR5_R1MODE_BOOST
| #define PWR_CR5_R1MODE_BOOST 0 |
◆ PWR_CR5_R1MODE_MASK
| #define PWR_CR5_R1MODE_MASK 0x1 |
◆ PWR_CR5_R1MODE_NORMAL
| #define PWR_CR5_R1MODE_NORMAL 1 |
◆ PWR_CR5_R1MODE_SHIFT
| #define PWR_CR5_R1MODE_SHIFT 8 |
◆ PWR_PDCR
| #define PWR_PDCR |
( |
|
pwr_port | ) |
MMIO32((pwr_port) + 0x04) |
◆ PWR_PORT_A
◆ PWR_PORT_B
◆ PWR_PORT_C
◆ PWR_PORT_D
◆ PWR_PORT_E
◆ PWR_PORT_F
◆ PWR_PORT_G
◆ PWR_PUCR
| #define PWR_PUCR |
( |
|
pwr_port | ) |
MMIO32((pwr_port) + 0x00) |
◆ PWR_SCR
◆ PWR_SCR_CSBF
| #define PWR_SCR_CSBF (1 << 8) |
◆ PWR_SCR_CWUF1
| #define PWR_SCR_CWUF1 (1 << 0) |
◆ PWR_SCR_CWUF2
| #define PWR_SCR_CWUF2 (1 << 1) |
◆ PWR_SCR_CWUF3
| #define PWR_SCR_CWUF3 (1 << 2) |
◆ PWR_SCR_CWUF4
| #define PWR_SCR_CWUF4 (1 << 3) |
◆ PWR_SCR_CWUF5
| #define PWR_SCR_CWUF5 (1 << 4) |
◆ PWR_SR1
◆ PWR_SR1_SBF
| #define PWR_SR1_SBF (1 << 8) |
◆ PWR_SR1_WUF1
| #define PWR_SR1_WUF1 (1 << 0) |
◆ PWR_SR1_WUF2
| #define PWR_SR1_WUF2 (1 << 1) |
◆ PWR_SR1_WUF3
| #define PWR_SR1_WUF3 (1 << 2) |
◆ PWR_SR1_WUF4
| #define PWR_SR1_WUF4 (1 << 3) |
◆ PWR_SR1_WUF5
| #define PWR_SR1_WUF5 (1 << 4) |
◆ PWR_SR1_WUFI
| #define PWR_SR1_WUFI (1 << 15) |
◆ PWR_SR2
◆ PWR_SR2_PVDO
| #define PWR_SR2_PVDO (1 << 11) |
◆ PWR_SR2_PVMO1
| #define PWR_SR2_PVMO1 (1 << 14) |
◆ PWR_SR2_PVMO2
| #define PWR_SR2_PVMO2 (1 << 15) |
◆ PWR_SR2_REGLPF
| #define PWR_SR2_REGLPF (1 << 9) |
◆ PWR_SR2_REGLPS
| #define PWR_SR2_REGLPS (1 << 8) |
◆ PWR_SR2_VOSF
| #define PWR_SR2_VOSF (1 << 10) |
◆ pwr_vos_scale
| Enumerator |
|---|
| PWR_SCALE1 | |
| PWR_SCALE2 | |
Definition at line 173 of file g4/pwr.h.
◆ pwr_disable_backup_domain_write_protect()
| void pwr_disable_backup_domain_write_protect |
( |
void |
| ) |
|
Disable Backup Domain Write Protection.
This allows backup domain registers to be changed. These registers are write protected after a reset.
Definition at line 57 of file pwr.c.
References PWR_CR1, and PWR_CR1_DBP.
◆ pwr_disable_boost()
| void pwr_disable_boost |
( |
void |
| ) |
|
◆ pwr_disable_power_voltage_detect()
| void pwr_disable_power_voltage_detect |
( |
void |
| ) |
|
Disable Power Voltage Detector.
Definition at line 100 of file pwr.c.
References PWR_CR2.
◆ pwr_enable_backup_domain_write_protect()
| void pwr_enable_backup_domain_write_protect |
( |
void |
| ) |
|
Re-enable Backup Domain Write Protection.
This protects backup domain registers from inadvertent change.
Definition at line 66 of file pwr.c.
References PWR_CR1.
◆ pwr_enable_boost()
| void pwr_enable_boost |
( |
void |
| ) |
|
◆ pwr_enable_power_voltage_detect()
| void pwr_enable_power_voltage_detect |
( |
uint32_t |
pvd_level | ) |
|
◆ pwr_set_low_power_mode_selection()
| void pwr_set_low_power_mode_selection |
( |
uint32_t |
lpms | ) |
|
◆ pwr_set_vos_scale()
