CAN Bus Timing 1 Register
CAN Bus Timing 1 Register bit definitions. More...
Collaboration diagram for CAN Bus Timing 1 Register:
Macros | |
| #define | CAN_BTR1_TSEG1_MASK (0x0F) |
| #define | CAN_BTR1_TSEG1_SHIFT 24 |
| #define | CAN_BTR1_TSEG1(val) (((val) & CAN_BTR1_TSEG1_MASK) << CAN_BTR1_TSEG1_SHIFT) |
| #define | CAN_BTR1_TSEG2_MASK (0x07) |
| #define | CAN_BTR1_TSEG2_SHIFT 28 |
| #define | CAN_BTR1_TSEG2(val) (((val) & CAN_BTR1_TSEG2_MASK) << CAN_BTR1_TSEG2_SHIFT) |
| #define | CAN_BTR1_SAM BIT31 |
Detailed Description
CAN Bus Timing 1 Register bit definitions.
Macro Definition Documentation
◆ CAN_BTR1_SAM
◆ CAN_BTR1_TSEG1
| #define CAN_BTR1_TSEG1 | ( | val | ) | (((val) & CAN_BTR1_TSEG1_MASK) << CAN_BTR1_TSEG1_SHIFT) |
◆ CAN_BTR1_TSEG1_MASK
◆ CAN_BTR1_TSEG1_SHIFT
◆ CAN_BTR1_TSEG2
| #define CAN_BTR1_TSEG2 | ( | val | ) | (((val) & CAN_BTR1_TSEG2_MASK) << CAN_BTR1_TSEG2_SHIFT) |
