CAN Bus Timing 0 Register.
CAN Bus Timing 0 Register bit definitions. More...
Collaboration diagram for CAN Bus Timing 0 Register.:
Macros | |
| #define | CAN_BTR0_BRP_MASK (0x3F) |
| #define | CAN_BTR0_BRP_SHIFT 16 |
| #define | CAN_BTR0_BRP(val) (((val) & CAN_BTR0_BRP_MASK) << CAN_BTR0_BRP_SHIFT) |
| #define | CAN_BTR0_SJW_MASK (0x03) |
| #define | CAN_BTR0_SJW_SHIFT 22 |
| #define | CAN_BTR0_SJW(val) (((val) & CAN_BTR0_SJW_MASK) << CAN_BTR0_SJW_SHIFT) |
Detailed Description
CAN Bus Timing 0 Register bit definitions.
Macro Definition Documentation
◆ CAN_BTR0_BRP
| #define CAN_BTR0_BRP | ( | val | ) | (((val) & CAN_BTR0_BRP_MASK) << CAN_BTR0_BRP_SHIFT) |
◆ CAN_BTR0_BRP_MASK
◆ CAN_BTR0_BRP_SHIFT
◆ CAN_BTR0_SJW
| #define CAN_BTR0_SJW | ( | val | ) | (((val) & CAN_BTR0_SJW_MASK) << CAN_BTR0_SJW_SHIFT) |
