Memory Controller Defines
Memory Controller definitions for the Qorvo PAC55xx series of microcontrollers. More...
Collaboration diagram for Memory Controller Defines:
Modules | |
| Memory Controller Configuration Register | |
| Memory Controller Status Register | |
| Flash Lock/Write Enable Register values | |
| Flash Erase Enable Register values | |
Macros | |
| #define | MEMCTL_FLASHPAGE MMIO32(MEMCTL_BASE + 0x000C) |
| Flash Page Address Register. More... | |
| #define | MEMCTL_SWDUNLOCK MMIO32(MEMCTL_BASE + 0x0010) |
| SWD Unlock Register. More... | |
Detailed Description
Memory Controller definitions for the Qorvo PAC55xx series of microcontrollers.
- Date
- 17 Mar 2020
Definitions in this file come from the PAC55XX Family User Guide Rev 1.23 by Active-Semi dated November 19, 2019.
Macro Definition Documentation
◆ MEMCTL_FLASHPAGE
| #define MEMCTL_FLASHPAGE MMIO32(MEMCTL_BASE + 0x000C) |
◆ MEMCTL_SWDUNLOCK
| #define MEMCTL_SWDUNLOCK MMIO32(MEMCTL_BASE + 0x0010) |
