VCO Division factor P for PLLPCLK clock output [2..32]. More...
Collaboration diagram for PLLP:
Macros | |
| #define | RCC_PLLCFGR_PLLP_DIV(x) ((x)-1) |
Detailed Description
VCO Division factor P for PLLPCLK clock output [2..32].
Frequency must not exceed 122mhz in voltage range 1, or 40mhz in range 2
- See also
- PLLP
