CHSELR ADC Channel Selection register
Collaboration diagram for CHSELR ADC Channel Selection register:
Macros | |
| #define | ADC_CHSELR_MAX_CHANNELS 18 |
| ADC_CHSELR_MAX_CHANNELS Maximum number of channel in regular sequence. More... | |
| #define | ADC_CHSELR_MAX_SQS 8 |
| ADC_CHSELR_MAX_SQ_CHANNELS Maximum number of sequences in fully configurable mode. More... | |
| #define | ADC_CHSELR_SQS_MAX_CHANNEL 14 |
| ADC_CHSELR_SQS_MAX_CHANNEL Maximum channel number in a fully configuralbe sequence. More... | |
| #define | ADC_CHSELR_SQx_MASK 0xf |
| #define | ADC_CHSELR_SQx_SHIFT(seqnum) (4 * ((seqnum)-1)) |
| #define | ADC_CHSELR_SQx(seqnum, value) ((value) << ADC_CHSELR_SQx_SHIFT(seqnum)) |
| ADC_CHSELR_SQx Xth conversion of ADC sequence channel number value. More... | |
| #define | ADC_CHSELR_SQx_EOS 0xf |
| ADC_CHSELR_SQx_EOS End of Sequence. More... | |
| #define | ADC_CHSELR_CHSEL(x) (1 << (x)) |
Detailed Description
Macro Definition Documentation
◆ ADC_CHSELR_CHSEL
| #define ADC_CHSELR_CHSEL | ( | x | ) | (1 << (x)) |
Definition at line 68 of file adc_common_v2_single.h.
◆ ADC_CHSELR_MAX_CHANNELS
| #define ADC_CHSELR_MAX_CHANNELS 18 |
◆ ADC_CHSELR_MAX_SQS
| #define ADC_CHSELR_MAX_SQS 8 |
◆ ADC_CHSELR_SQS_MAX_CHANNEL
| #define ADC_CHSELR_SQS_MAX_CHANNEL 14 |
◆ ADC_CHSELR_SQx
| #define ADC_CHSELR_SQx | ( | seqnum, | |
| value | |||
| ) | ((value) << ADC_CHSELR_SQx_SHIFT(seqnum)) |
◆ ADC_CHSELR_SQx_EOS
| #define ADC_CHSELR_SQx_EOS 0xf |
