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#define | DMAMUX_CxCR_DMAREQ_ID_DMAMUX_REQ_GEN0 1 |
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#define | DMAMUX_CxCR_DMAREQ_ID_DMAMUX_REQ_GEN1 2 |
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#define | DMAMUX_CxCR_DMAREQ_ID_DMAMUX_REQ_GEN2 3 |
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#define | DMAMUX_CxCR_DMAREQ_ID_DMAMUX_REQ_GEN3 4 |
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#define | DMAMUX_CxCR_DMAREQ_ID_ADC 5 |
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#define | DMAMUX_CxCR_DMAREQ_ID_AES_IN 6 |
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#define | DMAMUX_CxCR_DMAREQ_ID_AES_OUT 7 |
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#define | DMAMUX_CxCR_DMAREQ_ID_DAC_Channel1 8 |
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#define | DMAMUX_CxCR_DMAREQ_ID_DAC_Channel2 9 |
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#define | DMAMUX_CxCR_DMAREQ_ID_I2C1_RX 10 |
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#define | DMAMUX_CxCR_DMAREQ_ID_I2C1_TX 11 |
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#define | DMAMUX_CxCR_DMAREQ_ID_I2C2_RX 12 |
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#define | DMAMUX_CxCR_DMAREQ_ID_I2C2_TX 13 |
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#define | DMAMUX_CxCR_DMAREQ_ID_LPUART_RX 14 |
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#define | DMAMUX_CxCR_DMAREQ_ID_LPUART_TX 15 |
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#define | DMAMUX_CxCR_DMAREQ_ID_SPI1_RX 16 |
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#define | DMAMUX_CxCR_DMAREQ_ID_SPI1_TX 17 |
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#define | DMAMUX_CxCR_DMAREQ_ID_SPI2_RX 18 |
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#define | DMAMUX_CxCR_DMAREQ_ID_SPI2_TX 19 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM1_CH1 20 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM1_CH2 21 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM1_CH3 22 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM1_CH4 23 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM1_TRIG_COM 24 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM1_UP 25 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM2_CH1 26 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM2_CH2 27 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM2_CH3 28 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM2_CH4 29 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM2_TRIG 30 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM2_UP 31 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM3_CH1 32 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM3_CH2 33 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM3_CH3 34 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM3_CH4 35 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM3_TRIG 36 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM3_UP 37 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM6_UP 38 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM7_UP 39 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM15_CH1 40 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM15_CH2 41 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM15_TRIG_COM 42 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM15_UP 43 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM16_CH1 44 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM16_TRIG_COM 45 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM16_UP 46 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM17_CH1 47 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM17_TRIG_COM 48 |
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#define | DMAMUX_CxCR_DMAREQ_ID_TIM17_UP 49 |
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#define | DMAMUX_CxCR_DMAREQ_ID_USART1_RX 50 |
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#define | DMAMUX_CxCR_DMAREQ_ID_USART1_TX 51 |
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#define | DMAMUX_CxCR_DMAREQ_ID_USART2_RX 52 |
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#define | DMAMUX_CxCR_DMAREQ_ID_USART2_TX 53 |
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#define | DMAMUX_CxCR_DMAREQ_ID_USART3_RX 54 |
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#define | DMAMUX_CxCR_DMAREQ_ID_USART3_TX 55 |
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#define | DMAMUX_CxCR_DMAREQ_ID_USART4_RX 56 |
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#define | DMAMUX_CxCR_DMAREQ_ID_USART4_TX 57 |
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#define | DMAMUX_CxCR_DMAREQ_ID_UCPD1_RX 58 |
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#define | DMAMUX_CxCR_DMAREQ_ID_UCPD1_TX 59 |
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#define | DMAMUX_CxCR_DMAREQ_ID_UCPD2_RX 60 |
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#define | DMAMUX_CxCR_DMAREQ_ID_UCPD2_TX 61 |
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#define | DMAMUX_CxCR_DMAREQ_ID_RESERVED62 62 |
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#define | DMAMUX_CxCR_DMAREQ_ID_RESERVED63 63 |
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