libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
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Defined Constants and Types for the LPC43xx Configuration Registers More...
Defined Constants and Types for the LPC43xx Configuration Registers
LGPL License Terms libopencm3 License
#define CREG_CREG0_ALARMCTRL | ( | x | ) | ((x) << CREG_CREG0_ALARMCTRL_SHIFT) |
#define CREG_CREG0_ALARMCTRL_MASK (0x3 << CREG_CREG0_ALARMCTRL_SHIFT) |
#define CREG_CREG0_BODLVL1 | ( | x | ) | ((x) << CREG_CREG0_BODLVL1_SHIFT) |
#define CREG_CREG0_BODLVL1_MASK (0x3 << CREG_CREG0_BODLVL1_SHIFT) |
#define CREG_CREG0_BODLVL2 | ( | x | ) | ((x) << CREG_CREG0_BODLVL2_SHIFT) |
#define CREG_CREG0_BODLVL2_MASK (0x3 << CREG_CREG0_BODLVL2_SHIFT) |
#define CREG_CREG0_EN1KHZ (1 << CREG_CREG0_EN1KHZ_SHIFT) |
#define CREG_CREG0_EN32KHZ (1 << CREG_CREG0_EN32KHZ_SHIFT) |
#define CREG_CREG0_PD32KHZ (1 << CREG_CREG0_PD32KHZ_SHIFT) |
#define CREG_CREG0_RESET32KHZ (1 << CREG_CREG0_RESET32KHZ_SHIFT) |
#define CREG_CREG0_SAMPLECTRL | ( | x | ) | ((x) << CREG_CREG0_SAMPLECTRL_SHIFT) |
#define CREG_CREG0_SAMPLECTRL_MASK (0x3 << CREG_CREG0_SAMPLECTRL_SHIFT) |
#define CREG_CREG0_USB0PHY (1 << CREG_CREG0_USB0PHY_SHIFT) |
#define CREG_CREG0_WAKEUP0CTRL | ( | x | ) | ((x) << CREG_CREG0_WAKEUP0CTRL_SHIFT) |
#define CREG_CREG0_WAKEUP0CTRL_MASK (0x3 << CREG_CREG0_WAKEUP0CTRL_SHIFT) |
#define CREG_CREG0_WAKEUP1CTRL | ( | x | ) | ((x) << CREG_CREG0_WAKEUP1CTRL_SHIFT) |
#define CREG_CREG0_WAKEUP1CTRL_MASK (0x3 << CREG_CREG0_WAKEUP1CTRL_SHIFT) |
#define CREG_CREG5_M0APPTAPSEL (1 << CREG_CREG5_M0APPTAPSEL_SHIFT) |
#define CREG_CREG5_M4TAPSEL (1 << CREG_CREG5_M4TAPSEL_SHIFT) |
#define CREG_CREG6_CTOUTCTRL (1 << CREG_CREG6_CTOUTCTRL_SHIFT) |
#define CREG_CREG6_EMC_CLK_SEL (1 << CREG_CREG6_EMC_CLK_SEL_SHIFT) |
#define CREG_CREG6_ETHMODE | ( | x | ) | ((x) << CREG_CREG6_ETHMODE_SHIFT) |
#define CREG_CREG6_ETHMODE_MASK (0x7 << CREG_CREG6_ETHMODE_SHIFT) |
#define CREG_CREG6_I2S0_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT) |
#define CREG_CREG6_I2S0_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT) |
#define CREG_CREG6_I2S1_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT) |
#define CREG_CREG6_I2S1_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER0 | ( | x | ) | ((x) << CREG_DMAMUX_DMAMUXPER0_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER0_MASK (0x3 << CREG_DMAMUX_DMAMUXPER0_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER1 | ( | x | ) | ((x) << CREG_DMAMUX_DMAMUXPER1_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER10 | ( | x | ) | ((x) << CREG_DMAMUX_DMAMUXPER10_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER10_MASK (0x3 << CREG_DMAMUX_DMAMUXPER10_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER11 | ( | x | ) | ((x) << CREG_DMAMUX_DMAMUXPER11_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER11_MASK (0x3 << CREG_DMAMUX_DMAMUXPER11_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER12 | ( | x | ) | ((x) << CREG_DMAMUX_DMAMUXPER12_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER12_MASK (0x3 << CREG_DMAMUX_DMAMUXPER12_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER13 | ( | x | ) | ((x) << CREG_DMAMUX_DMAMUXPER13_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER13_MASK (0x3 << CREG_DMAMUX_DMAMUXPER13_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER14 | ( | x | ) | ((x) << CREG_DMAMUX_DMAMUXPER14_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER14_MASK (0x3 << CREG_DMAMUX_DMAMUXPER14_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER15 | ( | x | ) | ((x) << CREG_DMAMUX_DMAMUXPER15_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER15_MASK (0x3 << CREG_DMAMUX_DMAMUXPER15_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER1_MASK (0x3 << CREG_DMAMUX_DMAMUXPER1_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER2 | ( | x | ) | ((x) << CREG_DMAMUX_DMAMUXPER2_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER2_MASK (0x3 << CREG_DMAMUX_DMAMUXPER2_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER3 | ( | x | ) | ((x) << CREG_DMAMUX_DMAMUXPER3_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER3_MASK (0x3 << CREG_DMAMUX_DMAMUXPER3_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER4 | ( | x | ) | ((x) << CREG_DMAMUX_DMAMUXPER4_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER4_MASK (0x3 << CREG_DMAMUX_DMAMUXPER4_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER5 | ( | x | ) | ((x) << CREG_DMAMUX_DMAMUXPER5_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER5_MASK (0x3 << CREG_DMAMUX_DMAMUXPER5_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER6 | ( | x | ) | ((x) << CREG_DMAMUX_DMAMUXPER6_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER6_MASK (0x3 << CREG_DMAMUX_DMAMUXPER6_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER7 | ( | x | ) | ((x) << CREG_DMAMUX_DMAMUXPER7_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER7_MASK (0x3 << CREG_DMAMUX_DMAMUXPER7_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER8 | ( | x | ) | ((x) << CREG_DMAMUX_DMAMUXPER8_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER8_MASK (0x3 << CREG_DMAMUX_DMAMUXPER8_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER9 | ( | x | ) | ((x) << CREG_DMAMUX_DMAMUXPER9_SHIFT) |
#define CREG_DMAMUX_DMAMUXPER9_MASK (0x3 << CREG_DMAMUX_DMAMUXPER9_SHIFT) |
#define CREG_ETBCFG_ETB (1 << CREG_ETBCFG_ETB_SHIFT) |
#define CREG_FLASHCFGA_FLASHTIM | ( | x | ) | ((x) << CREG_FLASHCFGA_FLASHTIM_SHIFT) |
#define CREG_FLASHCFGA_FLASHTIM_MASK (0xf << CREG_FLASHCFGA_FLASHTIM_SHIFT) |
#define CREG_FLASHCFGA_POW (1 << CREG_FLASHCFGA_POW_SHIFT) |
#define CREG_FLASHCFGB_FLASHTIM | ( | x | ) | ((x) << CREG_FLASHCFGB_FLASHTIM_SHIFT) |
#define CREG_FLASHCFGB_FLASHTIM_MASK (0xf << CREG_FLASHCFGB_FLASHTIM_SHIFT) |
#define CREG_FLASHCFGB_POW (1 << CREG_FLASHCFGB_POW_SHIFT) |
#define CREG_M0APPMEMMAP_M0APPMAP | ( | x | ) | ((x) << CREG_M0APPMEMMAP_M0APPMAP_SHIFT) |
#define CREG_M0APPMEMMAP_M0APPMAP_MASK (0xfffff << CREG_M0APPMEMMAP_M0APPMAP_SHIFT) |
#define CREG_M0TXEVENT_TXEVCLR (1 << CREG_M0TXEVENT_TXEVCLR_SHIFT) |
#define CREG_M4MEMMAP_M4MAP | ( | x | ) | ((x) << CREG_M4MEMMAP_M4MAP_SHIFT) |
#define CREG_M4MEMMAP_M4MAP_MASK (0xfffff << CREG_M4MEMMAP_M4MAP_SHIFT) |
#define CREG_M4TXEVENT_TXEVCLR (1 << CREG_M4TXEVENT_TXEVCLR_SHIFT) |
#define CREG_USB0FLADJ_FLTV | ( | x | ) | ((x) << CREG_USB0FLADJ_FLTV_SHIFT) |
#define CREG_USB0FLADJ_FLTV_MASK (0x3f << CREG_USB0FLADJ_FLTV_SHIFT) |
#define CREG_USB1FLADJ_FLTV | ( | x | ) | ((x) << CREG_USB1FLADJ_FLTV_SHIFT) |
#define CREG_USB1FLADJ_FLTV_MASK (0x3f << CREG_USB1FLADJ_FLTV_SHIFT) |