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#define | CGU_FREQ_MON MMIO32(CGU_BASE + 0x014) |
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#define | CGU_XTAL_OSC_CTRL MMIO32(CGU_BASE + 0x018) |
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#define | CGU_PLL0USB_STAT MMIO32(CGU_BASE + 0x01C) |
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#define | CGU_PLL0USB_CTRL MMIO32(CGU_BASE + 0x020) |
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#define | CGU_PLL0USB_MDIV MMIO32(CGU_BASE + 0x024) |
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#define | CGU_PLL0USB_NP_DIV MMIO32(CGU_BASE + 0x028) |
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#define | CGU_PLL0AUDIO_STAT MMIO32(CGU_BASE + 0x02C) |
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#define | CGU_PLL0AUDIO_CTRL MMIO32(CGU_BASE + 0x030) |
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#define | CGU_PLL0AUDIO_MDIV MMIO32(CGU_BASE + 0x034) |
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#define | CGU_PLL0AUDIO_NP_DIV MMIO32(CGU_BASE + 0x038) |
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#define | CGU_PLLAUDIO_FRAC MMIO32(CGU_BASE + 0x03C) |
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#define | CGU_PLL1_STAT MMIO32(CGU_BASE + 0x040) |
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#define | CGU_PLL1_CTRL MMIO32(CGU_BASE + 0x044) |
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#define | CGU_IDIVA_CTRL MMIO32(CGU_BASE + 0x048) |
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#define | CGU_IDIVB_CTRL MMIO32(CGU_BASE + 0x04C) |
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#define | CGU_IDIVC_CTRL MMIO32(CGU_BASE + 0x050) |
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#define | CGU_IDIVD_CTRL MMIO32(CGU_BASE + 0x054) |
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#define | CGU_IDIVE_CTRL MMIO32(CGU_BASE + 0x058) |
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#define | CGU_BASE_SAFE_CLK MMIO32(CGU_BASE + 0x05C) |
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#define | CGU_BASE_USB0_CLK MMIO32(CGU_BASE + 0x060) |
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#define | CGU_BASE_PERIPH_CLK MMIO32(CGU_BASE + 0x064) |
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#define | CGU_BASE_USB1_CLK MMIO32(CGU_BASE + 0x068) |
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#define | CGU_BASE_M4_CLK MMIO32(CGU_BASE + 0x06C) |
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#define | CGU_BASE_SPIFI_CLK MMIO32(CGU_BASE + 0x070) |
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#define | CGU_BASE_SPI_CLK MMIO32(CGU_BASE + 0x074) |
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#define | CGU_BASE_PHY_RX_CLK MMIO32(CGU_BASE + 0x078) |
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#define | CGU_BASE_PHY_TX_CLK MMIO32(CGU_BASE + 0x07C) |
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#define | CGU_BASE_APB1_CLK MMIO32(CGU_BASE + 0x080) |
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#define | CGU_BASE_APB3_CLK MMIO32(CGU_BASE + 0x084) |
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#define | CGU_BASE_LCD_CLK MMIO32(CGU_BASE + 0x088) |
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#define | CGU_BASE_VADC_CLK MMIO32(CGU_BASE + 0x08C) |
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#define | CGU_BASE_SDIO_CLK MMIO32(CGU_BASE + 0x090) |
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#define | CGU_BASE_SSP0_CLK MMIO32(CGU_BASE + 0x094) |
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#define | CGU_BASE_SSP1_CLK MMIO32(CGU_BASE + 0x098) |
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#define | CGU_BASE_UART0_CLK MMIO32(CGU_BASE + 0x09C) |
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#define | CGU_BASE_UART1_CLK MMIO32(CGU_BASE + 0x0A0) |
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#define | CGU_BASE_UART2_CLK MMIO32(CGU_BASE + 0x0A4) |
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#define | CGU_BASE_UART3_CLK MMIO32(CGU_BASE + 0x0A8) |
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#define | CGU_BASE_OUT_CLK MMIO32(CGU_BASE + 0x0AC) |
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#define | CGU_OUTCLK_21_CTRL MMIO32(CGU_BASE + 0x0B0) |
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#define | CGU_OUTCLK_22_CTRL MMIO32(CGU_BASE + 0x0B4) |
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#define | CGU_OUTCLK_23_CTRL MMIO32(CGU_BASE + 0x0B8) |
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#define | CGU_OUTCLK_24_CTRL MMIO32(CGU_BASE + 0x0BC) |
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#define | CGU_BASE_APLL_CLK MMIO32(CGU_BASE + 0x0C0) |
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#define | CGU_BASE_CGU_OUT0_CLK MMIO32(CGU_BASE + 0x0C4) |
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#define | CGU_BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8) |
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#define | CGU_FREQ_MON_RCNT_SHIFT (0) |
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#define | CGU_FREQ_MON_RCNT_MASK (0x1ff << CGU_FREQ_MON_RCNT_SHIFT) |
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#define | CGU_FREQ_MON_RCNT(x) ((x) << CGU_FREQ_MON_RCNT_SHIFT) |
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#define | CGU_FREQ_MON_FCNT_SHIFT (9) |
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#define | CGU_FREQ_MON_FCNT_MASK (0x3fff << CGU_FREQ_MON_FCNT_SHIFT) |
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#define | CGU_FREQ_MON_FCNT(x) ((x) << CGU_FREQ_MON_FCNT_SHIFT) |
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#define | CGU_FREQ_MON_MEAS_SHIFT (23) |
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#define | CGU_FREQ_MON_MEAS (1 << CGU_FREQ_MON_MEAS_SHIFT) |
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#define | CGU_FREQ_MON_CLK_SEL_SHIFT (24) |
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#define | CGU_FREQ_MON_CLK_SEL_MASK (0x1f << CGU_FREQ_MON_CLK_SEL_SHIFT) |
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#define | CGU_FREQ_MON_CLK_SEL(x) ((x) << CGU_FREQ_MON_CLK_SEL_SHIFT) |
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#define | CGU_XTAL_OSC_CTRL_ENABLE_SHIFT (0) |
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#define | CGU_XTAL_OSC_CTRL_ENABLE (1 << CGU_XTAL_OSC_CTRL_ENABLE_SHIFT) |
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#define | CGU_XTAL_OSC_CTRL_BYPASS_SHIFT (1) |
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#define | CGU_XTAL_OSC_CTRL_BYPASS (1 << CGU_XTAL_OSC_CTRL_BYPASS_SHIFT) |
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#define | CGU_XTAL_OSC_CTRL_HF_SHIFT (2) |
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#define | CGU_XTAL_OSC_CTRL_HF (1 << CGU_XTAL_OSC_CTRL_HF_SHIFT) |
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#define | CGU_PLL0USB_STAT_LOCK_SHIFT (0) |
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#define | CGU_PLL0USB_STAT_LOCK (1 << CGU_PLL0USB_STAT_LOCK_SHIFT) |
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#define | CGU_PLL0USB_STAT_FR_SHIFT (1) |
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#define | CGU_PLL0USB_STAT_FR (1 << CGU_PLL0USB_STAT_FR_SHIFT) |
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#define | CGU_PLL0USB_CTRL_PD_SHIFT (0) |
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#define | CGU_PLL0USB_CTRL_PD (1 << CGU_PLL0USB_CTRL_PD_SHIFT) |
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#define | CGU_PLL0USB_CTRL_BYPASS_SHIFT (1) |
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#define | CGU_PLL0USB_CTRL_BYPASS (1 << CGU_PLL0USB_CTRL_BYPASS_SHIFT) |
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#define | CGU_PLL0USB_CTRL_DIRECTI_SHIFT (2) |
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#define | CGU_PLL0USB_CTRL_DIRECTI (1 << CGU_PLL0USB_CTRL_DIRECTI_SHIFT) |
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#define | CGU_PLL0USB_CTRL_DIRECTO_SHIFT (3) |
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#define | CGU_PLL0USB_CTRL_DIRECTO (1 << CGU_PLL0USB_CTRL_DIRECTO_SHIFT) |
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#define | CGU_PLL0USB_CTRL_CLKEN_SHIFT (4) |
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#define | CGU_PLL0USB_CTRL_CLKEN (1 << CGU_PLL0USB_CTRL_CLKEN_SHIFT) |
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#define | CGU_PLL0USB_CTRL_FRM_SHIFT (6) |
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#define | CGU_PLL0USB_CTRL_FRM (1 << CGU_PLL0USB_CTRL_FRM_SHIFT) |
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#define | CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT (11) |
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#define | CGU_PLL0USB_CTRL_AUTOBLOCK (1 << CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT) |
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#define | CGU_PLL0USB_CTRL_CLK_SEL_SHIFT (24) |
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#define | CGU_PLL0USB_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT) |
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#define | CGU_PLL0USB_CTRL_CLK_SEL(x) ((x) << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT) |
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#define | CGU_PLL0USB_MDIV_MDEC_SHIFT (0) |
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#define | CGU_PLL0USB_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0USB_MDIV_MDEC_SHIFT) |
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#define | CGU_PLL0USB_MDIV_MDEC(x) ((x) << CGU_PLL0USB_MDIV_MDEC_SHIFT) |
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#define | CGU_PLL0USB_MDIV_SELP_SHIFT (17) |
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#define | CGU_PLL0USB_MDIV_SELP_MASK (0x1f << CGU_PLL0USB_MDIV_SELP_SHIFT) |
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#define | CGU_PLL0USB_MDIV_SELP(x) ((x) << CGU_PLL0USB_MDIV_SELP_SHIFT) |
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#define | CGU_PLL0USB_MDIV_SELI_SHIFT (22) |
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#define | CGU_PLL0USB_MDIV_SELI_MASK (0x3f << CGU_PLL0USB_MDIV_SELI_SHIFT) |
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#define | CGU_PLL0USB_MDIV_SELI(x) ((x) << CGU_PLL0USB_MDIV_SELI_SHIFT) |
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#define | CGU_PLL0USB_MDIV_SELR_SHIFT (28) |
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#define | CGU_PLL0USB_MDIV_SELR_MASK (0xf << CGU_PLL0USB_MDIV_SELR_SHIFT) |
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#define | CGU_PLL0USB_MDIV_SELR(x) ((x) << CGU_PLL0USB_MDIV_SELR_SHIFT) |
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#define | CGU_PLL0USB_NP_DIV_PDEC_SHIFT (0) |
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#define | CGU_PLL0USB_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0USB_NP_DIV_PDEC_SHIFT) |
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#define | CGU_PLL0USB_NP_DIV_PDEC(x) ((x) << CGU_PLL0USB_NP_DIV_PDEC_SHIFT) |
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#define | CGU_PLL0USB_NP_DIV_NDEC_SHIFT (12) |
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#define | CGU_PLL0USB_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0USB_NP_DIV_NDEC_SHIFT) |
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#define | CGU_PLL0USB_NP_DIV_NDEC(x) ((x) << CGU_PLL0USB_NP_DIV_NDEC_SHIFT) |
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#define | CGU_PLL0AUDIO_STAT_LOCK_SHIFT (0) |
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#define | CGU_PLL0AUDIO_STAT_LOCK (1 << CGU_PLL0AUDIO_STAT_LOCK_SHIFT) |
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#define | CGU_PLL0AUDIO_STAT_FR_SHIFT (1) |
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#define | CGU_PLL0AUDIO_STAT_FR (1 << CGU_PLL0AUDIO_STAT_FR_SHIFT) |
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#define | CGU_PLL0AUDIO_CTRL_PD_SHIFT (0) |
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#define | CGU_PLL0AUDIO_CTRL_PD (1 << CGU_PLL0AUDIO_CTRL_PD_SHIFT) |
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#define | CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT (1) |
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#define | CGU_PLL0AUDIO_CTRL_BYPASS (1 << CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT) |
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#define | CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT (2) |
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#define | CGU_PLL0AUDIO_CTRL_DIRECTI (1 << CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT) |
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#define | CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT (3) |
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#define | CGU_PLL0AUDIO_CTRL_DIRECTO (1 << CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT) |
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#define | CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT (4) |
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#define | CGU_PLL0AUDIO_CTRL_CLKEN (1 << CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT) |
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#define | CGU_PLL0AUDIO_CTRL_FRM_SHIFT (6) |
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#define | CGU_PLL0AUDIO_CTRL_FRM (1 << CGU_PLL0AUDIO_CTRL_FRM_SHIFT) |
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#define | CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT (11) |
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#define | CGU_PLL0AUDIO_CTRL_AUTOBLOCK (1 << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT) |
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#define | CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT (12) |
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#define | CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ (1 << CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT) |
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#define | CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT (13) |
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#define | CGU_PLL0AUDIO_CTRL_SEL_EXT (1 << CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT) |
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#define | CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT (14) |
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#define | CGU_PLL0AUDIO_CTRL_MOD_PD (1 << CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT) |
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#define | CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT (24) |
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#define | CGU_PLL0AUDIO_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT) |
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#define | CGU_PLL0AUDIO_CTRL_CLK_SEL(x) ((x) << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT) |
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#define | CGU_PLL0AUDIO_MDIV_MDEC_SHIFT (0) |
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#define | CGU_PLL0AUDIO_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT) |
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#define | CGU_PLL0AUDIO_MDIV_MDEC(x) ((x) << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT) |
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#define | CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT (0) |
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#define | CGU_PLL0AUDIO_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT) |
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#define | CGU_PLL0AUDIO_NP_DIV_PDEC(x) ((x) << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT) |
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#define | CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT (12) |
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#define | CGU_PLL0AUDIO_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT) |
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#define | CGU_PLL0AUDIO_NP_DIV_NDEC(x) ((x) << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT) |
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#define | CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT (0) |
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#define | CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_MASK (0x3fffff << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT) |
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#define | CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL(x) ((x) << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT) |
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#define | CGU_PLL1_STAT_LOCK_SHIFT (0) |
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#define | CGU_PLL1_STAT_LOCK (1 << CGU_PLL1_STAT_LOCK_SHIFT) |
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#define | CGU_PLL1_CTRL_PD_SHIFT (0) |
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#define | CGU_PLL1_CTRL_PD (1 << CGU_PLL1_CTRL_PD_SHIFT) |
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#define | CGU_PLL1_CTRL_BYPASS_SHIFT (1) |
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#define | CGU_PLL1_CTRL_BYPASS (1 << CGU_PLL1_CTRL_BYPASS_SHIFT) |
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#define | CGU_PLL1_CTRL_FBSEL_SHIFT (6) |
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#define | CGU_PLL1_CTRL_FBSEL (1 << CGU_PLL1_CTRL_FBSEL_SHIFT) |
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#define | CGU_PLL1_CTRL_DIRECT_SHIFT (7) |
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#define | CGU_PLL1_CTRL_DIRECT (1 << CGU_PLL1_CTRL_DIRECT_SHIFT) |
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#define | CGU_PLL1_CTRL_PSEL_SHIFT (8) |
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#define | CGU_PLL1_CTRL_PSEL_MASK (0x3 << CGU_PLL1_CTRL_PSEL_SHIFT) |
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#define | CGU_PLL1_CTRL_PSEL(x) ((x) << CGU_PLL1_CTRL_PSEL_SHIFT) |
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#define | CGU_PLL1_CTRL_AUTOBLOCK_SHIFT (11) |
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#define | CGU_PLL1_CTRL_AUTOBLOCK (1 << CGU_PLL1_CTRL_AUTOBLOCK_SHIFT) |
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#define | CGU_PLL1_CTRL_NSEL_SHIFT (12) |
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#define | CGU_PLL1_CTRL_NSEL_MASK (0x3 << CGU_PLL1_CTRL_NSEL_SHIFT) |
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#define | CGU_PLL1_CTRL_NSEL(x) ((x) << CGU_PLL1_CTRL_NSEL_SHIFT) |
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#define | CGU_PLL1_CTRL_MSEL_SHIFT (16) |
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#define | CGU_PLL1_CTRL_MSEL_MASK (0xff << CGU_PLL1_CTRL_MSEL_SHIFT) |
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#define | CGU_PLL1_CTRL_MSEL(x) ((x) << CGU_PLL1_CTRL_MSEL_SHIFT) |
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#define | CGU_PLL1_CTRL_CLK_SEL_SHIFT (24) |
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#define | CGU_PLL1_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL1_CTRL_CLK_SEL_SHIFT) |
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#define | CGU_PLL1_CTRL_CLK_SEL(x) ((x) << CGU_PLL1_CTRL_CLK_SEL_SHIFT) |
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#define | CGU_IDIVA_CTRL_PD_SHIFT (0) |
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#define | CGU_IDIVA_CTRL_PD (1 << CGU_IDIVA_CTRL_PD_SHIFT) |
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#define | CGU_IDIVA_CTRL_IDIV_SHIFT (2) |
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#define | CGU_IDIVA_CTRL_IDIV_MASK (0x3 << CGU_IDIVA_CTRL_IDIV_SHIFT) |
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#define | CGU_IDIVA_CTRL_IDIV(x) ((x) << CGU_IDIVA_CTRL_IDIV_SHIFT) |
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#define | CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT (11) |
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#define | CGU_IDIVA_CTRL_AUTOBLOCK (1 << CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT) |
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#define | CGU_IDIVA_CTRL_CLK_SEL_SHIFT (24) |
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#define | CGU_IDIVA_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVA_CTRL_CLK_SEL_SHIFT) |
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#define | CGU_IDIVA_CTRL_CLK_SEL(x) ((x) << CGU_IDIVA_CTRL_CLK_SEL_SHIFT) |
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#define | CGU_IDIVB_CTRL_PD_SHIFT (0) |
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#define | CGU_IDIVB_CTRL_PD (1 << CGU_IDIVB_CTRL_PD_SHIFT) |
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#define | CGU_IDIVB_CTRL_IDIV_SHIFT (2) |
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#define | CGU_IDIVB_CTRL_IDIV_MASK (0xf << CGU_IDIVB_CTRL_IDIV_SHIFT) |
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#define | CGU_IDIVB_CTRL_IDIV(x) ((x) << CGU_IDIVB_CTRL_IDIV_SHIFT) |
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#define | CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT (11) |
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#define | CGU_IDIVB_CTRL_AUTOBLOCK (1 << CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT) |
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#define | CGU_IDIVB_CTRL_CLK_SEL_SHIFT (24) |
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#define | CGU_IDIVB_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVB_CTRL_CLK_SEL_SHIFT) |
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#define | CGU_IDIVB_CTRL_CLK_SEL(x) ((x) << CGU_IDIVB_CTRL_CLK_SEL_SHIFT) |
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#define | CGU_IDIVC_CTRL_PD_SHIFT (0) |
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#define | CGU_IDIVC_CTRL_PD (1 << CGU_IDIVC_CTRL_PD_SHIFT) |
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#define | CGU_IDIVC_CTRL_IDIV_SHIFT (2) |
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#define | CGU_IDIVC_CTRL_IDIV_MASK (0xf << CGU_IDIVC_CTRL_IDIV_SHIFT) |
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#define | CGU_IDIVC_CTRL_IDIV(x) ((x) << CGU_IDIVC_CTRL_IDIV_SHIFT) |
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#define | CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT (11) |
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#define | CGU_IDIVC_CTRL_AUTOBLOCK (1 << CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT) |
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#define | CGU_IDIVC_CTRL_CLK_SEL_SHIFT (24) |
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#define | CGU_IDIVC_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVC_CTRL_CLK_SEL_SHIFT) |
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#define | CGU_IDIVC_CTRL_CLK_SEL(x) ((x) << CGU_IDIVC_CTRL_CLK_SEL_SHIFT) |
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#define | CGU_IDIVD_CTRL_PD_SHIFT (0) |
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#define | CGU_IDIVD_CTRL_PD (1 << CGU_IDIVD_CTRL_PD_SHIFT) |
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#define | CGU_IDIVD_CTRL_IDIV_SHIFT (2) |
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#define | CGU_IDIVD_CTRL_IDIV_MASK (0xf << CGU_IDIVD_CTRL_IDIV_SHIFT) |
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#define | CGU_IDIVD_CTRL_IDIV(x) ((x) << CGU_IDIVD_CTRL_IDIV_SHIFT) |
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#define | CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT (11) |
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#define | CGU_IDIVD_CTRL_AUTOBLOCK (1 << CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT) |
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#define | CGU_IDIVD_CTRL_CLK_SEL_SHIFT (24) |
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#define | CGU_IDIVD_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVD_CTRL_CLK_SEL_SHIFT) |
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#define | CGU_IDIVD_CTRL_CLK_SEL(x) ((x) << CGU_IDIVD_CTRL_CLK_SEL_SHIFT) |
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#define | CGU_IDIVE_CTRL_PD_SHIFT (0) |
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#define | CGU_IDIVE_CTRL_PD (1 << CGU_IDIVE_CTRL_PD_SHIFT) |
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#define | CGU_IDIVE_CTRL_IDIV_SHIFT (2) |
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#define | CGU_IDIVE_CTRL_IDIV_MASK (0xff << CGU_IDIVE_CTRL_IDIV_SHIFT) |
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#define | CGU_IDIVE_CTRL_IDIV(x) ((x) << CGU_IDIVE_CTRL_IDIV_SHIFT) |
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#define | CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT (11) |
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#define | CGU_IDIVE_CTRL_AUTOBLOCK (1 << CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT) |
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#define | CGU_IDIVE_CTRL_CLK_SEL_SHIFT (24) |
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#define | CGU_IDIVE_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVE_CTRL_CLK_SEL_SHIFT) |
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#define | CGU_IDIVE_CTRL_CLK_SEL(x) ((x) << CGU_IDIVE_CTRL_CLK_SEL_SHIFT) |
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#define | CGU_BASE_SAFE_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_SAFE_CLK_PD (1 << CGU_BASE_SAFE_CLK_PD_SHIFT) |
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#define | CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_SAFE_CLK_AUTOBLOCK (1 << CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_SAFE_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_SAFE_CLK_CLK_SEL(x) ((x) << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_USB0_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_USB0_CLK_PD (1 << CGU_BASE_USB0_CLK_PD_SHIFT) |
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#define | CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_USB0_CLK_AUTOBLOCK (1 << CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_USB0_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_USB0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_USB0_CLK_CLK_SEL(x) ((x) << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_PERIPH_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_PERIPH_CLK_PD (1 << CGU_BASE_PERIPH_CLK_PD_SHIFT) |
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#define | CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_PERIPH_CLK_AUTOBLOCK (1 << CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_PERIPH_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_PERIPH_CLK_CLK_SEL(x) ((x) << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_USB1_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_USB1_CLK_PD (1 << CGU_BASE_USB1_CLK_PD_SHIFT) |
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#define | CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_USB1_CLK_AUTOBLOCK (1 << CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_USB1_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_USB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_USB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_M4_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_M4_CLK_PD (1 << CGU_BASE_M4_CLK_PD_SHIFT) |
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#define | CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_M4_CLK_AUTOBLOCK (1 << CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_M4_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_M4_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_M4_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_M4_CLK_CLK_SEL(x) ((x) << CGU_BASE_M4_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_SPIFI_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_SPIFI_CLK_PD (1 << CGU_BASE_SPIFI_CLK_PD_SHIFT) |
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#define | CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_SPIFI_CLK_AUTOBLOCK (1 << CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_SPIFI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_SPIFI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_SPI_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_SPI_CLK_PD (1 << CGU_BASE_SPI_CLK_PD_SHIFT) |
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#define | CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_SPI_CLK_AUTOBLOCK (1 << CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_SPI_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_SPI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_SPI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_PHY_RX_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_PHY_RX_CLK_PD (1 << CGU_BASE_PHY_RX_CLK_PD_SHIFT) |
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#define | CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_PHY_RX_CLK_AUTOBLOCK (1 << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_PHY_RX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_PHY_RX_CLK_CLK_SEL(x) ((x) << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_PHY_TX_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_PHY_TX_CLK_PD (1 << CGU_BASE_PHY_TX_CLK_PD_SHIFT) |
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#define | CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_PHY_TX_CLK_AUTOBLOCK (1 << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_PHY_TX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_PHY_TX_CLK_CLK_SEL(x) ((x) << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_APB1_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_APB1_CLK_PD (1 << CGU_BASE_APB1_CLK_PD_SHIFT) |
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#define | CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_APB1_CLK_AUTOBLOCK (1 << CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_APB1_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_APB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_APB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_APB3_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_APB3_CLK_PD (1 << CGU_BASE_APB3_CLK_PD_SHIFT) |
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#define | CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_APB3_CLK_AUTOBLOCK (1 << CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_APB3_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_APB3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_APB3_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_LCD_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_LCD_CLK_PD (1 << CGU_BASE_LCD_CLK_PD_SHIFT) |
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#define | CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_LCD_CLK_AUTOBLOCK (1 << CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_LCD_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_LCD_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_LCD_CLK_CLK_SEL(x) ((x) << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_VADC_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_VADC_CLK_PD (1 << CGU_BASE_VADC_CLK_PD_SHIFT) |
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#define | CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_VADC_CLK_AUTOBLOCK (1 << CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_VADC_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_VADC_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_VADC_CLK_CLK_SEL(x) ((x) << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_SDIO_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_SDIO_CLK_PD (1 << CGU_BASE_SDIO_CLK_PD_SHIFT) |
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#define | CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_SDIO_CLK_AUTOBLOCK (1 << CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_SDIO_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_SDIO_CLK_CLK_SEL(x) ((x) << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_SSP0_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_SSP0_CLK_PD (1 << CGU_BASE_SSP0_CLK_PD_SHIFT) |
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#define | CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_SSP0_CLK_AUTOBLOCK (1 << CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_SSP0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_SSP0_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_SSP1_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_SSP1_CLK_PD (1 << CGU_BASE_SSP1_CLK_PD_SHIFT) |
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#define | CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_SSP1_CLK_AUTOBLOCK (1 << CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_SSP1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_SSP1_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_UART0_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_UART0_CLK_PD (1 << CGU_BASE_UART0_CLK_PD_SHIFT) |
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#define | CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_UART0_CLK_AUTOBLOCK (1 << CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_UART0_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_UART0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_UART0_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_UART1_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_UART1_CLK_PD (1 << CGU_BASE_UART1_CLK_PD_SHIFT) |
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#define | CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_UART1_CLK_AUTOBLOCK (1 << CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_UART1_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_UART1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_UART1_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_UART2_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_UART2_CLK_PD (1 << CGU_BASE_UART2_CLK_PD_SHIFT) |
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#define | CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_UART2_CLK_AUTOBLOCK (1 << CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_UART2_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_UART2_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_UART2_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_UART3_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_UART3_CLK_PD (1 << CGU_BASE_UART3_CLK_PD_SHIFT) |
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#define | CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_UART3_CLK_AUTOBLOCK (1 << CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_UART3_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_UART3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_UART3_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_OUT_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_OUT_CLK_PD (1 << CGU_BASE_OUT_CLK_PD_SHIFT) |
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#define | CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_OUT_CLK_AUTOBLOCK (1 << CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_OUT_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_OUT_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_OUT_CLK_CLK_SEL(x) ((x) << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_APLL_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_APLL_CLK_PD (1 << CGU_BASE_APLL_CLK_PD_SHIFT) |
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#define | CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_APLL_CLK_AUTOBLOCK (1 << CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_APLL_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_APLL_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_APLL_CLK_CLK_SEL(x) ((x) << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_CGU_OUT0_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_CGU_OUT0_CLK_PD (1 << CGU_BASE_CGU_OUT0_CLK_PD_SHIFT) |
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#define | CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK (1 << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_CGU_OUT0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_CGU_OUT0_CLK_CLK_SEL(x) ((x) << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_CGU_OUT1_CLK_PD_SHIFT (0) |
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#define | CGU_BASE_CGU_OUT1_CLK_PD (1 << CGU_BASE_CGU_OUT1_CLK_PD_SHIFT) |
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#define | CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT (11) |
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#define | CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK (1 << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT) |
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#define | CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT (24) |
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#define | CGU_BASE_CGU_OUT1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT) |
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#define | CGU_BASE_CGU_OUT1_CLK_CLK_SEL(x) ((x) << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT) |
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#define | CGU_SRC_32K 0x00 |
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#define | CGU_SRC_IRC 0x01 |
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#define | CGU_SRC_ENET_RX 0x02 |
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#define | CGU_SRC_ENET_TX 0x03 |
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#define | CGU_SRC_GP_CLKIN 0x04 |
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#define | CGU_SRC_XTAL 0x06 |
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#define | CGU_SRC_PLL0USB 0x07 |
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#define | CGU_SRC_PLL0AUDIO 0x08 |
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#define | CGU_SRC_PLL1 0x09 |
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#define | CGU_SRC_IDIVA 0x0C |
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#define | CGU_SRC_IDIVB 0x0D |
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#define | CGU_SRC_IDIVC 0x0E |
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#define | CGU_SRC_IDIVD 0x0F |
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#define | CGU_SRC_IDIVE 0x10 |
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