libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
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Defined Constants and Types for the LPC43xx Clock Generation Unit More...
Defined Constants and Types for the LPC43xx Clock Generation Unit
LGPL License Terms libopencm3 License
#define CGU_BASE_APB1_CLK_AUTOBLOCK (1 << CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_APB1_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_APB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_APB1_CLK_PD (1 << CGU_BASE_APB1_CLK_PD_SHIFT) |
#define CGU_BASE_APB3_CLK_AUTOBLOCK (1 << CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_APB3_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_APB3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_APB3_CLK_PD (1 << CGU_BASE_APB3_CLK_PD_SHIFT) |
#define CGU_BASE_APLL_CLK_AUTOBLOCK (1 << CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_APLL_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_APLL_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_APLL_CLK_PD (1 << CGU_BASE_APLL_CLK_PD_SHIFT) |
#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK (1 << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_CGU_OUT0_CLK_PD (1 << CGU_BASE_CGU_OUT0_CLK_PD_SHIFT) |
#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK (1 << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_CGU_OUT1_CLK_PD (1 << CGU_BASE_CGU_OUT1_CLK_PD_SHIFT) |
#define CGU_BASE_LCD_CLK_AUTOBLOCK (1 << CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_LCD_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_LCD_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_LCD_CLK_PD (1 << CGU_BASE_LCD_CLK_PD_SHIFT) |
#define CGU_BASE_M4_CLK_AUTOBLOCK (1 << CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_M4_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_M4_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_M4_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_M4_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_M4_CLK_PD (1 << CGU_BASE_M4_CLK_PD_SHIFT) |
#define CGU_BASE_OUT_CLK_AUTOBLOCK (1 << CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_OUT_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_OUT_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_OUT_CLK_PD (1 << CGU_BASE_OUT_CLK_PD_SHIFT) |
#define CGU_BASE_PERIPH_CLK_AUTOBLOCK (1 << CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_PERIPH_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_PERIPH_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_PERIPH_CLK_PD (1 << CGU_BASE_PERIPH_CLK_PD_SHIFT) |
#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK (1 << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_PHY_RX_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_PHY_RX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_PHY_RX_CLK_PD (1 << CGU_BASE_PHY_RX_CLK_PD_SHIFT) |
#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK (1 << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_PHY_TX_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_PHY_TX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_PHY_TX_CLK_PD (1 << CGU_BASE_PHY_TX_CLK_PD_SHIFT) |
#define CGU_BASE_SAFE_CLK_AUTOBLOCK (1 << CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_SAFE_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_SAFE_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_SAFE_CLK_PD (1 << CGU_BASE_SAFE_CLK_PD_SHIFT) |
#define CGU_BASE_SDIO_CLK_AUTOBLOCK (1 << CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_SDIO_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_SDIO_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_SDIO_CLK_PD (1 << CGU_BASE_SDIO_CLK_PD_SHIFT) |
#define CGU_BASE_SPI_CLK_AUTOBLOCK (1 << CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_SPI_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_SPI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_SPI_CLK_PD (1 << CGU_BASE_SPI_CLK_PD_SHIFT) |
#define CGU_BASE_SPIFI_CLK_AUTOBLOCK (1 << CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_SPIFI_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_SPIFI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_SPIFI_CLK_PD (1 << CGU_BASE_SPIFI_CLK_PD_SHIFT) |
#define CGU_BASE_SSP0_CLK_AUTOBLOCK (1 << CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_SSP0_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_SSP0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_SSP0_CLK_PD (1 << CGU_BASE_SSP0_CLK_PD_SHIFT) |
#define CGU_BASE_SSP1_CLK_AUTOBLOCK (1 << CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_SSP1_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_SSP1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_SSP1_CLK_PD (1 << CGU_BASE_SSP1_CLK_PD_SHIFT) |
#define CGU_BASE_UART0_CLK_AUTOBLOCK (1 << CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_UART0_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_UART0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_UART0_CLK_PD (1 << CGU_BASE_UART0_CLK_PD_SHIFT) |
#define CGU_BASE_UART1_CLK_AUTOBLOCK (1 << CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_UART1_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_UART1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_UART1_CLK_PD (1 << CGU_BASE_UART1_CLK_PD_SHIFT) |
#define CGU_BASE_UART2_CLK_AUTOBLOCK (1 << CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_UART2_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_UART2_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_UART2_CLK_PD (1 << CGU_BASE_UART2_CLK_PD_SHIFT) |
#define CGU_BASE_UART3_CLK_AUTOBLOCK (1 << CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_UART3_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_UART3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_UART3_CLK_PD (1 << CGU_BASE_UART3_CLK_PD_SHIFT) |
#define CGU_BASE_USB0_CLK_AUTOBLOCK (1 << CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_USB0_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_USB0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_USB0_CLK_PD (1 << CGU_BASE_USB0_CLK_PD_SHIFT) |
#define CGU_BASE_USB1_CLK_AUTOBLOCK (1 << CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_USB1_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_USB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_USB1_CLK_PD (1 << CGU_BASE_USB1_CLK_PD_SHIFT) |
#define CGU_BASE_VADC_CLK_AUTOBLOCK (1 << CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT) |
#define CGU_BASE_VADC_CLK_CLK_SEL | ( | x | ) | ((x) << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_VADC_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT) |
#define CGU_BASE_VADC_CLK_PD (1 << CGU_BASE_VADC_CLK_PD_SHIFT) |
#define CGU_FREQ_MON_CLK_SEL | ( | x | ) | ((x) << CGU_FREQ_MON_CLK_SEL_SHIFT) |
#define CGU_FREQ_MON_CLK_SEL_MASK (0x1f << CGU_FREQ_MON_CLK_SEL_SHIFT) |
#define CGU_FREQ_MON_FCNT | ( | x | ) | ((x) << CGU_FREQ_MON_FCNT_SHIFT) |
#define CGU_FREQ_MON_FCNT_MASK (0x3fff << CGU_FREQ_MON_FCNT_SHIFT) |
#define CGU_FREQ_MON_MEAS (1 << CGU_FREQ_MON_MEAS_SHIFT) |
#define CGU_FREQ_MON_RCNT | ( | x | ) | ((x) << CGU_FREQ_MON_RCNT_SHIFT) |
#define CGU_FREQ_MON_RCNT_MASK (0x1ff << CGU_FREQ_MON_RCNT_SHIFT) |
#define CGU_IDIVA_CTRL_AUTOBLOCK (1 << CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT) |
#define CGU_IDIVA_CTRL_CLK_SEL | ( | x | ) | ((x) << CGU_IDIVA_CTRL_CLK_SEL_SHIFT) |
#define CGU_IDIVA_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVA_CTRL_CLK_SEL_SHIFT) |
#define CGU_IDIVA_CTRL_IDIV | ( | x | ) | ((x) << CGU_IDIVA_CTRL_IDIV_SHIFT) |
#define CGU_IDIVA_CTRL_IDIV_MASK (0x3 << CGU_IDIVA_CTRL_IDIV_SHIFT) |
#define CGU_IDIVA_CTRL_PD (1 << CGU_IDIVA_CTRL_PD_SHIFT) |
#define CGU_IDIVB_CTRL_AUTOBLOCK (1 << CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT) |
#define CGU_IDIVB_CTRL_CLK_SEL | ( | x | ) | ((x) << CGU_IDIVB_CTRL_CLK_SEL_SHIFT) |
#define CGU_IDIVB_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVB_CTRL_CLK_SEL_SHIFT) |
#define CGU_IDIVB_CTRL_IDIV | ( | x | ) | ((x) << CGU_IDIVB_CTRL_IDIV_SHIFT) |
#define CGU_IDIVB_CTRL_IDIV_MASK (0xf << CGU_IDIVB_CTRL_IDIV_SHIFT) |
#define CGU_IDIVB_CTRL_PD (1 << CGU_IDIVB_CTRL_PD_SHIFT) |
#define CGU_IDIVC_CTRL_AUTOBLOCK (1 << CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT) |
#define CGU_IDIVC_CTRL_CLK_SEL | ( | x | ) | ((x) << CGU_IDIVC_CTRL_CLK_SEL_SHIFT) |
#define CGU_IDIVC_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVC_CTRL_CLK_SEL_SHIFT) |
#define CGU_IDIVC_CTRL_IDIV | ( | x | ) | ((x) << CGU_IDIVC_CTRL_IDIV_SHIFT) |
#define CGU_IDIVC_CTRL_IDIV_MASK (0xf << CGU_IDIVC_CTRL_IDIV_SHIFT) |
#define CGU_IDIVC_CTRL_PD (1 << CGU_IDIVC_CTRL_PD_SHIFT) |
#define CGU_IDIVD_CTRL_AUTOBLOCK (1 << CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT) |
#define CGU_IDIVD_CTRL_CLK_SEL | ( | x | ) | ((x) << CGU_IDIVD_CTRL_CLK_SEL_SHIFT) |
#define CGU_IDIVD_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVD_CTRL_CLK_SEL_SHIFT) |
#define CGU_IDIVD_CTRL_IDIV | ( | x | ) | ((x) << CGU_IDIVD_CTRL_IDIV_SHIFT) |
#define CGU_IDIVD_CTRL_IDIV_MASK (0xf << CGU_IDIVD_CTRL_IDIV_SHIFT) |
#define CGU_IDIVD_CTRL_PD (1 << CGU_IDIVD_CTRL_PD_SHIFT) |
#define CGU_IDIVE_CTRL_AUTOBLOCK (1 << CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT) |
#define CGU_IDIVE_CTRL_CLK_SEL | ( | x | ) | ((x) << CGU_IDIVE_CTRL_CLK_SEL_SHIFT) |
#define CGU_IDIVE_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVE_CTRL_CLK_SEL_SHIFT) |
#define CGU_IDIVE_CTRL_IDIV | ( | x | ) | ((x) << CGU_IDIVE_CTRL_IDIV_SHIFT) |
#define CGU_IDIVE_CTRL_IDIV_MASK (0xff << CGU_IDIVE_CTRL_IDIV_SHIFT) |
#define CGU_IDIVE_CTRL_PD (1 << CGU_IDIVE_CTRL_PD_SHIFT) |
#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK (1 << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT) |
#define CGU_PLL0AUDIO_CTRL_BYPASS (1 << CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT) |
#define CGU_PLL0AUDIO_CTRL_CLK_SEL | ( | x | ) | ((x) << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT) |
#define CGU_PLL0AUDIO_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT) |
#define CGU_PLL0AUDIO_CTRL_CLKEN (1 << CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT) |
#define CGU_PLL0AUDIO_CTRL_DIRECTI (1 << CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT) |
#define CGU_PLL0AUDIO_CTRL_DIRECTO (1 << CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT) |
#define CGU_PLL0AUDIO_CTRL_FRM (1 << CGU_PLL0AUDIO_CTRL_FRM_SHIFT) |
#define CGU_PLL0AUDIO_CTRL_MOD_PD (1 << CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT) |
#define CGU_PLL0AUDIO_CTRL_PD (1 << CGU_PLL0AUDIO_CTRL_PD_SHIFT) |
#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ (1 << CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT) |
#define CGU_PLL0AUDIO_CTRL_SEL_EXT (1 << CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT) |
#define CGU_PLL0AUDIO_MDIV_MDEC | ( | x | ) | ((x) << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT) |
#define CGU_PLL0AUDIO_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT) |
#define CGU_PLL0AUDIO_NP_DIV_NDEC | ( | x | ) | ((x) << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT) |
#define CGU_PLL0AUDIO_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT) |
#define CGU_PLL0AUDIO_NP_DIV_PDEC | ( | x | ) | ((x) << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT) |
#define CGU_PLL0AUDIO_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT) |
#define CGU_PLL0AUDIO_STAT_FR (1 << CGU_PLL0AUDIO_STAT_FR_SHIFT) |
#define CGU_PLL0AUDIO_STAT_LOCK (1 << CGU_PLL0AUDIO_STAT_LOCK_SHIFT) |
#define CGU_PLL0USB_CTRL_AUTOBLOCK (1 << CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT) |
#define CGU_PLL0USB_CTRL_BYPASS (1 << CGU_PLL0USB_CTRL_BYPASS_SHIFT) |
#define CGU_PLL0USB_CTRL_CLK_SEL | ( | x | ) | ((x) << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT) |
#define CGU_PLL0USB_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT) |
#define CGU_PLL0USB_CTRL_CLKEN (1 << CGU_PLL0USB_CTRL_CLKEN_SHIFT) |
#define CGU_PLL0USB_CTRL_DIRECTI (1 << CGU_PLL0USB_CTRL_DIRECTI_SHIFT) |
#define CGU_PLL0USB_CTRL_DIRECTO (1 << CGU_PLL0USB_CTRL_DIRECTO_SHIFT) |
#define CGU_PLL0USB_CTRL_FRM (1 << CGU_PLL0USB_CTRL_FRM_SHIFT) |
#define CGU_PLL0USB_CTRL_PD (1 << CGU_PLL0USB_CTRL_PD_SHIFT) |
#define CGU_PLL0USB_MDIV_MDEC | ( | x | ) | ((x) << CGU_PLL0USB_MDIV_MDEC_SHIFT) |
#define CGU_PLL0USB_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0USB_MDIV_MDEC_SHIFT) |
#define CGU_PLL0USB_MDIV_SELI | ( | x | ) | ((x) << CGU_PLL0USB_MDIV_SELI_SHIFT) |
#define CGU_PLL0USB_MDIV_SELI_MASK (0x3f << CGU_PLL0USB_MDIV_SELI_SHIFT) |
#define CGU_PLL0USB_MDIV_SELP | ( | x | ) | ((x) << CGU_PLL0USB_MDIV_SELP_SHIFT) |
#define CGU_PLL0USB_MDIV_SELP_MASK (0x1f << CGU_PLL0USB_MDIV_SELP_SHIFT) |
#define CGU_PLL0USB_MDIV_SELR | ( | x | ) | ((x) << CGU_PLL0USB_MDIV_SELR_SHIFT) |
#define CGU_PLL0USB_MDIV_SELR_MASK (0xf << CGU_PLL0USB_MDIV_SELR_SHIFT) |
#define CGU_PLL0USB_NP_DIV_NDEC | ( | x | ) | ((x) << CGU_PLL0USB_NP_DIV_NDEC_SHIFT) |
#define CGU_PLL0USB_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0USB_NP_DIV_NDEC_SHIFT) |
#define CGU_PLL0USB_NP_DIV_PDEC | ( | x | ) | ((x) << CGU_PLL0USB_NP_DIV_PDEC_SHIFT) |
#define CGU_PLL0USB_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0USB_NP_DIV_PDEC_SHIFT) |
#define CGU_PLL0USB_STAT_FR (1 << CGU_PLL0USB_STAT_FR_SHIFT) |
#define CGU_PLL0USB_STAT_LOCK (1 << CGU_PLL0USB_STAT_LOCK_SHIFT) |
#define CGU_PLL1_CTRL_AUTOBLOCK (1 << CGU_PLL1_CTRL_AUTOBLOCK_SHIFT) |
#define CGU_PLL1_CTRL_BYPASS (1 << CGU_PLL1_CTRL_BYPASS_SHIFT) |
#define CGU_PLL1_CTRL_CLK_SEL | ( | x | ) | ((x) << CGU_PLL1_CTRL_CLK_SEL_SHIFT) |
#define CGU_PLL1_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL1_CTRL_CLK_SEL_SHIFT) |
#define CGU_PLL1_CTRL_DIRECT (1 << CGU_PLL1_CTRL_DIRECT_SHIFT) |
#define CGU_PLL1_CTRL_FBSEL (1 << CGU_PLL1_CTRL_FBSEL_SHIFT) |
#define CGU_PLL1_CTRL_MSEL | ( | x | ) | ((x) << CGU_PLL1_CTRL_MSEL_SHIFT) |
#define CGU_PLL1_CTRL_MSEL_MASK (0xff << CGU_PLL1_CTRL_MSEL_SHIFT) |
#define CGU_PLL1_CTRL_NSEL | ( | x | ) | ((x) << CGU_PLL1_CTRL_NSEL_SHIFT) |
#define CGU_PLL1_CTRL_NSEL_MASK (0x3 << CGU_PLL1_CTRL_NSEL_SHIFT) |
#define CGU_PLL1_CTRL_PD (1 << CGU_PLL1_CTRL_PD_SHIFT) |
#define CGU_PLL1_CTRL_PSEL | ( | x | ) | ((x) << CGU_PLL1_CTRL_PSEL_SHIFT) |
#define CGU_PLL1_CTRL_PSEL_MASK (0x3 << CGU_PLL1_CTRL_PSEL_SHIFT) |
#define CGU_PLL1_STAT_LOCK (1 << CGU_PLL1_STAT_LOCK_SHIFT) |
#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL | ( | x | ) | ((x) << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT) |
#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_MASK (0x3fffff << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT) |
#define CGU_XTAL_OSC_CTRL_BYPASS (1 << CGU_XTAL_OSC_CTRL_BYPASS_SHIFT) |
#define CGU_XTAL_OSC_CTRL_ENABLE (1 << CGU_XTAL_OSC_CTRL_ENABLE_SHIFT) |
#define CGU_XTAL_OSC_CTRL_HF (1 << CGU_XTAL_OSC_CTRL_HF_SHIFT) |