libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
cgu.h
Go to the documentation of this file.
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/** @defgroup cgu_defines Clock Generation Unit Defines
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*
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* @brief <b>Defined Constants and Types for the LPC43xx Clock Generation
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* Unit</b>
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*
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* @ingroup LPC43xx_defines
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2012 Michael Ossmann
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* <mike@ossmann.com>
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*
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* @date 10 March 2013
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LPC43XX_CGU_H
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#define CGU_LPC43XX_CGU_H
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/**@{*/
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#include <
libopencm3/cm3/common.h
>
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#include <
libopencm3/lpc43xx/memorymap.h
>
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/* --- CGU registers ------------------------------------------------------- */
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/* Frequency monitor register */
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#define CGU_FREQ_MON MMIO32(CGU_BASE + 0x014)
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/* Crystal oscillator control register */
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#define CGU_XTAL_OSC_CTRL MMIO32(CGU_BASE + 0x018)
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/* PLL0USB status register */
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#define CGU_PLL0USB_STAT MMIO32(CGU_BASE + 0x01C)
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/* PLL0USB control register */
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#define CGU_PLL0USB_CTRL MMIO32(CGU_BASE + 0x020)
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/* PLL0USB M-divider register */
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#define CGU_PLL0USB_MDIV MMIO32(CGU_BASE + 0x024)
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/* PLL0USB N/P-divider register */
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#define CGU_PLL0USB_NP_DIV MMIO32(CGU_BASE + 0x028)
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/* PLL0AUDIO status register */
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#define CGU_PLL0AUDIO_STAT MMIO32(CGU_BASE + 0x02C)
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/* PLL0AUDIO control register */
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#define CGU_PLL0AUDIO_CTRL MMIO32(CGU_BASE + 0x030)
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/* PLL0AUDIO M-divider register */
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#define CGU_PLL0AUDIO_MDIV MMIO32(CGU_BASE + 0x034)
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/* PLL0AUDIO N/P-divider register */
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#define CGU_PLL0AUDIO_NP_DIV MMIO32(CGU_BASE + 0x038)
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/* PLL0AUDIO fractional divider register */
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#define CGU_PLLAUDIO_FRAC MMIO32(CGU_BASE + 0x03C)
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/* PLL1 status register */
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#define CGU_PLL1_STAT MMIO32(CGU_BASE + 0x040)
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/* PLL1 control register */
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#define CGU_PLL1_CTRL MMIO32(CGU_BASE + 0x044)
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/* Integer divider A control register */
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#define CGU_IDIVA_CTRL MMIO32(CGU_BASE + 0x048)
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/* Integer divider B control register */
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#define CGU_IDIVB_CTRL MMIO32(CGU_BASE + 0x04C)
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/* Integer divider C control register */
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#define CGU_IDIVC_CTRL MMIO32(CGU_BASE + 0x050)
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/* Integer divider D control register */
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#define CGU_IDIVD_CTRL MMIO32(CGU_BASE + 0x054)
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/* Integer divider E control register */
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#define CGU_IDIVE_CTRL MMIO32(CGU_BASE + 0x058)
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/* Output stage 0 control register */
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#define CGU_BASE_SAFE_CLK MMIO32(CGU_BASE + 0x05C)
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/* Output stage 1 control register for base clock */
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#define CGU_BASE_USB0_CLK MMIO32(CGU_BASE + 0x060)
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/* Output stage 2 control register for base clock */
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#define CGU_BASE_PERIPH_CLK MMIO32(CGU_BASE + 0x064)
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/* Output stage 3 control register for base clock */
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#define CGU_BASE_USB1_CLK MMIO32(CGU_BASE + 0x068)
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/* Output stage 4 control register for base clock */
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#define CGU_BASE_M4_CLK MMIO32(CGU_BASE + 0x06C)
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/* Output stage 5 control register for base clock */
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#define CGU_BASE_SPIFI_CLK MMIO32(CGU_BASE + 0x070)
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/* Output stage 6 control register for base clock */
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#define CGU_BASE_SPI_CLK MMIO32(CGU_BASE + 0x074)
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/* Output stage 7 control register for base clock */
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#define CGU_BASE_PHY_RX_CLK MMIO32(CGU_BASE + 0x078)
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/* Output stage 8 control register for base clock */
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#define CGU_BASE_PHY_TX_CLK MMIO32(CGU_BASE + 0x07C)
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/* Output stage 9 control register for base clock */
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#define CGU_BASE_APB1_CLK MMIO32(CGU_BASE + 0x080)
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/* Output stage 10 control register for base clock */
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#define CGU_BASE_APB3_CLK MMIO32(CGU_BASE + 0x084)
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/* Output stage 11 control register for base clock */
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#define CGU_BASE_LCD_CLK MMIO32(CGU_BASE + 0x088)
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/* Output stage 12 control register for base clock */
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#define CGU_BASE_VADC_CLK MMIO32(CGU_BASE + 0x08C)
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/* Output stage 13 control register for base clock */
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#define CGU_BASE_SDIO_CLK MMIO32(CGU_BASE + 0x090)
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/* Output stage 14 control register for base clock */
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#define CGU_BASE_SSP0_CLK MMIO32(CGU_BASE + 0x094)
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/* Output stage 15 control register for base clock */
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#define CGU_BASE_SSP1_CLK MMIO32(CGU_BASE + 0x098)
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/* Output stage 16 control register for base clock */
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#define CGU_BASE_UART0_CLK MMIO32(CGU_BASE + 0x09C)
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/* Output stage 17 control register for base clock */
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#define CGU_BASE_UART1_CLK MMIO32(CGU_BASE + 0x0A0)
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/* Output stage 18 control register for base clock */
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#define CGU_BASE_UART2_CLK MMIO32(CGU_BASE + 0x0A4)
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/* Output stage 19 control register for base clock */
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#define CGU_BASE_UART3_CLK MMIO32(CGU_BASE + 0x0A8)
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/* Output stage 20 control register for base clock */
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#define CGU_BASE_OUT_CLK MMIO32(CGU_BASE + 0x0AC)
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/* Reserved output stage */
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#define CGU_OUTCLK_21_CTRL MMIO32(CGU_BASE + 0x0B0)
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/* Reserved output stage */
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#define CGU_OUTCLK_22_CTRL MMIO32(CGU_BASE + 0x0B4)
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/* Reserved output stage */
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#define CGU_OUTCLK_23_CTRL MMIO32(CGU_BASE + 0x0B8)
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/* Reserved output stage */
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#define CGU_OUTCLK_24_CTRL MMIO32(CGU_BASE + 0x0BC)
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/* Output stage 25 control register for base clock */
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#define CGU_BASE_APLL_CLK MMIO32(CGU_BASE + 0x0C0)
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/* Output stage 26 control CLK register for base clock */
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#define CGU_BASE_CGU_OUT0_CLK MMIO32(CGU_BASE + 0x0C4)
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/* Output stage 27 control CLK register for base clock */
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#define CGU_BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8)
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/* --- CGU_FREQ_MON values -------------------------------------- */
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/* RCNT: 9-bit reference clock-counter value */
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#define CGU_FREQ_MON_RCNT_SHIFT (0)
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#define CGU_FREQ_MON_RCNT_MASK (0x1ff << CGU_FREQ_MON_RCNT_SHIFT)
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#define CGU_FREQ_MON_RCNT(x) ((x) << CGU_FREQ_MON_RCNT_SHIFT)
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/* FCNT: 14-bit selected clock-counter value */
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#define CGU_FREQ_MON_FCNT_SHIFT (9)
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#define CGU_FREQ_MON_FCNT_MASK (0x3fff << CGU_FREQ_MON_FCNT_SHIFT)
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#define CGU_FREQ_MON_FCNT(x) ((x) << CGU_FREQ_MON_FCNT_SHIFT)
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/* MEAS: Measure frequency */
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#define CGU_FREQ_MON_MEAS_SHIFT (23)
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#define CGU_FREQ_MON_MEAS (1 << CGU_FREQ_MON_MEAS_SHIFT)
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/* CLK_SEL: Clock-source selection for the clock to be measured */
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#define CGU_FREQ_MON_CLK_SEL_SHIFT (24)
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#define CGU_FREQ_MON_CLK_SEL_MASK (0x1f << CGU_FREQ_MON_CLK_SEL_SHIFT)
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#define CGU_FREQ_MON_CLK_SEL(x) ((x) << CGU_FREQ_MON_CLK_SEL_SHIFT)
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/* --- CGU_XTAL_OSC_CTRL values --------------------------------- */
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/* ENABLE: Oscillator-pad enable */
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#define CGU_XTAL_OSC_CTRL_ENABLE_SHIFT (0)
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#define CGU_XTAL_OSC_CTRL_ENABLE (1 << CGU_XTAL_OSC_CTRL_ENABLE_SHIFT)
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/* BYPASS: Configure crystal operation or external-clock input pin XTAL1 */
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#define CGU_XTAL_OSC_CTRL_BYPASS_SHIFT (1)
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#define CGU_XTAL_OSC_CTRL_BYPASS (1 << CGU_XTAL_OSC_CTRL_BYPASS_SHIFT)
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/* HF: Select frequency range */
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#define CGU_XTAL_OSC_CTRL_HF_SHIFT (2)
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#define CGU_XTAL_OSC_CTRL_HF (1 << CGU_XTAL_OSC_CTRL_HF_SHIFT)
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/* --- CGU_PLL0USB_STAT values ---------------------------------- */
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/* LOCK: PLL0 lock indicator */
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#define CGU_PLL0USB_STAT_LOCK_SHIFT (0)
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#define CGU_PLL0USB_STAT_LOCK (1 << CGU_PLL0USB_STAT_LOCK_SHIFT)
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/* FR: PLL0 free running indicator */
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#define CGU_PLL0USB_STAT_FR_SHIFT (1)
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#define CGU_PLL0USB_STAT_FR (1 << CGU_PLL0USB_STAT_FR_SHIFT)
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/* --- CGU_PLL0USB_CTRL values ---------------------------------- */
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/* PD: PLL0 power down */
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#define CGU_PLL0USB_CTRL_PD_SHIFT (0)
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#define CGU_PLL0USB_CTRL_PD (1 << CGU_PLL0USB_CTRL_PD_SHIFT)
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/* BYPASS: Input clock bypass control */
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#define CGU_PLL0USB_CTRL_BYPASS_SHIFT (1)
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#define CGU_PLL0USB_CTRL_BYPASS (1 << CGU_PLL0USB_CTRL_BYPASS_SHIFT)
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/* DIRECTI: PLL0 direct input */
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#define CGU_PLL0USB_CTRL_DIRECTI_SHIFT (2)
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#define CGU_PLL0USB_CTRL_DIRECTI (1 << CGU_PLL0USB_CTRL_DIRECTI_SHIFT)
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/* DIRECTO: PLL0 direct output */
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#define CGU_PLL0USB_CTRL_DIRECTO_SHIFT (3)
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#define CGU_PLL0USB_CTRL_DIRECTO (1 << CGU_PLL0USB_CTRL_DIRECTO_SHIFT)
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/* CLKEN: PLL0 clock enable */
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#define CGU_PLL0USB_CTRL_CLKEN_SHIFT (4)
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#define CGU_PLL0USB_CTRL_CLKEN (1 << CGU_PLL0USB_CTRL_CLKEN_SHIFT)
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/* FRM: Free running mode */
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#define CGU_PLL0USB_CTRL_FRM_SHIFT (6)
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#define CGU_PLL0USB_CTRL_FRM (1 << CGU_PLL0USB_CTRL_FRM_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT (11)
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#define CGU_PLL0USB_CTRL_AUTOBLOCK (1 << CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_PLL0USB_CTRL_CLK_SEL_SHIFT (24)
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#define CGU_PLL0USB_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT)
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#define CGU_PLL0USB_CTRL_CLK_SEL(x) ((x) << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT)
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/* --- CGU_PLL0USB_MDIV values ---------------------------------- */
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/* MDEC: Decoded M-divider coefficient value */
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#define CGU_PLL0USB_MDIV_MDEC_SHIFT (0)
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#define CGU_PLL0USB_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0USB_MDIV_MDEC_SHIFT)
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#define CGU_PLL0USB_MDIV_MDEC(x) ((x) << CGU_PLL0USB_MDIV_MDEC_SHIFT)
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/* SELP: Bandwidth select P value */
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#define CGU_PLL0USB_MDIV_SELP_SHIFT (17)
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#define CGU_PLL0USB_MDIV_SELP_MASK (0x1f << CGU_PLL0USB_MDIV_SELP_SHIFT)
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#define CGU_PLL0USB_MDIV_SELP(x) ((x) << CGU_PLL0USB_MDIV_SELP_SHIFT)
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/* SELI: Bandwidth select I value */
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#define CGU_PLL0USB_MDIV_SELI_SHIFT (22)
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#define CGU_PLL0USB_MDIV_SELI_MASK (0x3f << CGU_PLL0USB_MDIV_SELI_SHIFT)
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#define CGU_PLL0USB_MDIV_SELI(x) ((x) << CGU_PLL0USB_MDIV_SELI_SHIFT)
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/* SELR: Bandwidth select R value */
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#define CGU_PLL0USB_MDIV_SELR_SHIFT (28)
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#define CGU_PLL0USB_MDIV_SELR_MASK (0xf << CGU_PLL0USB_MDIV_SELR_SHIFT)
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#define CGU_PLL0USB_MDIV_SELR(x) ((x) << CGU_PLL0USB_MDIV_SELR_SHIFT)
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/* --- CGU_PLL0USB_NP_DIV values -------------------------------- */
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/* PDEC: Decoded P-divider coefficient value */
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#define CGU_PLL0USB_NP_DIV_PDEC_SHIFT (0)
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#define CGU_PLL0USB_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0USB_NP_DIV_PDEC_SHIFT)
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#define CGU_PLL0USB_NP_DIV_PDEC(x) ((x) << CGU_PLL0USB_NP_DIV_PDEC_SHIFT)
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/* NDEC: Decoded N-divider coefficient value */
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#define CGU_PLL0USB_NP_DIV_NDEC_SHIFT (12)
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#define CGU_PLL0USB_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0USB_NP_DIV_NDEC_SHIFT)
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#define CGU_PLL0USB_NP_DIV_NDEC(x) ((x) << CGU_PLL0USB_NP_DIV_NDEC_SHIFT)
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/* --- CGU_PLL0AUDIO_STAT values -------------------------------- */
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/* LOCK: PLL0 lock indicator */
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#define CGU_PLL0AUDIO_STAT_LOCK_SHIFT (0)
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#define CGU_PLL0AUDIO_STAT_LOCK (1 << CGU_PLL0AUDIO_STAT_LOCK_SHIFT)
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/* FR: PLL0 free running indicator */
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#define CGU_PLL0AUDIO_STAT_FR_SHIFT (1)
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#define CGU_PLL0AUDIO_STAT_FR (1 << CGU_PLL0AUDIO_STAT_FR_SHIFT)
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/* --- CGU_PLL0AUDIO_CTRL values -------------------------------- */
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/* PD: PLL0 power down */
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#define CGU_PLL0AUDIO_CTRL_PD_SHIFT (0)
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#define CGU_PLL0AUDIO_CTRL_PD (1 << CGU_PLL0AUDIO_CTRL_PD_SHIFT)
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/* BYPASS: Input clock bypass control */
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#define CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT (1)
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#define CGU_PLL0AUDIO_CTRL_BYPASS (1 << CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT)
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/* DIRECTI: PLL0 direct input */
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#define CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT (2)
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#define CGU_PLL0AUDIO_CTRL_DIRECTI (1 << CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT)
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/* DIRECTO: PLL0 direct output */
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#define CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT (3)
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#define CGU_PLL0AUDIO_CTRL_DIRECTO (1 << CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT)
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/* CLKEN: PLL0 clock enable */
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#define CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT (4)
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#define CGU_PLL0AUDIO_CTRL_CLKEN (1 << CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT)
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/* FRM: Free running mode */
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#define CGU_PLL0AUDIO_CTRL_FRM_SHIFT (6)
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#define CGU_PLL0AUDIO_CTRL_FRM (1 << CGU_PLL0AUDIO_CTRL_FRM_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT (11)
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#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK \
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(1 << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT)
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/* PLLFRACT_REQ: Fractional PLL word write request */
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#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT (12)
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#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ \
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(1 << CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT)
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/* SEL_EXT: Select fractional divider */
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#define CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT (13)
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#define CGU_PLL0AUDIO_CTRL_SEL_EXT (1 << CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT)
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/* MOD_PD: Sigma-Delta modulator power-down */
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#define CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT (14)
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#define CGU_PLL0AUDIO_CTRL_MOD_PD (1 << CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT)
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/* CLK_SEL: Clock source selection */
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#define CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT (24)
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#define CGU_PLL0AUDIO_CTRL_CLK_SEL_MASK \
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(0x1f << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT)
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#define CGU_PLL0AUDIO_CTRL_CLK_SEL(x) \
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((x) << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT)
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/* --- CGU_PLL0AUDIO_MDIV values -------------------------------- */
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/* MDEC: Decoded M-divider coefficient value */
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#define CGU_PLL0AUDIO_MDIV_MDEC_SHIFT (0)
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#define CGU_PLL0AUDIO_MDIV_MDEC_MASK \
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(0x1ffff << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT)
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#define CGU_PLL0AUDIO_MDIV_MDEC(x) \
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((x) << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT)
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/* --- CGU_PLL0AUDIO_NP_DIV values ------------------------------ */
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/* PDEC: Decoded P-divider coefficient value */
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#define CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT (0)
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#define CGU_PLL0AUDIO_NP_DIV_PDEC_MASK \
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(0x7f << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT)
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#define CGU_PLL0AUDIO_NP_DIV_PDEC(x) \
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((x) << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT)
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/* NDEC: Decoded N-divider coefficient value */
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#define CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT (12)
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#define CGU_PLL0AUDIO_NP_DIV_NDEC_MASK \
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(0x3ff << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT)
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#define CGU_PLL0AUDIO_NP_DIV_NDEC(x) \
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((x) << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT)
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/* --- CGU_PLLAUDIO_FRAC values --------------------------------- */
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/* PLLFRACT_CTRL: PLL fractional divider control word */
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#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT (0)
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#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_MASK \
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(0x3fffff << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT)
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#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL(x) \
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((x) << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT)
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/* --- CGU_PLL1_STAT values ------------------------------------- */
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/* LOCK: PLL1 lock indicator */
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#define CGU_PLL1_STAT_LOCK_SHIFT (0)
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#define CGU_PLL1_STAT_LOCK (1 << CGU_PLL1_STAT_LOCK_SHIFT)
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/* --- CGU_PLL1_CTRL values ------------------------------------- */
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/* PD: PLL1 power down */
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#define CGU_PLL1_CTRL_PD_SHIFT (0)
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#define CGU_PLL1_CTRL_PD (1 << CGU_PLL1_CTRL_PD_SHIFT)
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/* BYPASS: Input clock bypass control */
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#define CGU_PLL1_CTRL_BYPASS_SHIFT (1)
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#define CGU_PLL1_CTRL_BYPASS (1 << CGU_PLL1_CTRL_BYPASS_SHIFT)
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/* FBSEL: PLL feedback select */
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#define CGU_PLL1_CTRL_FBSEL_SHIFT (6)
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#define CGU_PLL1_CTRL_FBSEL (1 << CGU_PLL1_CTRL_FBSEL_SHIFT)
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/* DIRECT: PLL direct CCO output */
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#define CGU_PLL1_CTRL_DIRECT_SHIFT (7)
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#define CGU_PLL1_CTRL_DIRECT (1 << CGU_PLL1_CTRL_DIRECT_SHIFT)
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/* PSEL: Post-divider division ratio P */
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#define CGU_PLL1_CTRL_PSEL_SHIFT (8)
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#define CGU_PLL1_CTRL_PSEL_MASK (0x3 << CGU_PLL1_CTRL_PSEL_SHIFT)
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#define CGU_PLL1_CTRL_PSEL(x) ((x) << CGU_PLL1_CTRL_PSEL_SHIFT)
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/* AUTOBLOCK: Block clock automatically during frequency change */
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#define CGU_PLL1_CTRL_AUTOBLOCK_SHIFT (11)
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#define CGU_PLL1_CTRL_AUTOBLOCK (1 << CGU_PLL1_CTRL_AUTOBLOCK_SHIFT)
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/* NSEL: Pre-divider division ratio N */
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#define CGU_PLL1_CTRL_NSEL_SHIFT (12)
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#define CGU_PLL1_CTRL_NSEL_MASK (0x3 << CGU_PLL1_CTRL_NSEL_SHIFT)
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#define CGU_PLL1_CTRL_NSEL(x) ((x) << CGU_PLL1_CTRL_NSEL_SHIFT)
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/* MSEL: Feedback-divider division ratio (M) */
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#define CGU_PLL1_CTRL_MSEL_SHIFT (16)
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#define CGU_PLL1_CTRL_MSEL_MASK (0xff << CGU_PLL1_CTRL_MSEL_SHIFT)
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#define CGU_PLL1_CTRL_MSEL(x) ((x) << CGU_PLL1_CTRL_MSEL_SHIFT)
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/* CLK_SEL: Clock-source selection */
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#define CGU_PLL1_CTRL_CLK_SEL_SHIFT (24)
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#define CGU_PLL1_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL1_CTRL_CLK_SEL_SHIFT)
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#define CGU_PLL1_CTRL_CLK_SEL(x) ((x) << CGU_PLL1_CTRL_CLK_SEL_SHIFT)
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/* --- CGU_IDIVA_CTRL values ------------------------------------ */
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/* PD: Integer divider power down */
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#define CGU_IDIVA_CTRL_PD_SHIFT (0)
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#define CGU_IDIVA_CTRL_PD (1 << CGU_IDIVA_CTRL_PD_SHIFT)
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/* IDIV: Integer divider A divider value (1/(IDIV + 1)) */
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#define CGU_IDIVA_CTRL_IDIV_SHIFT (2)
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#define CGU_IDIVA_CTRL_IDIV_MASK (0x3 << CGU_IDIVA_CTRL_IDIV_SHIFT)
450
#define CGU_IDIVA_CTRL_IDIV(x) ((x) << CGU_IDIVA_CTRL_IDIV_SHIFT)
451
452
/* AUTOBLOCK: Block clock automatically during frequency change */
453
#define CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT (11)
454
#define CGU_IDIVA_CTRL_AUTOBLOCK (1 << CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT)
455
456
/* CLK_SEL: Clock source selection */
457
#define CGU_IDIVA_CTRL_CLK_SEL_SHIFT (24)
458
#define CGU_IDIVA_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVA_CTRL_CLK_SEL_SHIFT)
459
#define CGU_IDIVA_CTRL_CLK_SEL(x) ((x) << CGU_IDIVA_CTRL_CLK_SEL_SHIFT)
460
461
/* --- CGU_IDIVB_CTRL values ------------------------------------ */
462
463
/* PD: Integer divider power down */
464
#define CGU_IDIVB_CTRL_PD_SHIFT (0)
465
#define CGU_IDIVB_CTRL_PD (1 << CGU_IDIVB_CTRL_PD_SHIFT)
466
467
/* IDIV: Integer divider B divider value (1/(IDIV + 1)) */
468
#define CGU_IDIVB_CTRL_IDIV_SHIFT (2)
469
#define CGU_IDIVB_CTRL_IDIV_MASK (0xf << CGU_IDIVB_CTRL_IDIV_SHIFT)
470
#define CGU_IDIVB_CTRL_IDIV(x) ((x) << CGU_IDIVB_CTRL_IDIV_SHIFT)
471
472
/* AUTOBLOCK: Block clock automatically during frequency change */
473
#define CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT (11)
474
#define CGU_IDIVB_CTRL_AUTOBLOCK (1 << CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT)
475
476
/* CLK_SEL: Clock source selection */
477
#define CGU_IDIVB_CTRL_CLK_SEL_SHIFT (24)
478
#define CGU_IDIVB_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVB_CTRL_CLK_SEL_SHIFT)
479
#define CGU_IDIVB_CTRL_CLK_SEL(x) ((x) << CGU_IDIVB_CTRL_CLK_SEL_SHIFT)
480
481
/* --- CGU_IDIVC_CTRL values ------------------------------------ */
482
483
/* PD: Integer divider power down */
484
#define CGU_IDIVC_CTRL_PD_SHIFT (0)
485
#define CGU_IDIVC_CTRL_PD (1 << CGU_IDIVC_CTRL_PD_SHIFT)
486
487
/* IDIV: Integer divider C divider value (1/(IDIV + 1)) */
488
#define CGU_IDIVC_CTRL_IDIV_SHIFT (2)
489
#define CGU_IDIVC_CTRL_IDIV_MASK (0xf << CGU_IDIVC_CTRL_IDIV_SHIFT)
490
#define CGU_IDIVC_CTRL_IDIV(x) ((x) << CGU_IDIVC_CTRL_IDIV_SHIFT)
491
492
/* AUTOBLOCK: Block clock automatically during frequency change */
493
#define CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT (11)
494
#define CGU_IDIVC_CTRL_AUTOBLOCK (1 << CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT)
495
496
/* CLK_SEL: Clock source selection */
497
#define CGU_IDIVC_CTRL_CLK_SEL_SHIFT (24)
498
#define CGU_IDIVC_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVC_CTRL_CLK_SEL_SHIFT)
499
#define CGU_IDIVC_CTRL_CLK_SEL(x) ((x) << CGU_IDIVC_CTRL_CLK_SEL_SHIFT)
500
501
/* --- CGU_IDIVD_CTRL values ------------------------------------ */
502
503
/* PD: Integer divider power down */
504
#define CGU_IDIVD_CTRL_PD_SHIFT (0)
505
#define CGU_IDIVD_CTRL_PD (1 << CGU_IDIVD_CTRL_PD_SHIFT)
506
507
/* IDIV: Integer divider D divider value (1/(IDIV + 1)) */
508
#define CGU_IDIVD_CTRL_IDIV_SHIFT (2)
509
#define CGU_IDIVD_CTRL_IDIV_MASK (0xf << CGU_IDIVD_CTRL_IDIV_SHIFT)
510
#define CGU_IDIVD_CTRL_IDIV(x) ((x) << CGU_IDIVD_CTRL_IDIV_SHIFT)
511
512
/* AUTOBLOCK: Block clock automatically during frequency change */
513
#define CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT (11)
514
#define CGU_IDIVD_CTRL_AUTOBLOCK (1 << CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT)
515
516
/* CLK_SEL: Clock source selection */
517
#define CGU_IDIVD_CTRL_CLK_SEL_SHIFT (24)
518
#define CGU_IDIVD_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVD_CTRL_CLK_SEL_SHIFT)
519
#define CGU_IDIVD_CTRL_CLK_SEL(x) ((x) << CGU_IDIVD_CTRL_CLK_SEL_SHIFT)
520
521
/* --- CGU_IDIVE_CTRL values ------------------------------------ */
522
523
/* PD: Integer divider power down */
524
#define CGU_IDIVE_CTRL_PD_SHIFT (0)
525
#define CGU_IDIVE_CTRL_PD (1 << CGU_IDIVE_CTRL_PD_SHIFT)
526
527
/* IDIV: Integer divider E divider value (1/(IDIV + 1)) */
528
#define CGU_IDIVE_CTRL_IDIV_SHIFT (2)
529
#define CGU_IDIVE_CTRL_IDIV_MASK (0xff << CGU_IDIVE_CTRL_IDIV_SHIFT)
530
#define CGU_IDIVE_CTRL_IDIV(x) ((x) << CGU_IDIVE_CTRL_IDIV_SHIFT)
531
532
/* AUTOBLOCK: Block clock automatically during frequency change */
533
#define CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT (11)
534
#define CGU_IDIVE_CTRL_AUTOBLOCK (1 << CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT)
535
536
/* CLK_SEL: Clock source selection */
537
#define CGU_IDIVE_CTRL_CLK_SEL_SHIFT (24)
538
#define CGU_IDIVE_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVE_CTRL_CLK_SEL_SHIFT)
539
#define CGU_IDIVE_CTRL_CLK_SEL(x) ((x) << CGU_IDIVE_CTRL_CLK_SEL_SHIFT)
540
541
/* --- CGU_BASE_SAFE_CLK values --------------------------------- */
542
543
/* PD: Output stage power down */
544
#define CGU_BASE_SAFE_CLK_PD_SHIFT (0)
545
#define CGU_BASE_SAFE_CLK_PD (1 << CGU_BASE_SAFE_CLK_PD_SHIFT)
546
547
/* AUTOBLOCK: Block clock automatically during frequency change */
548
#define CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT (11)
549
#define CGU_BASE_SAFE_CLK_AUTOBLOCK (1 << CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT)
550
551
/* CLK_SEL: Clock source selection */
552
#define CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT (24)
553
#define CGU_BASE_SAFE_CLK_CLK_SEL_MASK \
554
(0x1f << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT)
555
#define CGU_BASE_SAFE_CLK_CLK_SEL(x) \
556
((x) << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT)
557
558
/* --- CGU_BASE_USB0_CLK values --------------------------------- */
559
560
/* PD: Output stage power down */
561
#define CGU_BASE_USB0_CLK_PD_SHIFT (0)
562
#define CGU_BASE_USB0_CLK_PD (1 << CGU_BASE_USB0_CLK_PD_SHIFT)
563
564
/* AUTOBLOCK: Block clock automatically during frequency change */
565
#define CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT (11)
566
#define CGU_BASE_USB0_CLK_AUTOBLOCK (1 << CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT)
567
568
/* CLK_SEL: Clock source selection */
569
#define CGU_BASE_USB0_CLK_CLK_SEL_SHIFT (24)
570
#define CGU_BASE_USB0_CLK_CLK_SEL_MASK \
571
(0x1f << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT)
572
#define CGU_BASE_USB0_CLK_CLK_SEL(x) \
573
((x) << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT)
574
575
/* --- CGU_BASE_PERIPH_CLK values ------------------------------- */
576
577
/* PD: Output stage power down */
578
#define CGU_BASE_PERIPH_CLK_PD_SHIFT (0)
579
#define CGU_BASE_PERIPH_CLK_PD (1 << CGU_BASE_PERIPH_CLK_PD_SHIFT)
580
581
/* AUTOBLOCK: Block clock automatically during frequency change */
582
#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT (11)
583
#define CGU_BASE_PERIPH_CLK_AUTOBLOCK \
584
(1 << CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT)
585
586
/* CLK_SEL: Clock source selection */
587
#define CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT (24)
588
#define CGU_BASE_PERIPH_CLK_CLK_SEL_MASK \
589
(0x1f << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT)
590
#define CGU_BASE_PERIPH_CLK_CLK_SEL(x) \
591
((x) << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT)
592
593
/* --- CGU_BASE_USB1_CLK values --------------------------------- */
594
595
/* PD: Output stage power down */
596
#define CGU_BASE_USB1_CLK_PD_SHIFT (0)
597
#define CGU_BASE_USB1_CLK_PD (1 << CGU_BASE_USB1_CLK_PD_SHIFT)
598
599
/* AUTOBLOCK: Block clock automatically during frequency change */
600
#define CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT (11)
601
#define CGU_BASE_USB1_CLK_AUTOBLOCK (1 << CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT)
602
603
/* CLK_SEL: Clock source selection */
604
#define CGU_BASE_USB1_CLK_CLK_SEL_SHIFT (24)
605
#define CGU_BASE_USB1_CLK_CLK_SEL_MASK \
606
(0x1f << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT)
607
#define CGU_BASE_USB1_CLK_CLK_SEL(x) \
608
((x) << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT)
609
610
/* --- CGU_BASE_M4_CLK values ----------------------------------- */
611
612
/* PD: Output stage power down */
613
#define CGU_BASE_M4_CLK_PD_SHIFT (0)
614
#define CGU_BASE_M4_CLK_PD (1 << CGU_BASE_M4_CLK_PD_SHIFT)
615
616
/* AUTOBLOCK: Block clock automatically during frequency change */
617
#define CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT (11)
618
#define CGU_BASE_M4_CLK_AUTOBLOCK (1 << CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT)
619
620
/* CLK_SEL: Clock source selection */
621
#define CGU_BASE_M4_CLK_CLK_SEL_SHIFT (24)
622
#define CGU_BASE_M4_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_M4_CLK_CLK_SEL_SHIFT)
623
#define CGU_BASE_M4_CLK_CLK_SEL(x) ((x) << CGU_BASE_M4_CLK_CLK_SEL_SHIFT)
624
625
/* --- CGU_BASE_SPIFI_CLK values -------------------------------- */
626
627
/* PD: Output stage power down */
628
#define CGU_BASE_SPIFI_CLK_PD_SHIFT (0)
629
#define CGU_BASE_SPIFI_CLK_PD (1 << CGU_BASE_SPIFI_CLK_PD_SHIFT)
630
631
/* AUTOBLOCK: Block clock automatically during frequency change */
632
#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT (11)
633
#define CGU_BASE_SPIFI_CLK_AUTOBLOCK \
634
(1 << CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT)
635
636
/* CLK_SEL: Clock source selection */
637
#define CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT (24)
638
#define CGU_BASE_SPIFI_CLK_CLK_SEL_MASK \
639
(0x1f << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT)
640
#define CGU_BASE_SPIFI_CLK_CLK_SEL(x) \
641
((x) << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT)
642
643
/* --- CGU_BASE_SPI_CLK values ---------------------------------- */
644
645
/* PD: Output stage power down */
646
#define CGU_BASE_SPI_CLK_PD_SHIFT (0)
647
#define CGU_BASE_SPI_CLK_PD (1 << CGU_BASE_SPI_CLK_PD_SHIFT)
648
649
/* AUTOBLOCK: Block clock automatically during frequency change */
650
#define CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT (11)
651
#define CGU_BASE_SPI_CLK_AUTOBLOCK (1 << CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT)
652
653
/* CLK_SEL: Clock source selection */
654
#define CGU_BASE_SPI_CLK_CLK_SEL_SHIFT (24)
655
#define CGU_BASE_SPI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT)
656
#define CGU_BASE_SPI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT)
657
658
/* --- CGU_BASE_PHY_RX_CLK values ------------------------------- */
659
660
/* PD: Output stage power down */
661
#define CGU_BASE_PHY_RX_CLK_PD_SHIFT (0)
662
#define CGU_BASE_PHY_RX_CLK_PD (1 << CGU_BASE_PHY_RX_CLK_PD_SHIFT)
663
664
/* AUTOBLOCK: Block clock automatically during frequency change */
665
#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT (11)
666
#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK \
667
(1 << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT)
668
669
/* CLK_SEL: Clock source selection */
670
#define CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT (24)
671
#define CGU_BASE_PHY_RX_CLK_CLK_SEL_MASK \
672
(0x1f << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT)
673
#define CGU_BASE_PHY_RX_CLK_CLK_SEL(x) \
674
((x) << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT)
675
676
/* --- CGU_BASE_PHY_TX_CLK values ------------------------------- */
677
678
/* PD: Output stage power down */
679
#define CGU_BASE_PHY_TX_CLK_PD_SHIFT (0)
680
#define CGU_BASE_PHY_TX_CLK_PD (1 << CGU_BASE_PHY_TX_CLK_PD_SHIFT)
681
682
/* AUTOBLOCK: Block clock automatically during frequency change */
683
#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT (11)
684
#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK \
685
(1 << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT)
686
687
/* CLK_SEL: Clock source selection */
688
#define CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT (24)
689
#define CGU_BASE_PHY_TX_CLK_CLK_SEL_MASK \
690
(0x1f << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT)
691
#define CGU_BASE_PHY_TX_CLK_CLK_SEL(x) \
692
((x) << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT)
693
694
/* --- CGU_BASE_APB1_CLK values --------------------------------- */
695
696
/* PD: Output stage power down */
697
#define CGU_BASE_APB1_CLK_PD_SHIFT (0)
698
#define CGU_BASE_APB1_CLK_PD (1 << CGU_BASE_APB1_CLK_PD_SHIFT)
699
700
/* AUTOBLOCK: Block clock automatically during frequency change */
701
#define CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT (11)
702
#define CGU_BASE_APB1_CLK_AUTOBLOCK (1 << CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT)
703
704
/* CLK_SEL: Clock source selection */
705
#define CGU_BASE_APB1_CLK_CLK_SEL_SHIFT (24)
706
#define CGU_BASE_APB1_CLK_CLK_SEL_MASK \
707
(0x1f << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT)
708
#define CGU_BASE_APB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT)
709
710
/* --- CGU_BASE_APB3_CLK values --------------------------------- */
711
712
/* PD: Output stage power down */
713
#define CGU_BASE_APB3_CLK_PD_SHIFT (0)
714
#define CGU_BASE_APB3_CLK_PD (1 << CGU_BASE_APB3_CLK_PD_SHIFT)
715
716
/* AUTOBLOCK: Block clock automatically during frequency change */
717
#define CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT (11)
718
#define CGU_BASE_APB3_CLK_AUTOBLOCK (1 << CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT)
719
720
/* CLK_SEL: Clock source selection */
721
#define CGU_BASE_APB3_CLK_CLK_SEL_SHIFT (24)
722
#define CGU_BASE_APB3_CLK_CLK_SEL_MASK \
723
(0x1f << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT)
724
#define CGU_BASE_APB3_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT)
725
726
/* --- CGU_BASE_LCD_CLK values ---------------------------------- */
727
728
/* PD: Output stage power down */
729
#define CGU_BASE_LCD_CLK_PD_SHIFT (0)
730
#define CGU_BASE_LCD_CLK_PD (1 << CGU_BASE_LCD_CLK_PD_SHIFT)
731
732
/* AUTOBLOCK: Block clock automatically during frequency change */
733
#define CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT (11)
734
#define CGU_BASE_LCD_CLK_AUTOBLOCK (1 << CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT)
735
736
/* CLK_SEL: Clock source selection */
737
#define CGU_BASE_LCD_CLK_CLK_SEL_SHIFT (24)
738
#define CGU_BASE_LCD_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT)
739
#define CGU_BASE_LCD_CLK_CLK_SEL(x) ((x) << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT)
740
741
/* --- CGU_BASE_VADC_CLK values --------------------------------- */
742
743
/* PD: Output stage power down */
744
#define CGU_BASE_VADC_CLK_PD_SHIFT (0)
745
#define CGU_BASE_VADC_CLK_PD (1 << CGU_BASE_VADC_CLK_PD_SHIFT)
746
747
/* AUTOBLOCK: Block clock automatically during frequency change */
748
#define CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT (11)
749
#define CGU_BASE_VADC_CLK_AUTOBLOCK (1 << CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT)
750
751
/* CLK_SEL: Clock source selection */
752
#define CGU_BASE_VADC_CLK_CLK_SEL_SHIFT (24)
753
#define CGU_BASE_VADC_CLK_CLK_SEL_MASK \
754
(0x1f << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT)
755
#define CGU_BASE_VADC_CLK_CLK_SEL(x) ((x) << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT)
756
757
/* --- CGU_BASE_SDIO_CLK values --------------------------------- */
758
759
/* PD: Output stage power down */
760
#define CGU_BASE_SDIO_CLK_PD_SHIFT (0)
761
#define CGU_BASE_SDIO_CLK_PD (1 << CGU_BASE_SDIO_CLK_PD_SHIFT)
762
763
/* AUTOBLOCK: Block clock automatically during frequency change */
764
#define CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT (11)
765
#define CGU_BASE_SDIO_CLK_AUTOBLOCK (1 << CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT)
766
767
/* CLK_SEL: Clock source selection */
768
#define CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT (24)
769
#define CGU_BASE_SDIO_CLK_CLK_SEL_MASK \
770
(0x1f << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT)
771
#define CGU_BASE_SDIO_CLK_CLK_SEL(x) ((x) << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT)
772
773
/* --- CGU_BASE_SSP0_CLK values --------------------------------- */
774
775
/* PD: Output stage power down */
776
#define CGU_BASE_SSP0_CLK_PD_SHIFT (0)
777
#define CGU_BASE_SSP0_CLK_PD (1 << CGU_BASE_SSP0_CLK_PD_SHIFT)
778
779
/* AUTOBLOCK: Block clock automatically during frequency change */
780
#define CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT (11)
781
#define CGU_BASE_SSP0_CLK_AUTOBLOCK (1 << CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT)
782
783
/* CLK_SEL: Clock source selection */
784
#define CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT (24)
785
#define CGU_BASE_SSP0_CLK_CLK_SEL_MASK \
786
(0x1f << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT)
787
#define CGU_BASE_SSP0_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT)
788
789
/* --- CGU_BASE_SSP1_CLK values --------------------------------- */
790
791
/* PD: Output stage power down */
792
#define CGU_BASE_SSP1_CLK_PD_SHIFT (0)
793
#define CGU_BASE_SSP1_CLK_PD (1 << CGU_BASE_SSP1_CLK_PD_SHIFT)
794
795
/* AUTOBLOCK: Block clock automatically during frequency change */
796
#define CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT (11)
797
#define CGU_BASE_SSP1_CLK_AUTOBLOCK (1 << CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT)
798
799
/* CLK_SEL: Clock source selection */
800
#define CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT (24)
801
#define CGU_BASE_SSP1_CLK_CLK_SEL_MASK \
802
(0x1f << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT)
803
#define CGU_BASE_SSP1_CLK_CLK_SEL(x) \
804
((x) << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT)
805
806
/* --- CGU_BASE_UART0_CLK values -------------------------------- */
807
808
/* PD: Output stage power down */
809
#define CGU_BASE_UART0_CLK_PD_SHIFT (0)
810
#define CGU_BASE_UART0_CLK_PD (1 << CGU_BASE_UART0_CLK_PD_SHIFT)
811
812
/* AUTOBLOCK: Block clock automatically during frequency change */
813
#define CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT (11)
814
#define CGU_BASE_UART0_CLK_AUTOBLOCK \
815
(1 << CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT)
816
817
/* CLK_SEL: Clock source selection */
818
#define CGU_BASE_UART0_CLK_CLK_SEL_SHIFT (24)
819
#define CGU_BASE_UART0_CLK_CLK_SEL_MASK \
820
(0x1f << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT)
821
#define CGU_BASE_UART0_CLK_CLK_SEL(x) \
822
((x) << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT)
823
824
/* --- CGU_BASE_UART1_CLK values -------------------------------- */
825
826
/* PD: Output stage power down */
827
#define CGU_BASE_UART1_CLK_PD_SHIFT (0)
828
#define CGU_BASE_UART1_CLK_PD (1 << CGU_BASE_UART1_CLK_PD_SHIFT)
829
830
/* AUTOBLOCK: Block clock automatically during frequency change */
831
#define CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT (11)
832
#define CGU_BASE_UART1_CLK_AUTOBLOCK \
833
(1 << CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT)
834
835
/* CLK_SEL: Clock source selection */
836
#define CGU_BASE_UART1_CLK_CLK_SEL_SHIFT (24)
837
#define CGU_BASE_UART1_CLK_CLK_SEL_MASK \
838
(0x1f << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT)
839
#define CGU_BASE_UART1_CLK_CLK_SEL(x) \
840
((x) << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT)
841
842
/* --- CGU_BASE_UART2_CLK values -------------------------------- */
843
844
/* PD: Output stage power down */
845
#define CGU_BASE_UART2_CLK_PD_SHIFT (0)
846
#define CGU_BASE_UART2_CLK_PD (1 << CGU_BASE_UART2_CLK_PD_SHIFT)
847
848
/* AUTOBLOCK: Block clock automatically during frequency change */
849
#define CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT (11)
850
#define CGU_BASE_UART2_CLK_AUTOBLOCK \
851
(1 << CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT)
852
853
/* CLK_SEL: Clock source selection */
854
#define CGU_BASE_UART2_CLK_CLK_SEL_SHIFT (24)
855
#define CGU_BASE_UART2_CLK_CLK_SEL_MASK \
856
(0x1f << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT)
857
#define CGU_BASE_UART2_CLK_CLK_SEL(x) \
858
((x) << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT)
859
860
/* --- CGU_BASE_UART3_CLK values -------------------------------- */
861
862
/* PD: Output stage power down */
863
#define CGU_BASE_UART3_CLK_PD_SHIFT (0)
864
#define CGU_BASE_UART3_CLK_PD (1 << CGU_BASE_UART3_CLK_PD_SHIFT)
865
866
/* AUTOBLOCK: Block clock automatically during frequency change */
867
#define CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT (11)
868
#define CGU_BASE_UART3_CLK_AUTOBLOCK \
869
(1 << CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT)
870
871
/* CLK_SEL: Clock source selection */
872
#define CGU_BASE_UART3_CLK_CLK_SEL_SHIFT (24)
873
#define CGU_BASE_UART3_CLK_CLK_SEL_MASK \
874
(0x1f << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT)
875
#define CGU_BASE_UART3_CLK_CLK_SEL(x) \
876
((x) << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT)
877
878
/* --- CGU_BASE_OUT_CLK values ---------------------------------- */
879
880
/* PD: Output stage power down */
881
#define CGU_BASE_OUT_CLK_PD_SHIFT (0)
882
#define CGU_BASE_OUT_CLK_PD (1 << CGU_BASE_OUT_CLK_PD_SHIFT)
883
884
/* AUTOBLOCK: Block clock automatically during frequency change */
885
#define CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT (11)
886
#define CGU_BASE_OUT_CLK_AUTOBLOCK (1 << CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT)
887
888
/* CLK_SEL: Clock source selection */
889
#define CGU_BASE_OUT_CLK_CLK_SEL_SHIFT (24)
890
#define CGU_BASE_OUT_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT)
891
#define CGU_BASE_OUT_CLK_CLK_SEL(x) ((x) << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT)
892
893
/* --- CGU_BASE_APLL_CLK values --------------------------------- */
894
895
/* PD: Output stage power down */
896
#define CGU_BASE_APLL_CLK_PD_SHIFT (0)
897
#define CGU_BASE_APLL_CLK_PD (1 << CGU_BASE_APLL_CLK_PD_SHIFT)
898
899
/* AUTOBLOCK: Block clock automatically during frequency change */
900
#define CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT (11)
901
#define CGU_BASE_APLL_CLK_AUTOBLOCK (1 << CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT)
902
903
/* CLK_SEL: Clock source selection */
904
#define CGU_BASE_APLL_CLK_CLK_SEL_SHIFT (24)
905
#define CGU_BASE_APLL_CLK_CLK_SEL_MASK \
906
(0x1f << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT)
907
#define CGU_BASE_APLL_CLK_CLK_SEL(x) ((x) << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT)
908
909
/* --- CGU_BASE_CGU_OUT0_CLK values ----------------------------- */
910
911
/* PD: Output stage power down */
912
#define CGU_BASE_CGU_OUT0_CLK_PD_SHIFT (0)
913
#define CGU_BASE_CGU_OUT0_CLK_PD (1 << CGU_BASE_CGU_OUT0_CLK_PD_SHIFT)
914
915
/* AUTOBLOCK: Block clock automatically during frequency change */
916
#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT (11)
917
#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK \
918
(1 << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT)
919
920
/* CLK_SEL: Clock source selection */
921
#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT (24)
922
#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_MASK \
923
(0x1f << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT)
924
#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL(x) \
925
((x) << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT)
926
927
/* --- CGU_BASE_CGU_OUT1_CLK values ----------------------------- */
928
929
/* PD: Output stage power down */
930
#define CGU_BASE_CGU_OUT1_CLK_PD_SHIFT (0)
931
#define CGU_BASE_CGU_OUT1_CLK_PD (1 << CGU_BASE_CGU_OUT1_CLK_PD_SHIFT)
932
933
/* AUTOBLOCK: Block clock automatically during frequency change */
934
#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT (11)
935
#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK \
936
(1 << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT)
937
938
/* CLK_SEL: Clock source selection */
939
#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT (24)
940
#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_MASK \
941
(0x1f << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT)
942
#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL(x) \
943
((x) << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT)
944
945
/* --- CGU_BASE_x_CLK clock sources --------------------------------------- */
946
947
#define CGU_SRC_32K 0x00
948
#define CGU_SRC_IRC 0x01
949
#define CGU_SRC_ENET_RX 0x02
950
#define CGU_SRC_ENET_TX 0x03
951
#define CGU_SRC_GP_CLKIN 0x04
952
#define CGU_SRC_XTAL 0x06
953
#define CGU_SRC_PLL0USB 0x07
954
#define CGU_SRC_PLL0AUDIO 0x08
955
#define CGU_SRC_PLL1 0x09
956
#define CGU_SRC_IDIVA 0x0C
957
#define CGU_SRC_IDIVB 0x0D
958
#define CGU_SRC_IDIVC 0x0E
959
#define CGU_SRC_IDIVD 0x0F
960
#define CGU_SRC_IDIVE 0x10
961
962
/**@}*/
963
964
#endif
common.h
memorymap.h
include
libopencm3
lpc43xx
cgu.h
Generated on Tue Mar 7 2023 16:13:01 for libopencm3 by
1.9.4
1.9.4 1.9.4