Defined Constants and Types for the LPC43xx Clock Control Unit More...

Collaboration diagram for Clock Control Unit Defines:

Macros
#define	CCU1_PM MMIO32(CCU1_BASE + 0x000)

#define	CCU1_BASE_STAT MMIO32(CCU1_BASE + 0x004)

#define	CCU1_CLK_APB3_BUS_CFG MMIO32(CCU1_BASE + 0x100)

#define	CCU1_CLK_APB3_BUS_STAT MMIO32(CCU1_BASE + 0x104)

#define	CCU1_CLK_APB3_I2C1_CFG MMIO32(CCU1_BASE + 0x108)

#define	CCU1_CLK_APB3_I2C1_STAT MMIO32(CCU1_BASE + 0x10C)

#define	CCU1_CLK_APB3_DAC_CFG MMIO32(CCU1_BASE + 0x110)

#define	CCU1_CLK_APB3_DAC_STAT MMIO32(CCU1_BASE + 0x114)

#define	CCU1_CLK_APB3_ADC0_CFG MMIO32(CCU1_BASE + 0x118)

#define	CCU1_CLK_APB3_ADC0_STAT MMIO32(CCU1_BASE + 0x11C)

#define	CCU1_CLK_APB3_ADC1_CFG MMIO32(CCU1_BASE + 0x120)

#define	CCU1_CLK_APB3_ADC1_STAT MMIO32(CCU1_BASE + 0x124)

#define	CCU1_CLK_APB3_CAN0_CFG MMIO32(CCU1_BASE + 0x128)

#define	CCU1_CLK_APB3_CAN0_STAT MMIO32(CCU1_BASE + 0x12C)

#define	CCU1_CLK_APB1_BUS_CFG MMIO32(CCU1_BASE + 0x200)

#define	CCU1_CLK_APB1_BUS_STAT MMIO32(CCU1_BASE + 0x204)

#define	CCU1_CLK_APB1_MOTOCONPWM_CFG MMIO32(CCU1_BASE + 0x208)

#define	CCU1_CLK_APB1_MOTOCONPWM_STAT MMIO32(CCU1_BASE + 0x20C)

#define	CCU1_CLK_APB1_I2C0_CFG MMIO32(CCU1_BASE + 0x210)

#define	CCU1_CLK_APB1_I2C0_STAT MMIO32(CCU1_BASE + 0x214)

#define	CCU1_CLK_APB1_I2S_CFG MMIO32(CCU1_BASE + 0x218)

#define	CCU1_CLK_APB1_I2S_STAT MMIO32(CCU1_BASE + 0x21C)

#define	CCU1_CLK_APB1_CAN1_CFG MMIO32(CCU1_BASE + 0x220)

#define	CCU1_CLK_APB1_CAN1_STAT MMIO32(CCU1_BASE + 0x224)

#define	CCU1_CLK_SPIFI_CFG MMIO32(CCU1_BASE + 0x300)

#define	CCU1_CLK_SPIFI_STAT MMIO32(CCU1_BASE + 0x304)

#define	CCU1_CLK_M4_BUS_CFG MMIO32(CCU1_BASE + 0x400)

#define	CCU1_CLK_M4_BUS_STAT MMIO32(CCU1_BASE + 0x404)

#define	CCU1_CLK_M4_SPIFI_CFG MMIO32(CCU1_BASE + 0x408)

#define	CCU1_CLK_M4_SPIFI_STAT MMIO32(CCU1_BASE + 0x40C)

#define	CCU1_CLK_M4_GPIO_CFG MMIO32(CCU1_BASE + 0x410)

#define	CCU1_CLK_M4_GPIO_STAT MMIO32(CCU1_BASE + 0x414)

#define	CCU1_CLK_M4_LCD_CFG MMIO32(CCU1_BASE + 0x418)

#define	CCU1_CLK_M4_LCD_STAT MMIO32(CCU1_BASE + 0x41C)

#define	CCU1_CLK_M4_ETHERNET_CFG MMIO32(CCU1_BASE + 0x420)

#define	CCU1_CLK_M4_ETHERNET_STAT MMIO32(CCU1_BASE + 0x424)

#define	CCU1_CLK_M4_USB0_CFG MMIO32(CCU1_BASE + 0x428)

#define	CCU1_CLK_M4_USB0_STAT MMIO32(CCU1_BASE + 0x42C)

#define	CCU1_CLK_M4_EMC_CFG MMIO32(CCU1_BASE + 0x430)

#define	CCU1_CLK_M4_EMC_STAT MMIO32(CCU1_BASE + 0x434)

#define	CCU1_CLK_M4_SDIO_CFG MMIO32(CCU1_BASE + 0x438)

#define	CCU1_CLK_M4_SDIO_STAT MMIO32(CCU1_BASE + 0x43C)

#define	CCU1_CLK_M4_DMA_CFG MMIO32(CCU1_BASE + 0x440)

#define	CCU1_CLK_M4_DMA_STAT MMIO32(CCU1_BASE + 0x444)

#define	CCU1_CLK_M4_M4CORE_CFG MMIO32(CCU1_BASE + 0x448)

#define	CCU1_CLK_M4_M4CORE_STAT MMIO32(CCU1_BASE + 0x44C)

#define	CCU1_CLK_M4_SCT_CFG MMIO32(CCU1_BASE + 0x468)

#define	CCU1_CLK_M4_SCT_STAT MMIO32(CCU1_BASE + 0x46C)

#define	CCU1_CLK_M4_USB1_CFG MMIO32(CCU1_BASE + 0x470)

#define	CCU1_CLK_M4_USB1_STAT MMIO32(CCU1_BASE + 0x474)

#define	CCU1_CLK_M4_EMCDIV_CFG MMIO32(CCU1_BASE + 0x478)

#define	CCU1_CLK_M4_EMCDIV_STAT MMIO32(CCU1_BASE + 0x47C)

#define	CCU1_CLK_M4_M0APP_CFG MMIO32(CCU1_BASE + 0x490)

#define	CCU1_CLK_M4_M0APP_STAT MMIO32(CCU1_BASE + 0x494)

#define	CCU1_CLK_M4_VADC_CFG MMIO32(CCU1_BASE + 0x498)

#define	CCU1_CLK_M4_VADC_STAT MMIO32(CCU1_BASE + 0x49C)

#define	CCU1_CLK_M4_WWDT_CFG MMIO32(CCU1_BASE + 0x500)

#define	CCU1_CLK_M4_WWDT_STAT MMIO32(CCU1_BASE + 0x504)

#define	CCU1_CLK_M4_USART0_CFG MMIO32(CCU1_BASE + 0x508)

#define	CCU1_CLK_M4_USART0_STAT MMIO32(CCU1_BASE + 0x50C)

#define	CCU1_CLK_M4_UART1_CFG MMIO32(CCU1_BASE + 0x510)

#define	CCU1_CLK_M4_UART1_STAT MMIO32(CCU1_BASE + 0x514)

#define	CCU1_CLK_M4_SSP0_CFG MMIO32(CCU1_BASE + 0x518)

#define	CCU1_CLK_M4_SSP0_STAT MMIO32(CCU1_BASE + 0x51C)

#define	CCU1_CLK_M4_TIMER0_CFG MMIO32(CCU1_BASE + 0x520)

#define	CCU1_CLK_M4_TIMER0_STAT MMIO32(CCU1_BASE + 0x524)

#define	CCU1_CLK_M4_TIMER1_CFG MMIO32(CCU1_BASE + 0x528)

#define	CCU1_CLK_M4_TIMER1_STAT MMIO32(CCU1_BASE + 0x52C)

#define	CCU1_CLK_M4_SCU_CFG MMIO32(CCU1_BASE + 0x530)

#define	CCU1_CLK_M4_SCU_STAT MMIO32(CCU1_BASE + 0x534)

#define	CCU1_CLK_M4_CREG_CFG MMIO32(CCU1_BASE + 0x538)

#define	CCU1_CLK_M4_CREG_STAT MMIO32(CCU1_BASE + 0x53C)

#define	CCU1_CLK_M4_RITIMER_CFG MMIO32(CCU1_BASE + 0x600)

#define	CCU1_CLK_M4_RITIMER_STAT MMIO32(CCU1_BASE + 0x604)

#define	CCU1_CLK_M4_USART2_CFG MMIO32(CCU1_BASE + 0x608)

#define	CCU1_CLK_M4_USART2_STAT MMIO32(CCU1_BASE + 0x60C)

#define	CCU1_CLK_M4_USART3_CFG MMIO32(CCU1_BASE + 0x610)

#define	CCU1_CLK_M4_USART3_STAT MMIO32(CCU1_BASE + 0x614)

#define	CCU1_CLK_M4_TIMER2_CFG MMIO32(CCU1_BASE + 0x618)

#define	CCU1_CLK_M4_TIMER2_STAT MMIO32(CCU1_BASE + 0x61C)

#define	CCU1_CLK_M4_TIMER3_CFG MMIO32(CCU1_BASE + 0x620)

#define	CCU1_CLK_M4_TIMER3_STAT MMIO32(CCU1_BASE + 0x624)

#define	CCU1_CLK_M4_SSP1_CFG MMIO32(CCU1_BASE + 0x628)

#define	CCU1_CLK_M4_SSP1_STAT MMIO32(CCU1_BASE + 0x62C)

#define	CCU1_CLK_M4_QEI_CFG MMIO32(CCU1_BASE + 0x630)

#define	CCU1_CLK_M4_QEI_STAT MMIO32(CCU1_BASE + 0x634)

#define	CCU1_CLK_PERIPH_BUS_CFG MMIO32(CCU1_BASE + 0x700)

#define	CCU1_CLK_PERIPH_BUS_STAT MMIO32(CCU1_BASE + 0x704)

#define	CCU1_CLK_PERIPH_CORE_CFG MMIO32(CCU1_BASE + 0x710)

#define	CCU1_CLK_PERIPH_CORE_STAT MMIO32(CCU1_BASE + 0x714)

#define	CCU1_CLK_PERIPH_SGPIO_CFG MMIO32(CCU1_BASE + 0x718)

#define	CCU1_CLK_PERIPH_SGPIO_STAT MMIO32(CCU1_BASE + 0x71C)

#define	CCU1_CLK_USB0_CFG MMIO32(CCU1_BASE + 0x800)

#define	CCU1_CLK_USB0_STAT MMIO32(CCU1_BASE + 0x804)

#define	CCU1_CLK_USB1_CFG MMIO32(CCU1_BASE + 0x900)

#define	CCU1_CLK_USB1_STAT MMIO32(CCU1_BASE + 0x904)

#define	CCU1_CLK_SPI_CFG MMIO32(CCU1_BASE + 0xA00)

#define	CCU1_CLK_SPI_STAT MMIO32(CCU1_BASE + 0xA04)

#define	CCU1_CLK_VADC_CFG MMIO32(CCU1_BASE + 0xB00)

#define	CCU1_CLK_VADC_STAT MMIO32(CCU1_BASE + 0xB04)

#define	CCU2_PM MMIO32(CCU2_BASE + 0x000)

#define	CCU2_BASE_STAT MMIO32(CCU2_BASE + 0x004)

#define	CCU2_CLK_APLL_CFG MMIO32(CCU2_BASE + 0x100)

#define	CCU2_CLK_APLL_STAT MMIO32(CCU2_BASE + 0x104)

#define	CCU2_CLK_APB2_USART3_CFG MMIO32(CCU2_BASE + 0x200)

#define	CCU2_CLK_APB2_USART3_STAT MMIO32(CCU2_BASE + 0x204)

#define	CCU2_CLK_APB2_USART2_CFG MMIO32(CCU2_BASE + 0x300)

#define	CCU2_CLK_APB2_USART2_STAT MMIO32(CCU2_BASE + 0x304)

#define	CCU2_CLK_APB0_UART1_CFG MMIO32(CCU2_BASE + 0x400)

#define	CCU2_CLK_APB0_UART1_STAT MMIO32(CCU2_BASE + 0x404)

#define	CCU2_CLK_APB0_USART0_CFG MMIO32(CCU2_BASE + 0x500)

#define	CCU2_CLK_APB0_USART0_STAT MMIO32(CCU2_BASE + 0x504)

#define	CCU2_CLK_APB2_SSP1_CFG MMIO32(CCU2_BASE + 0x600)

#define	CCU2_CLK_APB2_SSP1_STAT MMIO32(CCU2_BASE + 0x604)

#define	CCU2_CLK_APB0_SSP0_CFG MMIO32(CCU2_BASE + 0x700)

#define	CCU2_CLK_APB0_SSP0_STAT MMIO32(CCU2_BASE + 0x704)

#define	CCU2_CLK_SDIO_CFG MMIO32(CCU2_BASE + 0x800)

#define	CCU2_CLK_SDIO_STAT MMIO32(CCU2_BASE + 0x804)

Detailed Description

Defined Constants and Types for the LPC43xx Clock Control Unit

Version: 1.0.0

Author: © 2012 Michael Ossmann mike@.nosp@m.ossm.nosp@m.ann.c.nosp@m.om

Date: 10 March 2013

LGPL License Terms libopencm3 License

Macro Definition Documentation

◆ CCU1_BASE_STAT

#define CCU1_BASE_STAT MMIO32(CCU1_BASE + 0x004)

Definition at line 48 of file ccu.h.

◆ CCU1_CLK_APB1_BUS_CFG

#define CCU1_CLK_APB1_BUS_CFG MMIO32(CCU1_BASE + 0x200)

Definition at line 87 of file ccu.h.

◆ CCU1_CLK_APB1_BUS_STAT

#define CCU1_CLK_APB1_BUS_STAT MMIO32(CCU1_BASE + 0x204)

Definition at line 90 of file ccu.h.

◆ CCU1_CLK_APB1_CAN1_CFG

#define CCU1_CLK_APB1_CAN1_CFG MMIO32(CCU1_BASE + 0x220)

Definition at line 111 of file ccu.h.

◆ CCU1_CLK_APB1_CAN1_STAT

#define CCU1_CLK_APB1_CAN1_STAT MMIO32(CCU1_BASE + 0x224)

Definition at line 114 of file ccu.h.

◆ CCU1_CLK_APB1_I2C0_CFG

#define CCU1_CLK_APB1_I2C0_CFG MMIO32(CCU1_BASE + 0x210)

Definition at line 99 of file ccu.h.

◆ CCU1_CLK_APB1_I2C0_STAT

#define CCU1_CLK_APB1_I2C0_STAT MMIO32(CCU1_BASE + 0x214)

Definition at line 102 of file ccu.h.

◆ CCU1_CLK_APB1_I2S_CFG

#define CCU1_CLK_APB1_I2S_CFG MMIO32(CCU1_BASE + 0x218)

Definition at line 105 of file ccu.h.

◆ CCU1_CLK_APB1_I2S_STAT

#define CCU1_CLK_APB1_I2S_STAT MMIO32(CCU1_BASE + 0x21C)

Definition at line 108 of file ccu.h.

◆ CCU1_CLK_APB1_MOTOCONPWM_CFG

#define CCU1_CLK_APB1_MOTOCONPWM_CFG MMIO32(CCU1_BASE + 0x208)

Definition at line 93 of file ccu.h.

◆ CCU1_CLK_APB1_MOTOCONPWM_STAT

#define CCU1_CLK_APB1_MOTOCONPWM_STAT MMIO32(CCU1_BASE + 0x20C)

Definition at line 96 of file ccu.h.

◆ CCU1_CLK_APB3_ADC0_CFG

#define CCU1_CLK_APB3_ADC0_CFG MMIO32(CCU1_BASE + 0x118)

Definition at line 69 of file ccu.h.

◆ CCU1_CLK_APB3_ADC0_STAT

#define CCU1_CLK_APB3_ADC0_STAT MMIO32(CCU1_BASE + 0x11C)

Definition at line 72 of file ccu.h.

◆ CCU1_CLK_APB3_ADC1_CFG

#define CCU1_CLK_APB3_ADC1_CFG MMIO32(CCU1_BASE + 0x120)

Definition at line 75 of file ccu.h.

◆ CCU1_CLK_APB3_ADC1_STAT

#define CCU1_CLK_APB3_ADC1_STAT MMIO32(CCU1_BASE + 0x124)

Definition at line 78 of file ccu.h.

◆ CCU1_CLK_APB3_BUS_CFG

#define CCU1_CLK_APB3_BUS_CFG MMIO32(CCU1_BASE + 0x100)

Definition at line 51 of file ccu.h.

◆ CCU1_CLK_APB3_BUS_STAT

#define CCU1_CLK_APB3_BUS_STAT MMIO32(CCU1_BASE + 0x104)

Definition at line 54 of file ccu.h.

◆ CCU1_CLK_APB3_CAN0_CFG

#define CCU1_CLK_APB3_CAN0_CFG MMIO32(CCU1_BASE + 0x128)

Definition at line 81 of file ccu.h.

◆ CCU1_CLK_APB3_CAN0_STAT

#define CCU1_CLK_APB3_CAN0_STAT MMIO32(CCU1_BASE + 0x12C)

Definition at line 84 of file ccu.h.

◆ CCU1_CLK_APB3_DAC_CFG

#define CCU1_CLK_APB3_DAC_CFG MMIO32(CCU1_BASE + 0x110)

Definition at line 63 of file ccu.h.

◆ CCU1_CLK_APB3_DAC_STAT

#define CCU1_CLK_APB3_DAC_STAT MMIO32(CCU1_BASE + 0x114)

Definition at line 66 of file ccu.h.

◆ CCU1_CLK_APB3_I2C1_CFG

#define CCU1_CLK_APB3_I2C1_CFG MMIO32(CCU1_BASE + 0x108)

Definition at line 57 of file ccu.h.

◆ CCU1_CLK_APB3_I2C1_STAT

#define CCU1_CLK_APB3_I2C1_STAT MMIO32(CCU1_BASE + 0x10C)

Definition at line 60 of file ccu.h.

◆ CCU1_CLK_M4_BUS_CFG

#define CCU1_CLK_M4_BUS_CFG MMIO32(CCU1_BASE + 0x400)

Definition at line 123 of file ccu.h.

◆ CCU1_CLK_M4_BUS_STAT

#define CCU1_CLK_M4_BUS_STAT MMIO32(CCU1_BASE + 0x404)

Definition at line 126 of file ccu.h.

◆ CCU1_CLK_M4_CREG_CFG

#define CCU1_CLK_M4_CREG_CFG MMIO32(CCU1_BASE + 0x538)

Definition at line 255 of file ccu.h.

◆ CCU1_CLK_M4_CREG_STAT

#define CCU1_CLK_M4_CREG_STAT MMIO32(CCU1_BASE + 0x53C)

Definition at line 258 of file ccu.h.

◆ CCU1_CLK_M4_DMA_CFG

#define CCU1_CLK_M4_DMA_CFG MMIO32(CCU1_BASE + 0x440)

Definition at line 171 of file ccu.h.

◆ CCU1_CLK_M4_DMA_STAT

#define CCU1_CLK_M4_DMA_STAT MMIO32(CCU1_BASE + 0x444)

Definition at line 174 of file ccu.h.

◆ CCU1_CLK_M4_EMC_CFG

#define CCU1_CLK_M4_EMC_CFG MMIO32(CCU1_BASE + 0x430)

Definition at line 159 of file ccu.h.

◆ CCU1_CLK_M4_EMC_STAT

#define CCU1_CLK_M4_EMC_STAT MMIO32(CCU1_BASE + 0x434)

Definition at line 162 of file ccu.h.

◆ CCU1_CLK_M4_EMCDIV_CFG

#define CCU1_CLK_M4_EMCDIV_CFG MMIO32(CCU1_BASE + 0x478)

Definition at line 195 of file ccu.h.

◆ CCU1_CLK_M4_EMCDIV_STAT

#define CCU1_CLK_M4_EMCDIV_STAT MMIO32(CCU1_BASE + 0x47C)

Definition at line 198 of file ccu.h.

◆ CCU1_CLK_M4_ETHERNET_CFG

#define CCU1_CLK_M4_ETHERNET_CFG MMIO32(CCU1_BASE + 0x420)

Definition at line 147 of file ccu.h.

◆ CCU1_CLK_M4_ETHERNET_STAT

#define CCU1_CLK_M4_ETHERNET_STAT MMIO32(CCU1_BASE + 0x424)

Definition at line 150 of file ccu.h.

◆ CCU1_CLK_M4_GPIO_CFG

#define CCU1_CLK_M4_GPIO_CFG MMIO32(CCU1_BASE + 0x410)

Definition at line 135 of file ccu.h.

◆ CCU1_CLK_M4_GPIO_STAT

#define CCU1_CLK_M4_GPIO_STAT MMIO32(CCU1_BASE + 0x414)

Definition at line 138 of file ccu.h.

◆ CCU1_CLK_M4_LCD_CFG

#define CCU1_CLK_M4_LCD_CFG MMIO32(CCU1_BASE + 0x418)

Definition at line 141 of file ccu.h.

◆ CCU1_CLK_M4_LCD_STAT

#define CCU1_CLK_M4_LCD_STAT MMIO32(CCU1_BASE + 0x41C)

Definition at line 144 of file ccu.h.

◆ CCU1_CLK_M4_M0APP_CFG

#define CCU1_CLK_M4_M0APP_CFG MMIO32(CCU1_BASE + 0x490)

Definition at line 201 of file ccu.h.

◆ CCU1_CLK_M4_M0APP_STAT

#define CCU1_CLK_M4_M0APP_STAT MMIO32(CCU1_BASE + 0x494)

Definition at line 204 of file ccu.h.

◆ CCU1_CLK_M4_M4CORE_CFG

#define CCU1_CLK_M4_M4CORE_CFG MMIO32(CCU1_BASE + 0x448)

Definition at line 177 of file ccu.h.

◆ CCU1_CLK_M4_M4CORE_STAT

#define CCU1_CLK_M4_M4CORE_STAT MMIO32(CCU1_BASE + 0x44C)

Definition at line 180 of file ccu.h.

◆ CCU1_CLK_M4_QEI_CFG

#define CCU1_CLK_M4_QEI_CFG MMIO32(CCU1_BASE + 0x630)

Definition at line 297 of file ccu.h.

◆ CCU1_CLK_M4_QEI_STAT

#define CCU1_CLK_M4_QEI_STAT MMIO32(CCU1_BASE + 0x634)

Definition at line 300 of file ccu.h.

◆ CCU1_CLK_M4_RITIMER_CFG

#define CCU1_CLK_M4_RITIMER_CFG MMIO32(CCU1_BASE + 0x600)

Definition at line 261 of file ccu.h.

◆ CCU1_CLK_M4_RITIMER_STAT

#define CCU1_CLK_M4_RITIMER_STAT MMIO32(CCU1_BASE + 0x604)

Definition at line 264 of file ccu.h.

◆ CCU1_CLK_M4_SCT_CFG

#define CCU1_CLK_M4_SCT_CFG MMIO32(CCU1_BASE + 0x468)

Definition at line 183 of file ccu.h.

◆ CCU1_CLK_M4_SCT_STAT

#define CCU1_CLK_M4_SCT_STAT MMIO32(CCU1_BASE + 0x46C)

Definition at line 186 of file ccu.h.

◆ CCU1_CLK_M4_SCU_CFG

#define CCU1_CLK_M4_SCU_CFG MMIO32(CCU1_BASE + 0x530)

Definition at line 249 of file ccu.h.

◆ CCU1_CLK_M4_SCU_STAT

#define CCU1_CLK_M4_SCU_STAT MMIO32(CCU1_BASE + 0x534)

Definition at line 252 of file ccu.h.

◆ CCU1_CLK_M4_SDIO_CFG

#define CCU1_CLK_M4_SDIO_CFG MMIO32(CCU1_BASE + 0x438)

Definition at line 165 of file ccu.h.

◆ CCU1_CLK_M4_SDIO_STAT

#define CCU1_CLK_M4_SDIO_STAT MMIO32(CCU1_BASE + 0x43C)

Definition at line 168 of file ccu.h.

◆ CCU1_CLK_M4_SPIFI_CFG

#define CCU1_CLK_M4_SPIFI_CFG MMIO32(CCU1_BASE + 0x408)

Definition at line 129 of file ccu.h.

◆ CCU1_CLK_M4_SPIFI_STAT

#define CCU1_CLK_M4_SPIFI_STAT MMIO32(CCU1_BASE + 0x40C)

Definition at line 132 of file ccu.h.

◆ CCU1_CLK_M4_SSP0_CFG

#define CCU1_CLK_M4_SSP0_CFG MMIO32(CCU1_BASE + 0x518)

Definition at line 231 of file ccu.h.

◆ CCU1_CLK_M4_SSP0_STAT

#define CCU1_CLK_M4_SSP0_STAT MMIO32(CCU1_BASE + 0x51C)

Definition at line 234 of file ccu.h.

◆ CCU1_CLK_M4_SSP1_CFG

#define CCU1_CLK_M4_SSP1_CFG MMIO32(CCU1_BASE + 0x628)

Definition at line 291 of file ccu.h.

◆ CCU1_CLK_M4_SSP1_STAT

#define CCU1_CLK_M4_SSP1_STAT MMIO32(CCU1_BASE + 0x62C)

Definition at line 294 of file ccu.h.

◆ CCU1_CLK_M4_TIMER0_CFG

#define CCU1_CLK_M4_TIMER0_CFG MMIO32(CCU1_BASE + 0x520)

Definition at line 237 of file ccu.h.

◆ CCU1_CLK_M4_TIMER0_STAT

#define CCU1_CLK_M4_TIMER0_STAT MMIO32(CCU1_BASE + 0x524)

Definition at line 240 of file ccu.h.

◆ CCU1_CLK_M4_TIMER1_CFG

#define CCU1_CLK_M4_TIMER1_CFG MMIO32(CCU1_BASE + 0x528)

Definition at line 243 of file ccu.h.

◆ CCU1_CLK_M4_TIMER1_STAT

#define CCU1_CLK_M4_TIMER1_STAT MMIO32(CCU1_BASE + 0x52C)

Definition at line 246 of file ccu.h.

◆ CCU1_CLK_M4_TIMER2_CFG

#define CCU1_CLK_M4_TIMER2_CFG MMIO32(CCU1_BASE + 0x618)

Definition at line 279 of file ccu.h.

◆ CCU1_CLK_M4_TIMER2_STAT

#define CCU1_CLK_M4_TIMER2_STAT MMIO32(CCU1_BASE + 0x61C)

Definition at line 282 of file ccu.h.

◆ CCU1_CLK_M4_TIMER3_CFG

#define CCU1_CLK_M4_TIMER3_CFG MMIO32(CCU1_BASE + 0x620)

Definition at line 285 of file ccu.h.

◆ CCU1_CLK_M4_TIMER3_STAT

#define CCU1_CLK_M4_TIMER3_STAT MMIO32(CCU1_BASE + 0x624)

Definition at line 288 of file ccu.h.

◆ CCU1_CLK_M4_UART1_CFG

#define CCU1_CLK_M4_UART1_CFG MMIO32(CCU1_BASE + 0x510)

Definition at line 225 of file ccu.h.

◆ CCU1_CLK_M4_UART1_STAT

#define CCU1_CLK_M4_UART1_STAT MMIO32(CCU1_BASE + 0x514)

Definition at line 228 of file ccu.h.

◆ CCU1_CLK_M4_USART0_CFG

#define CCU1_CLK_M4_USART0_CFG MMIO32(CCU1_BASE + 0x508)

Definition at line 219 of file ccu.h.

◆ CCU1_CLK_M4_USART0_STAT

#define CCU1_CLK_M4_USART0_STAT MMIO32(CCU1_BASE + 0x50C)

Definition at line 222 of file ccu.h.

◆ CCU1_CLK_M4_USART2_CFG

#define CCU1_CLK_M4_USART2_CFG MMIO32(CCU1_BASE + 0x608)

Definition at line 267 of file ccu.h.

◆ CCU1_CLK_M4_USART2_STAT

#define CCU1_CLK_M4_USART2_STAT MMIO32(CCU1_BASE + 0x60C)

Definition at line 270 of file ccu.h.

◆ CCU1_CLK_M4_USART3_CFG

#define CCU1_CLK_M4_USART3_CFG MMIO32(CCU1_BASE + 0x610)

Definition at line 273 of file ccu.h.

◆ CCU1_CLK_M4_USART3_STAT

#define CCU1_CLK_M4_USART3_STAT MMIO32(CCU1_BASE + 0x614)

Definition at line 276 of file ccu.h.

◆ CCU1_CLK_M4_USB0_CFG

#define CCU1_CLK_M4_USB0_CFG MMIO32(CCU1_BASE + 0x428)

Definition at line 153 of file ccu.h.

◆ CCU1_CLK_M4_USB0_STAT

#define CCU1_CLK_M4_USB0_STAT MMIO32(CCU1_BASE + 0x42C)

Definition at line 156 of file ccu.h.

◆ CCU1_CLK_M4_USB1_CFG

#define CCU1_CLK_M4_USB1_CFG MMIO32(CCU1_BASE + 0x470)

Definition at line 189 of file ccu.h.

◆ CCU1_CLK_M4_USB1_STAT

#define CCU1_CLK_M4_USB1_STAT MMIO32(CCU1_BASE + 0x474)

Definition at line 192 of file ccu.h.

◆ CCU1_CLK_M4_VADC_CFG

#define CCU1_CLK_M4_VADC_CFG MMIO32(CCU1_BASE + 0x498)

Definition at line 207 of file ccu.h.

◆ CCU1_CLK_M4_VADC_STAT

#define CCU1_CLK_M4_VADC_STAT MMIO32(CCU1_BASE + 0x49C)

Definition at line 210 of file ccu.h.

◆ CCU1_CLK_M4_WWDT_CFG

#define CCU1_CLK_M4_WWDT_CFG MMIO32(CCU1_BASE + 0x500)

Definition at line 213 of file ccu.h.

◆ CCU1_CLK_M4_WWDT_STAT

#define CCU1_CLK_M4_WWDT_STAT MMIO32(CCU1_BASE + 0x504)

Definition at line 216 of file ccu.h.

◆ CCU1_CLK_PERIPH_BUS_CFG

#define CCU1_CLK_PERIPH_BUS_CFG MMIO32(CCU1_BASE + 0x700)

Definition at line 303 of file ccu.h.

◆ CCU1_CLK_PERIPH_BUS_STAT

#define CCU1_CLK_PERIPH_BUS_STAT MMIO32(CCU1_BASE + 0x704)

Definition at line 306 of file ccu.h.

◆ CCU1_CLK_PERIPH_CORE_CFG

#define CCU1_CLK_PERIPH_CORE_CFG MMIO32(CCU1_BASE + 0x710)

Definition at line 309 of file ccu.h.

◆ CCU1_CLK_PERIPH_CORE_STAT

#define CCU1_CLK_PERIPH_CORE_STAT MMIO32(CCU1_BASE + 0x714)

Definition at line 312 of file ccu.h.

◆ CCU1_CLK_PERIPH_SGPIO_CFG

#define CCU1_CLK_PERIPH_SGPIO_CFG MMIO32(CCU1_BASE + 0x718)

Definition at line 315 of file ccu.h.

◆ CCU1_CLK_PERIPH_SGPIO_STAT

#define CCU1_CLK_PERIPH_SGPIO_STAT MMIO32(CCU1_BASE + 0x71C)

Definition at line 318 of file ccu.h.

◆ CCU1_CLK_SPI_CFG

#define CCU1_CLK_SPI_CFG MMIO32(CCU1_BASE + 0xA00)

Definition at line 333 of file ccu.h.

◆ CCU1_CLK_SPI_STAT

#define CCU1_CLK_SPI_STAT MMIO32(CCU1_BASE + 0xA04)

Definition at line 336 of file ccu.h.

◆ CCU1_CLK_SPIFI_CFG

#define CCU1_CLK_SPIFI_CFG MMIO32(CCU1_BASE + 0x300)

Definition at line 117 of file ccu.h.

◆ CCU1_CLK_SPIFI_STAT

#define CCU1_CLK_SPIFI_STAT MMIO32(CCU1_BASE + 0x304)

Definition at line 120 of file ccu.h.

◆ CCU1_CLK_USB0_CFG

#define CCU1_CLK_USB0_CFG MMIO32(CCU1_BASE + 0x800)

Definition at line 321 of file ccu.h.

◆ CCU1_CLK_USB0_STAT

#define CCU1_CLK_USB0_STAT MMIO32(CCU1_BASE + 0x804)

Definition at line 324 of file ccu.h.

◆ CCU1_CLK_USB1_CFG

#define CCU1_CLK_USB1_CFG MMIO32(CCU1_BASE + 0x900)

Definition at line 327 of file ccu.h.

◆ CCU1_CLK_USB1_STAT

#define CCU1_CLK_USB1_STAT MMIO32(CCU1_BASE + 0x904)

Definition at line 330 of file ccu.h.

◆ CCU1_CLK_VADC_CFG

#define CCU1_CLK_VADC_CFG MMIO32(CCU1_BASE + 0xB00)

Definition at line 339 of file ccu.h.

◆ CCU1_CLK_VADC_STAT

#define CCU1_CLK_VADC_STAT MMIO32(CCU1_BASE + 0xB04)

Definition at line 342 of file ccu.h.

◆ CCU1_PM

#define CCU1_PM MMIO32(CCU1_BASE + 0x000)

Definition at line 45 of file ccu.h.

◆ CCU2_BASE_STAT

#define CCU2_BASE_STAT MMIO32(CCU2_BASE + 0x004)

Definition at line 350 of file ccu.h.

◆ CCU2_CLK_APB0_SSP0_CFG

#define CCU2_CLK_APB0_SSP0_CFG MMIO32(CCU2_BASE + 0x700)

Definition at line 389 of file ccu.h.

◆ CCU2_CLK_APB0_SSP0_STAT

#define CCU2_CLK_APB0_SSP0_STAT MMIO32(CCU2_BASE + 0x704)

Definition at line 392 of file ccu.h.

◆ CCU2_CLK_APB0_UART1_CFG

#define CCU2_CLK_APB0_UART1_CFG MMIO32(CCU2_BASE + 0x400)

Definition at line 371 of file ccu.h.

◆ CCU2_CLK_APB0_UART1_STAT

#define CCU2_CLK_APB0_UART1_STAT MMIO32(CCU2_BASE + 0x404)

Definition at line 374 of file ccu.h.

◆ CCU2_CLK_APB0_USART0_CFG

#define CCU2_CLK_APB0_USART0_CFG MMIO32(CCU2_BASE + 0x500)

Definition at line 377 of file ccu.h.

◆ CCU2_CLK_APB0_USART0_STAT

#define CCU2_CLK_APB0_USART0_STAT MMIO32(CCU2_BASE + 0x504)

Definition at line 380 of file ccu.h.

◆ CCU2_CLK_APB2_SSP1_CFG

#define CCU2_CLK_APB2_SSP1_CFG MMIO32(CCU2_BASE + 0x600)

Definition at line 383 of file ccu.h.

◆ CCU2_CLK_APB2_SSP1_STAT

#define CCU2_CLK_APB2_SSP1_STAT MMIO32(CCU2_BASE + 0x604)

Definition at line 386 of file ccu.h.

◆ CCU2_CLK_APB2_USART2_CFG

#define CCU2_CLK_APB2_USART2_CFG MMIO32(CCU2_BASE + 0x300)

Definition at line 365 of file ccu.h.

◆ CCU2_CLK_APB2_USART2_STAT

#define CCU2_CLK_APB2_USART2_STAT MMIO32(CCU2_BASE + 0x304)

Definition at line 368 of file ccu.h.

◆ CCU2_CLK_APB2_USART3_CFG

#define CCU2_CLK_APB2_USART3_CFG MMIO32(CCU2_BASE + 0x200)

Definition at line 359 of file ccu.h.

◆ CCU2_CLK_APB2_USART3_STAT

#define CCU2_CLK_APB2_USART3_STAT MMIO32(CCU2_BASE + 0x204)

Definition at line 362 of file ccu.h.

◆ CCU2_CLK_APLL_CFG

#define CCU2_CLK_APLL_CFG MMIO32(CCU2_BASE + 0x100)

Definition at line 353 of file ccu.h.

◆ CCU2_CLK_APLL_STAT

#define CCU2_CLK_APLL_STAT MMIO32(CCU2_BASE + 0x104)

Definition at line 356 of file ccu.h.

◆ CCU2_CLK_SDIO_CFG

#define CCU2_CLK_SDIO_CFG MMIO32(CCU2_BASE + 0x800)

Definition at line 395 of file ccu.h.

◆ CCU2_CLK_SDIO_STAT

#define CCU2_CLK_SDIO_STAT MMIO32(CCU2_BASE + 0x804)

Definition at line 398 of file ccu.h.

◆ CCU2_PM

#define CCU2_PM MMIO32(CCU2_BASE + 0x000)

Definition at line 347 of file ccu.h.

Macros