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| #define | CCU1_PM MMIO32(CCU1_BASE + 0x000) |
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| #define | CCU1_BASE_STAT MMIO32(CCU1_BASE + 0x004) |
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| #define | CCU1_CLK_APB3_BUS_CFG MMIO32(CCU1_BASE + 0x100) |
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| #define | CCU1_CLK_APB3_BUS_STAT MMIO32(CCU1_BASE + 0x104) |
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| #define | CCU1_CLK_APB3_I2C1_CFG MMIO32(CCU1_BASE + 0x108) |
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| #define | CCU1_CLK_APB3_I2C1_STAT MMIO32(CCU1_BASE + 0x10C) |
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| #define | CCU1_CLK_APB3_DAC_CFG MMIO32(CCU1_BASE + 0x110) |
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| #define | CCU1_CLK_APB3_DAC_STAT MMIO32(CCU1_BASE + 0x114) |
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| #define | CCU1_CLK_APB3_ADC0_CFG MMIO32(CCU1_BASE + 0x118) |
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| #define | CCU1_CLK_APB3_ADC0_STAT MMIO32(CCU1_BASE + 0x11C) |
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| #define | CCU1_CLK_APB3_ADC1_CFG MMIO32(CCU1_BASE + 0x120) |
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| #define | CCU1_CLK_APB3_ADC1_STAT MMIO32(CCU1_BASE + 0x124) |
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| #define | CCU1_CLK_APB3_CAN0_CFG MMIO32(CCU1_BASE + 0x128) |
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| #define | CCU1_CLK_APB3_CAN0_STAT MMIO32(CCU1_BASE + 0x12C) |
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| #define | CCU1_CLK_APB1_BUS_CFG MMIO32(CCU1_BASE + 0x200) |
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| #define | CCU1_CLK_APB1_BUS_STAT MMIO32(CCU1_BASE + 0x204) |
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| #define | CCU1_CLK_APB1_MOTOCONPWM_CFG MMIO32(CCU1_BASE + 0x208) |
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| #define | CCU1_CLK_APB1_MOTOCONPWM_STAT MMIO32(CCU1_BASE + 0x20C) |
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| #define | CCU1_CLK_APB1_I2C0_CFG MMIO32(CCU1_BASE + 0x210) |
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| #define | CCU1_CLK_APB1_I2C0_STAT MMIO32(CCU1_BASE + 0x214) |
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| #define | CCU1_CLK_APB1_I2S_CFG MMIO32(CCU1_BASE + 0x218) |
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| #define | CCU1_CLK_APB1_I2S_STAT MMIO32(CCU1_BASE + 0x21C) |
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| #define | CCU1_CLK_APB1_CAN1_CFG MMIO32(CCU1_BASE + 0x220) |
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| #define | CCU1_CLK_APB1_CAN1_STAT MMIO32(CCU1_BASE + 0x224) |
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| #define | CCU1_CLK_SPIFI_CFG MMIO32(CCU1_BASE + 0x300) |
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| #define | CCU1_CLK_SPIFI_STAT MMIO32(CCU1_BASE + 0x304) |
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| #define | CCU1_CLK_M4_BUS_CFG MMIO32(CCU1_BASE + 0x400) |
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| #define | CCU1_CLK_M4_BUS_STAT MMIO32(CCU1_BASE + 0x404) |
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| #define | CCU1_CLK_M4_SPIFI_CFG MMIO32(CCU1_BASE + 0x408) |
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| #define | CCU1_CLK_M4_SPIFI_STAT MMIO32(CCU1_BASE + 0x40C) |
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| #define | CCU1_CLK_M4_GPIO_CFG MMIO32(CCU1_BASE + 0x410) |
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| #define | CCU1_CLK_M4_GPIO_STAT MMIO32(CCU1_BASE + 0x414) |
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| #define | CCU1_CLK_M4_LCD_CFG MMIO32(CCU1_BASE + 0x418) |
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| #define | CCU1_CLK_M4_LCD_STAT MMIO32(CCU1_BASE + 0x41C) |
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| #define | CCU1_CLK_M4_ETHERNET_CFG MMIO32(CCU1_BASE + 0x420) |
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| #define | CCU1_CLK_M4_ETHERNET_STAT MMIO32(CCU1_BASE + 0x424) |
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| #define | CCU1_CLK_M4_USB0_CFG MMIO32(CCU1_BASE + 0x428) |
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| #define | CCU1_CLK_M4_USB0_STAT MMIO32(CCU1_BASE + 0x42C) |
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| #define | CCU1_CLK_M4_EMC_CFG MMIO32(CCU1_BASE + 0x430) |
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| #define | CCU1_CLK_M4_EMC_STAT MMIO32(CCU1_BASE + 0x434) |
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| #define | CCU1_CLK_M4_SDIO_CFG MMIO32(CCU1_BASE + 0x438) |
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| #define | CCU1_CLK_M4_SDIO_STAT MMIO32(CCU1_BASE + 0x43C) |
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| #define | CCU1_CLK_M4_DMA_CFG MMIO32(CCU1_BASE + 0x440) |
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| #define | CCU1_CLK_M4_DMA_STAT MMIO32(CCU1_BASE + 0x444) |
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| #define | CCU1_CLK_M4_M4CORE_CFG MMIO32(CCU1_BASE + 0x448) |
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| #define | CCU1_CLK_M4_M4CORE_STAT MMIO32(CCU1_BASE + 0x44C) |
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| #define | CCU1_CLK_M4_SCT_CFG MMIO32(CCU1_BASE + 0x468) |
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| #define | CCU1_CLK_M4_SCT_STAT MMIO32(CCU1_BASE + 0x46C) |
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| #define | CCU1_CLK_M4_USB1_CFG MMIO32(CCU1_BASE + 0x470) |
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| #define | CCU1_CLK_M4_USB1_STAT MMIO32(CCU1_BASE + 0x474) |
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| #define | CCU1_CLK_M4_EMCDIV_CFG MMIO32(CCU1_BASE + 0x478) |
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| #define | CCU1_CLK_M4_EMCDIV_STAT MMIO32(CCU1_BASE + 0x47C) |
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| #define | CCU1_CLK_M4_M0APP_CFG MMIO32(CCU1_BASE + 0x490) |
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| #define | CCU1_CLK_M4_M0APP_STAT MMIO32(CCU1_BASE + 0x494) |
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| #define | CCU1_CLK_M4_VADC_CFG MMIO32(CCU1_BASE + 0x498) |
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| #define | CCU1_CLK_M4_VADC_STAT MMIO32(CCU1_BASE + 0x49C) |
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| #define | CCU1_CLK_M4_WWDT_CFG MMIO32(CCU1_BASE + 0x500) |
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| #define | CCU1_CLK_M4_WWDT_STAT MMIO32(CCU1_BASE + 0x504) |
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| #define | CCU1_CLK_M4_USART0_CFG MMIO32(CCU1_BASE + 0x508) |
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| #define | CCU1_CLK_M4_USART0_STAT MMIO32(CCU1_BASE + 0x50C) |
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| #define | CCU1_CLK_M4_UART1_CFG MMIO32(CCU1_BASE + 0x510) |
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| #define | CCU1_CLK_M4_UART1_STAT MMIO32(CCU1_BASE + 0x514) |
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| #define | CCU1_CLK_M4_SSP0_CFG MMIO32(CCU1_BASE + 0x518) |
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| #define | CCU1_CLK_M4_SSP0_STAT MMIO32(CCU1_BASE + 0x51C) |
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| #define | CCU1_CLK_M4_TIMER0_CFG MMIO32(CCU1_BASE + 0x520) |
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| #define | CCU1_CLK_M4_TIMER0_STAT MMIO32(CCU1_BASE + 0x524) |
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| #define | CCU1_CLK_M4_TIMER1_CFG MMIO32(CCU1_BASE + 0x528) |
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| #define | CCU1_CLK_M4_TIMER1_STAT MMIO32(CCU1_BASE + 0x52C) |
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| #define | CCU1_CLK_M4_SCU_CFG MMIO32(CCU1_BASE + 0x530) |
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| #define | CCU1_CLK_M4_SCU_STAT MMIO32(CCU1_BASE + 0x534) |
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| #define | CCU1_CLK_M4_CREG_CFG MMIO32(CCU1_BASE + 0x538) |
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| #define | CCU1_CLK_M4_CREG_STAT MMIO32(CCU1_BASE + 0x53C) |
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| #define | CCU1_CLK_M4_RITIMER_CFG MMIO32(CCU1_BASE + 0x600) |
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| #define | CCU1_CLK_M4_RITIMER_STAT MMIO32(CCU1_BASE + 0x604) |
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| #define | CCU1_CLK_M4_USART2_CFG MMIO32(CCU1_BASE + 0x608) |
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| #define | CCU1_CLK_M4_USART2_STAT MMIO32(CCU1_BASE + 0x60C) |
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| #define | CCU1_CLK_M4_USART3_CFG MMIO32(CCU1_BASE + 0x610) |
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| #define | CCU1_CLK_M4_USART3_STAT MMIO32(CCU1_BASE + 0x614) |
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| #define | CCU1_CLK_M4_TIMER2_CFG MMIO32(CCU1_BASE + 0x618) |
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| #define | CCU1_CLK_M4_TIMER2_STAT MMIO32(CCU1_BASE + 0x61C) |
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| #define | CCU1_CLK_M4_TIMER3_CFG MMIO32(CCU1_BASE + 0x620) |
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| #define | CCU1_CLK_M4_TIMER3_STAT MMIO32(CCU1_BASE + 0x624) |
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| #define | CCU1_CLK_M4_SSP1_CFG MMIO32(CCU1_BASE + 0x628) |
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| #define | CCU1_CLK_M4_SSP1_STAT MMIO32(CCU1_BASE + 0x62C) |
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| #define | CCU1_CLK_M4_QEI_CFG MMIO32(CCU1_BASE + 0x630) |
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| #define | CCU1_CLK_M4_QEI_STAT MMIO32(CCU1_BASE + 0x634) |
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| #define | CCU1_CLK_PERIPH_BUS_CFG MMIO32(CCU1_BASE + 0x700) |
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| #define | CCU1_CLK_PERIPH_BUS_STAT MMIO32(CCU1_BASE + 0x704) |
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| #define | CCU1_CLK_PERIPH_CORE_CFG MMIO32(CCU1_BASE + 0x710) |
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| #define | CCU1_CLK_PERIPH_CORE_STAT MMIO32(CCU1_BASE + 0x714) |
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| #define | CCU1_CLK_PERIPH_SGPIO_CFG MMIO32(CCU1_BASE + 0x718) |
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| #define | CCU1_CLK_PERIPH_SGPIO_STAT MMIO32(CCU1_BASE + 0x71C) |
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| #define | CCU1_CLK_USB0_CFG MMIO32(CCU1_BASE + 0x800) |
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| #define | CCU1_CLK_USB0_STAT MMIO32(CCU1_BASE + 0x804) |
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| #define | CCU1_CLK_USB1_CFG MMIO32(CCU1_BASE + 0x900) |
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| #define | CCU1_CLK_USB1_STAT MMIO32(CCU1_BASE + 0x904) |
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| #define | CCU1_CLK_SPI_CFG MMIO32(CCU1_BASE + 0xA00) |
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| #define | CCU1_CLK_SPI_STAT MMIO32(CCU1_BASE + 0xA04) |
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| #define | CCU1_CLK_VADC_CFG MMIO32(CCU1_BASE + 0xB00) |
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| #define | CCU1_CLK_VADC_STAT MMIO32(CCU1_BASE + 0xB04) |
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| #define | CCU2_PM MMIO32(CCU2_BASE + 0x000) |
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| #define | CCU2_BASE_STAT MMIO32(CCU2_BASE + 0x004) |
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| #define | CCU2_CLK_APLL_CFG MMIO32(CCU2_BASE + 0x100) |
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| #define | CCU2_CLK_APLL_STAT MMIO32(CCU2_BASE + 0x104) |
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| #define | CCU2_CLK_APB2_USART3_CFG MMIO32(CCU2_BASE + 0x200) |
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| #define | CCU2_CLK_APB2_USART3_STAT MMIO32(CCU2_BASE + 0x204) |
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| #define | CCU2_CLK_APB2_USART2_CFG MMIO32(CCU2_BASE + 0x300) |
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| #define | CCU2_CLK_APB2_USART2_STAT MMIO32(CCU2_BASE + 0x304) |
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| #define | CCU2_CLK_APB0_UART1_CFG MMIO32(CCU2_BASE + 0x400) |
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| #define | CCU2_CLK_APB0_UART1_STAT MMIO32(CCU2_BASE + 0x404) |
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| #define | CCU2_CLK_APB0_USART0_CFG MMIO32(CCU2_BASE + 0x500) |
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| #define | CCU2_CLK_APB0_USART0_STAT MMIO32(CCU2_BASE + 0x504) |
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| #define | CCU2_CLK_APB2_SSP1_CFG MMIO32(CCU2_BASE + 0x600) |
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| #define | CCU2_CLK_APB2_SSP1_STAT MMIO32(CCU2_BASE + 0x604) |
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| #define | CCU2_CLK_APB0_SSP0_CFG MMIO32(CCU2_BASE + 0x700) |
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| #define | CCU2_CLK_APB0_SSP0_STAT MMIO32(CCU2_BASE + 0x704) |
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| #define | CCU2_CLK_SDIO_CFG MMIO32(CCU2_BASE + 0x800) |
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| #define | CCU2_CLK_SDIO_STAT MMIO32(CCU2_BASE + 0x804) |
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