libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
ccu.h
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1/** @defgroup ccu_defines Clock Control Unit Defines
2
3@brief <b>Defined Constants and Types for the LPC43xx Clock Control Unit</b>
4
5@ingroup LPC43xx_defines
6
7@version 1.0.0
8
9@author @htmlonly &copy; @endhtmlonly 2012 Michael Ossmann <mike@ossmann.com>
10
11@date 10 March 2013
12
13LGPL License Terms @ref lgpl_license
14 */
15/*
16 * This file is part of the libopencm3 project.
17 *
18 * Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
19 *
20 * This library is free software: you can redistribute it and/or modify
21 * it under the terms of the GNU Lesser General Public License as published by
22 * the Free Software Foundation, either version 3 of the License, or
23 * (at your option) any later version.
24 *
25 * This library is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU Lesser General Public License for more details.
29 *
30 * You should have received a copy of the GNU Lesser General Public License
31 * along with this library. If not, see <http://www.gnu.org/licenses/>.
32 */
33
34#ifndef LPC43XX_CCU_H
35#define LPC43XX_CCU_H
36
37/**@{*/
38
39#include <libopencm3/cm3/common.h>
40#include <libopencm3/lpc43xx/memorymap.h>
41
42/* --- CCU1 registers ------------------------------------------------------ */
43
44/* CCU1 power mode register */
45#define CCU1_PM MMIO32(CCU1_BASE + 0x000)
46
47/* CCU1 base clock status register */
48#define CCU1_BASE_STAT MMIO32(CCU1_BASE + 0x004)
49
50/* CLK_APB3_BUS clock configuration register */
51#define CCU1_CLK_APB3_BUS_CFG MMIO32(CCU1_BASE + 0x100)
52
53/* CLK_APB3_BUS clock status register */
54#define CCU1_CLK_APB3_BUS_STAT MMIO32(CCU1_BASE + 0x104)
55
56/* CLK_APB3_I2C1 configuration register */
57#define CCU1_CLK_APB3_I2C1_CFG MMIO32(CCU1_BASE + 0x108)
58
59/* CLK_APB3_I2C1 status register */
60#define CCU1_CLK_APB3_I2C1_STAT MMIO32(CCU1_BASE + 0x10C)
61
62/* CLK_APB3_DAC configuration register */
63#define CCU1_CLK_APB3_DAC_CFG MMIO32(CCU1_BASE + 0x110)
64
65/* CLK_APB3_DAC status register */
66#define CCU1_CLK_APB3_DAC_STAT MMIO32(CCU1_BASE + 0x114)
67
68/* CLK_APB3_ADC0 configuration register */
69#define CCU1_CLK_APB3_ADC0_CFG MMIO32(CCU1_BASE + 0x118)
70
71/* CLK_APB3_ADC0 status register */
72#define CCU1_CLK_APB3_ADC0_STAT MMIO32(CCU1_BASE + 0x11C)
73
74/* CLK_APB3_ADC1 configuration register */
75#define CCU1_CLK_APB3_ADC1_CFG MMIO32(CCU1_BASE + 0x120)
76
77/* CLK_APB3_ADC1 status register */
78#define CCU1_CLK_APB3_ADC1_STAT MMIO32(CCU1_BASE + 0x124)
79
80/* CLK_APB3_CAN0 configuration register */
81#define CCU1_CLK_APB3_CAN0_CFG MMIO32(CCU1_BASE + 0x128)
82
83/* CLK_APB3_CAN0 status register */
84#define CCU1_CLK_APB3_CAN0_STAT MMIO32(CCU1_BASE + 0x12C)
85
86/* CLK_APB1_BUS configuration register */
87#define CCU1_CLK_APB1_BUS_CFG MMIO32(CCU1_BASE + 0x200)
88
89/* CLK_APB1_BUS status register */
90#define CCU1_CLK_APB1_BUS_STAT MMIO32(CCU1_BASE + 0x204)
91
92/* CLK_APB1_MOTOCON configuration register */
93#define CCU1_CLK_APB1_MOTOCONPWM_CFG MMIO32(CCU1_BASE + 0x208)
94
95/* CLK_APB1_MOTOCON status register */
96#define CCU1_CLK_APB1_MOTOCONPWM_STAT MMIO32(CCU1_BASE + 0x20C)
97
98/* CLK_APB1_I2C0 configuration register */
99#define CCU1_CLK_APB1_I2C0_CFG MMIO32(CCU1_BASE + 0x210)
100
101/* CLK_APB1_I2C0 status register */
102#define CCU1_CLK_APB1_I2C0_STAT MMIO32(CCU1_BASE + 0x214)
103
104/* CLK_APB1_I2S configuration register */
105#define CCU1_CLK_APB1_I2S_CFG MMIO32(CCU1_BASE + 0x218)
106
107/* CLK_APB1_I2S status register */
108#define CCU1_CLK_APB1_I2S_STAT MMIO32(CCU1_BASE + 0x21C)
109
110/* CLK_APB3_CAN1 configuration register */
111#define CCU1_CLK_APB1_CAN1_CFG MMIO32(CCU1_BASE + 0x220)
112
113/* CLK_APB3_CAN1 status register */
114#define CCU1_CLK_APB1_CAN1_STAT MMIO32(CCU1_BASE + 0x224)
115
116/* CLK_SPIFI configuration register */
117#define CCU1_CLK_SPIFI_CFG MMIO32(CCU1_BASE + 0x300)
118
119/* CLK_SPIFI status register */
120#define CCU1_CLK_SPIFI_STAT MMIO32(CCU1_BASE + 0x304)
121
122/* CLK_M4_BUS configuration register */
123#define CCU1_CLK_M4_BUS_CFG MMIO32(CCU1_BASE + 0x400)
124
125/* CLK_M4_BUS status register */
126#define CCU1_CLK_M4_BUS_STAT MMIO32(CCU1_BASE + 0x404)
127
128/* CLK_M4_SPIFI configuration register */
129#define CCU1_CLK_M4_SPIFI_CFG MMIO32(CCU1_BASE + 0x408)
130
131/* CLK_M4_SPIFI status register */
132#define CCU1_CLK_M4_SPIFI_STAT MMIO32(CCU1_BASE + 0x40C)
133
134/* CLK_M4_GPIO configuration register */
135#define CCU1_CLK_M4_GPIO_CFG MMIO32(CCU1_BASE + 0x410)
136
137/* CLK_M4_GPIO status register */
138#define CCU1_CLK_M4_GPIO_STAT MMIO32(CCU1_BASE + 0x414)
139
140/* CLK_M4_LCD configuration register */
141#define CCU1_CLK_M4_LCD_CFG MMIO32(CCU1_BASE + 0x418)
142
143/* CLK_M4_LCD status register */
144#define CCU1_CLK_M4_LCD_STAT MMIO32(CCU1_BASE + 0x41C)
145
146/* CLK_M4_ETHERNET configuration register */
147#define CCU1_CLK_M4_ETHERNET_CFG MMIO32(CCU1_BASE + 0x420)
148
149/* CLK_M4_ETHERNET status register */
150#define CCU1_CLK_M4_ETHERNET_STAT MMIO32(CCU1_BASE + 0x424)
151
152/* CLK_M4_USB0 configuration register */
153#define CCU1_CLK_M4_USB0_CFG MMIO32(CCU1_BASE + 0x428)
154
155/* CLK_M4_USB0 status register */
156#define CCU1_CLK_M4_USB0_STAT MMIO32(CCU1_BASE + 0x42C)
157
158/* CLK_M4_EMC configuration register */
159#define CCU1_CLK_M4_EMC_CFG MMIO32(CCU1_BASE + 0x430)
160
161/* CLK_M4_EMC status register */
162#define CCU1_CLK_M4_EMC_STAT MMIO32(CCU1_BASE + 0x434)
163
164/* CLK_M4_SDIO configuration register */
165#define CCU1_CLK_M4_SDIO_CFG MMIO32(CCU1_BASE + 0x438)
166
167/* CLK_M4_SDIO status register */
168#define CCU1_CLK_M4_SDIO_STAT MMIO32(CCU1_BASE + 0x43C)
169
170/* CLK_M4_DMA configuration register */
171#define CCU1_CLK_M4_DMA_CFG MMIO32(CCU1_BASE + 0x440)
172
173/* CLK_M4_DMA status register */
174#define CCU1_CLK_M4_DMA_STAT MMIO32(CCU1_BASE + 0x444)
175
176/* CLK_M4_M4CORE configuration register */
177#define CCU1_CLK_M4_M4CORE_CFG MMIO32(CCU1_BASE + 0x448)
178
179/* CLK_M4_M4CORE status register */
180#define CCU1_CLK_M4_M4CORE_STAT MMIO32(CCU1_BASE + 0x44C)
181
182/* CLK_M4_SCT configuration register */
183#define CCU1_CLK_M4_SCT_CFG MMIO32(CCU1_BASE + 0x468)
184
185/* CLK_M4_SCT status register */
186#define CCU1_CLK_M4_SCT_STAT MMIO32(CCU1_BASE + 0x46C)
187
188/* CLK_M4_USB1 configuration register */
189#define CCU1_CLK_M4_USB1_CFG MMIO32(CCU1_BASE + 0x470)
190
191/* CLK_M4_USB1 status register */
192#define CCU1_CLK_M4_USB1_STAT MMIO32(CCU1_BASE + 0x474)
193
194/* CLK_M4_EMCDIV configuration register */
195#define CCU1_CLK_M4_EMCDIV_CFG MMIO32(CCU1_BASE + 0x478)
196
197/* CLK_M4_EMCDIV status register */
198#define CCU1_CLK_M4_EMCDIV_STAT MMIO32(CCU1_BASE + 0x47C)
199
200/* CLK_M4_M0_CFG configuration register */
201#define CCU1_CLK_M4_M0APP_CFG MMIO32(CCU1_BASE + 0x490)
202
203/* CLK_M4_M0_STAT status register */
204#define CCU1_CLK_M4_M0APP_STAT MMIO32(CCU1_BASE + 0x494)
205
206/* CLK_M4_VADC_CFG configuration register */
207#define CCU1_CLK_M4_VADC_CFG MMIO32(CCU1_BASE + 0x498)
208
209/* CLK_M4_VADC_STAT configuration register */
210#define CCU1_CLK_M4_VADC_STAT MMIO32(CCU1_BASE + 0x49C)
211
212/* CLK_M4_WWDT configuration register */
213#define CCU1_CLK_M4_WWDT_CFG MMIO32(CCU1_BASE + 0x500)
214
215/* CLK_M4_WWDT status register */
216#define CCU1_CLK_M4_WWDT_STAT MMIO32(CCU1_BASE + 0x504)
217
218/* CLK_M4_UART0 configuration register */
219#define CCU1_CLK_M4_USART0_CFG MMIO32(CCU1_BASE + 0x508)
220
221/* CLK_M4_UART0 status register */
222#define CCU1_CLK_M4_USART0_STAT MMIO32(CCU1_BASE + 0x50C)
223
224/* CLK_M4_UART1 configuration register */
225#define CCU1_CLK_M4_UART1_CFG MMIO32(CCU1_BASE + 0x510)
226
227/* CLK_M4_UART1 status register */
228#define CCU1_CLK_M4_UART1_STAT MMIO32(CCU1_BASE + 0x514)
229
230/* CLK_M4_SSP0 configuration register */
231#define CCU1_CLK_M4_SSP0_CFG MMIO32(CCU1_BASE + 0x518)
232
233/* CLK_M4_SSP0 status register */
234#define CCU1_CLK_M4_SSP0_STAT MMIO32(CCU1_BASE + 0x51C)
235
236/* CLK_M4_TIMER0 configuration register */
237#define CCU1_CLK_M4_TIMER0_CFG MMIO32(CCU1_BASE + 0x520)
238
239/* CLK_M4_TIMER0 status register */
240#define CCU1_CLK_M4_TIMER0_STAT MMIO32(CCU1_BASE + 0x524)
241
242/* CLK_M4_TIMER1 configuration register */
243#define CCU1_CLK_M4_TIMER1_CFG MMIO32(CCU1_BASE + 0x528)
244
245/* CLK_M4_TIMER1 status register */
246#define CCU1_CLK_M4_TIMER1_STAT MMIO32(CCU1_BASE + 0x52C)
247
248/* CLK_M4_SCU configuration register */
249#define CCU1_CLK_M4_SCU_CFG MMIO32(CCU1_BASE + 0x530)
250
251/* CLK_M4_SCU status register */
252#define CCU1_CLK_M4_SCU_STAT MMIO32(CCU1_BASE + 0x534)
253
254/* CLK_M4_CREG configuration register */
255#define CCU1_CLK_M4_CREG_CFG MMIO32(CCU1_BASE + 0x538)
256
257/* CLK_M4_CREG status register */
258#define CCU1_CLK_M4_CREG_STAT MMIO32(CCU1_BASE + 0x53C)
259
260/* CLK_M4_RITIMER configuration register */
261#define CCU1_CLK_M4_RITIMER_CFG MMIO32(CCU1_BASE + 0x600)
262
263/* CLK_M4_RITIMER status register */
264#define CCU1_CLK_M4_RITIMER_STAT MMIO32(CCU1_BASE + 0x604)
265
266/* CLK_M4_UART2 configuration register */
267#define CCU1_CLK_M4_USART2_CFG MMIO32(CCU1_BASE + 0x608)
268
269/* CLK_M4_UART2 status register */
270#define CCU1_CLK_M4_USART2_STAT MMIO32(CCU1_BASE + 0x60C)
271
272/* CLK_M4_UART3 configuration register */
273#define CCU1_CLK_M4_USART3_CFG MMIO32(CCU1_BASE + 0x610)
274
275/* CLK_M4_UART3 status register */
276#define CCU1_CLK_M4_USART3_STAT MMIO32(CCU1_BASE + 0x614)
277
278/* CLK_M4_TIMER2 configuration register */
279#define CCU1_CLK_M4_TIMER2_CFG MMIO32(CCU1_BASE + 0x618)
280
281/* CLK_M4_TIMER2 status register */
282#define CCU1_CLK_M4_TIMER2_STAT MMIO32(CCU1_BASE + 0x61C)
283
284/* CLK_M4_TIMER3 configuration register */
285#define CCU1_CLK_M4_TIMER3_CFG MMIO32(CCU1_BASE + 0x620)
286
287/* CLK_M4_TIMER3 status register */
288#define CCU1_CLK_M4_TIMER3_STAT MMIO32(CCU1_BASE + 0x624)
289
290/* CLK_M4_SSP1 configuration register */
291#define CCU1_CLK_M4_SSP1_CFG MMIO32(CCU1_BASE + 0x628)
292
293/* CLK_M4_SSP1 status register */
294#define CCU1_CLK_M4_SSP1_STAT MMIO32(CCU1_BASE + 0x62C)
295
296/* CLK_M4_QEI configuration register */
297#define CCU1_CLK_M4_QEI_CFG MMIO32(CCU1_BASE + 0x630)
298
299/* CLK_M4_QEI status register */
300#define CCU1_CLK_M4_QEI_STAT MMIO32(CCU1_BASE + 0x634)
301
302/* CLK_PERIPH_BUS configuration register */
303#define CCU1_CLK_PERIPH_BUS_CFG MMIO32(CCU1_BASE + 0x700)
304
305/* CLK_PERIPH_BUS status register */
306#define CCU1_CLK_PERIPH_BUS_STAT MMIO32(CCU1_BASE + 0x704)
307
308/* CLK_PERIPH_CORE configuration register */
309#define CCU1_CLK_PERIPH_CORE_CFG MMIO32(CCU1_BASE + 0x710)
310
311/* CLK_PERIPH_CORE status register */
312#define CCU1_CLK_PERIPH_CORE_STAT MMIO32(CCU1_BASE + 0x714)
313
314/* CLK_PERIPH_SGPIO configuration register */
315#define CCU1_CLK_PERIPH_SGPIO_CFG MMIO32(CCU1_BASE + 0x718)
316
317/* CLK_PERIPH_SGPIO status register */
318#define CCU1_CLK_PERIPH_SGPIO_STAT MMIO32(CCU1_BASE + 0x71C)
319
320/* CLK_USB0 configuration register */
321#define CCU1_CLK_USB0_CFG MMIO32(CCU1_BASE + 0x800)
322
323/* CLK_USB0 status register */
324#define CCU1_CLK_USB0_STAT MMIO32(CCU1_BASE + 0x804)
325
326/* CLK_USB1 configuration register */
327#define CCU1_CLK_USB1_CFG MMIO32(CCU1_BASE + 0x900)
328
329/* CLK_USB1 status register */
330#define CCU1_CLK_USB1_STAT MMIO32(CCU1_BASE + 0x904)
331
332/* CLK_SPI configuration register */
333#define CCU1_CLK_SPI_CFG MMIO32(CCU1_BASE + 0xA00)
334
335/* CLK_SPI status register */
336#define CCU1_CLK_SPI_STAT MMIO32(CCU1_BASE + 0xA04)
337
338/* CLK_VADC configuration register */
339#define CCU1_CLK_VADC_CFG MMIO32(CCU1_BASE + 0xB00)
340
341/* CLK_VADC status register */
342#define CCU1_CLK_VADC_STAT MMIO32(CCU1_BASE + 0xB04)
343
344/* --- CCU2 registers ------------------------------------------------------ */
345
346/* CCU2 power mode register */
347#define CCU2_PM MMIO32(CCU2_BASE + 0x000)
348
349/* CCU2 base clocks status register */
350#define CCU2_BASE_STAT MMIO32(CCU2_BASE + 0x004)
351
352/* CLK_APLL configuration register */
353#define CCU2_CLK_APLL_CFG MMIO32(CCU2_BASE + 0x100)
354
355/* CLK_APLL status register */
356#define CCU2_CLK_APLL_STAT MMIO32(CCU2_BASE + 0x104)
357
358/* CLK_APB2_UART3 configuration register */
359#define CCU2_CLK_APB2_USART3_CFG MMIO32(CCU2_BASE + 0x200)
360
361/* CLK_APB2_UART3 status register */
362#define CCU2_CLK_APB2_USART3_STAT MMIO32(CCU2_BASE + 0x204)
363
364/* CLK_APB2_UART2 configuration register */
365#define CCU2_CLK_APB2_USART2_CFG MMIO32(CCU2_BASE + 0x300)
366
367/* CLK_APB2_UART2 status register */
368#define CCU2_CLK_APB2_USART2_STAT MMIO32(CCU2_BASE + 0x304)
369
370/* CLK_APB0_UART1 configuration register */
371#define CCU2_CLK_APB0_UART1_CFG MMIO32(CCU2_BASE + 0x400)
372
373/* CLK_APB0_UART1 status register */
374#define CCU2_CLK_APB0_UART1_STAT MMIO32(CCU2_BASE + 0x404)
375
376/* CLK_APB0_UART0 configuration register */
377#define CCU2_CLK_APB0_USART0_CFG MMIO32(CCU2_BASE + 0x500)
378
379/* CLK_APB0_UART0 status register */
380#define CCU2_CLK_APB0_USART0_STAT MMIO32(CCU2_BASE + 0x504)
381
382/* CLK_APB2_SSP1 configuration register */
383#define CCU2_CLK_APB2_SSP1_CFG MMIO32(CCU2_BASE + 0x600)
384
385/* CLK_APB2_SSP1 status register */
386#define CCU2_CLK_APB2_SSP1_STAT MMIO32(CCU2_BASE + 0x604)
387
388/* CLK_APB0_SSP0 configuration register */
389#define CCU2_CLK_APB0_SSP0_CFG MMIO32(CCU2_BASE + 0x700)
390
391/* CLK_APB0_SSP0 status register */
392#define CCU2_CLK_APB0_SSP0_STAT MMIO32(CCU2_BASE + 0x704)
393
394/* CLK_SDIO configuration register (for SD/MMC) */
395#define CCU2_CLK_SDIO_CFG MMIO32(CCU2_BASE + 0x800)
396
397/* CLK_SDIO status register (for SD/MMC) */
398#define CCU2_CLK_SDIO_STAT MMIO32(CCU2_BASE + 0x804)
399
400/**@}*/
401
402#endif