libopencm3
A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers.
|
Defined Constants and Types for the LPC43xx Reset Generation Unit More...
Defined Constants and Types for the LPC43xx Reset Generation Unit
LGPL License Terms libopencm3 License
#define RESET_ACTIVE_STATUS0_BUS_RST (1 << RESET_ACTIVE_STATUS0_BUS_RST_SHIFT) |
#define RESET_ACTIVE_STATUS0_CORE_RST (1 << RESET_ACTIVE_STATUS0_CORE_RST_SHIFT) |
#define RESET_ACTIVE_STATUS0_CREG_RST (1 << RESET_ACTIVE_STATUS0_CREG_RST_SHIFT) |
#define RESET_ACTIVE_STATUS0_DMA_RST (1 << RESET_ACTIVE_STATUS0_DMA_RST_SHIFT) |
#define RESET_ACTIVE_STATUS0_EEPROM_RST (1 << RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT) |
#define RESET_ACTIVE_STATUS0_EMC_RST (1 << RESET_ACTIVE_STATUS0_EMC_RST_SHIFT) |
#define RESET_ACTIVE_STATUS0_ETHERNET_RST (1 << RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT) |
#define RESET_ACTIVE_STATUS0_FLASHA_RST (1 << RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT) |
#define RESET_ACTIVE_STATUS0_FLASHB_RST (1 << RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT) |
#define RESET_ACTIVE_STATUS0_GPIO_RST (1 << RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT) |
#define RESET_ACTIVE_STATUS0_LCD_RST (1 << RESET_ACTIVE_STATUS0_LCD_RST_SHIFT) |
#define RESET_ACTIVE_STATUS0_M4_RST (1 << RESET_ACTIVE_STATUS0_M4_RST_SHIFT) |
#define RESET_ACTIVE_STATUS0_MASTER_RST (1 << RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT) |
#define RESET_ACTIVE_STATUS0_PERIPH_RST (1 << RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT) |
#define RESET_ACTIVE_STATUS0_SCU_RST (1 << RESET_ACTIVE_STATUS0_SCU_RST_SHIFT) |
#define RESET_ACTIVE_STATUS0_SDIO_RST (1 << RESET_ACTIVE_STATUS0_SDIO_RST_SHIFT) |
#define RESET_ACTIVE_STATUS0_USB0_RST (1 << RESET_ACTIVE_STATUS0_USB0_RST_SHIFT) |
#define RESET_ACTIVE_STATUS0_USB1_RST (1 << RESET_ACTIVE_STATUS0_USB1_RST_SHIFT) |
#define RESET_ACTIVE_STATUS0_WWDT_RST (1 << RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_ADC0_RST (1 << RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_ADC1_RST (1 << RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_CAN0_RST (1 << RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_CAN1_RST (1 << RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_DAC_RST (1 << RESET_ACTIVE_STATUS1_DAC_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_I2C0_RST (1 << RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_I2C1_RST (1 << RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_I2S_RST (1 << RESET_ACTIVE_STATUS1_I2S_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_M0APP_RST (1 << RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_MOTOCONPWM_RST (1 << RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_QEI_RST (1 << RESET_ACTIVE_STATUS1_QEI_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_RITIMER_RST (1 << RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_SCT_RST (1 << RESET_ACTIVE_STATUS1_SCT_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_SGPIO_RST (1 << RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_SPI_RST (1 << RESET_ACTIVE_STATUS1_SPI_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_SPIFI_RST (1 << RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_SSP0_RST (1 << RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_SSP1_RST (1 << RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_TIMER0_RST (1 << RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_TIMER1_RST (1 << RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_TIMER2_RST (1 << RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_TIMER3_RST (1 << RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_UART0_RST (1 << RESET_ACTIVE_STATUS1_UART0_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_UART1_RST (1 << RESET_ACTIVE_STATUS1_UART1_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_UART2_RST (1 << RESET_ACTIVE_STATUS1_UART2_RST_SHIFT) |
#define RESET_ACTIVE_STATUS1_UART3_RST (1 << RESET_ACTIVE_STATUS1_UART3_RST_SHIFT) |
#define RESET_CTRL0_BUS_RST (1 << RESET_CTRL0_BUS_RST_SHIFT) |
#define RESET_CTRL0_CORE_RST (1 << RESET_CTRL0_CORE_RST_SHIFT) |
#define RESET_CTRL0_CREG_RST (1 << RESET_CTRL0_CREG_RST_SHIFT) |
#define RESET_CTRL0_DMA_RST (1 << RESET_CTRL0_DMA_RST_SHIFT) |
#define RESET_CTRL0_EEPROM_RST (1 << RESET_CTRL0_EEPROM_RST_SHIFT) |
#define RESET_CTRL0_EMC_RST (1 << RESET_CTRL0_EMC_RST_SHIFT) |
#define RESET_CTRL0_ETHERNET_RST (1 << RESET_CTRL0_ETHERNET_RST_SHIFT) |
#define RESET_CTRL0_FLASHA_RST (1 << RESET_CTRL0_FLASHA_RST_SHIFT) |
#define RESET_CTRL0_FLASHB_RST (1 << RESET_CTRL0_FLASHB_RST_SHIFT) |
#define RESET_CTRL0_GPIO_RST (1 << RESET_CTRL0_GPIO_RST_SHIFT) |
#define RESET_CTRL0_LCD_RST (1 << RESET_CTRL0_LCD_RST_SHIFT) |
#define RESET_CTRL0_M4_RST (1 << RESET_CTRL0_M4_RST_SHIFT) |
#define RESET_CTRL0_MASTER_RST (1 << RESET_CTRL0_MASTER_RST_SHIFT) |
#define RESET_CTRL0_PERIPH_RST (1 << RESET_CTRL0_PERIPH_RST_SHIFT) |
#define RESET_CTRL0_SCU_RST (1 << RESET_CTRL0_SCU_RST_SHIFT) |
#define RESET_CTRL0_SDIO_RST (1 << RESET_CTRL0_SDIO_RST_SHIFT) |
#define RESET_CTRL0_USB0_RST (1 << RESET_CTRL0_USB0_RST_SHIFT) |
#define RESET_CTRL0_USB1_RST (1 << RESET_CTRL0_USB1_RST_SHIFT) |
#define RESET_CTRL0_WWDT_RST (1 << RESET_CTRL0_WWDT_RST_SHIFT) |
#define RESET_CTRL1_ADC0_RST (1 << RESET_CTRL1_ADC0_RST_SHIFT) |
#define RESET_CTRL1_ADC1_RST (1 << RESET_CTRL1_ADC1_RST_SHIFT) |
#define RESET_CTRL1_CAN0_RST (1 << RESET_CTRL1_CAN0_RST_SHIFT) |
#define RESET_CTRL1_CAN1_RST (1 << RESET_CTRL1_CAN1_RST_SHIFT) |
#define RESET_CTRL1_DAC_RST (1 << RESET_CTRL1_DAC_RST_SHIFT) |
#define RESET_CTRL1_I2C0_RST (1 << RESET_CTRL1_I2C0_RST_SHIFT) |
#define RESET_CTRL1_I2C1_RST (1 << RESET_CTRL1_I2C1_RST_SHIFT) |
#define RESET_CTRL1_I2S_RST (1 << RESET_CTRL1_I2S_RST_SHIFT) |
#define RESET_CTRL1_M0APP_RST (1 << RESET_CTRL1_M0APP_RST_SHIFT) |
#define RESET_CTRL1_MOTOCONPWM_RST (1 << RESET_CTRL1_MOTOCONPWM_RST_SHIFT) |
#define RESET_CTRL1_QEI_RST (1 << RESET_CTRL1_QEI_RST_SHIFT) |
#define RESET_CTRL1_RTIMER_RST (1 << RESET_CTRL1_RTIMER_RST_SHIFT) |
#define RESET_CTRL1_SCT_RST (1 << RESET_CTRL1_SCT_RST_SHIFT) |
#define RESET_CTRL1_SGPIO_RST (1 << RESET_CTRL1_SGPIO_RST_SHIFT) |
#define RESET_CTRL1_SPI_RST (1 << RESET_CTRL1_SPI_RST_SHIFT) |
#define RESET_CTRL1_SPIFI_RST (1 << RESET_CTRL1_SPIFI_RST_SHIFT) |
#define RESET_CTRL1_SSP0_RST (1 << RESET_CTRL1_SSP0_RST_SHIFT) |
#define RESET_CTRL1_SSP1_RST (1 << RESET_CTRL1_SSP1_RST_SHIFT) |
#define RESET_CTRL1_TIMER0_RST (1 << RESET_CTRL1_TIMER0_RST_SHIFT) |
#define RESET_CTRL1_TIMER1_RST (1 << RESET_CTRL1_TIMER1_RST_SHIFT) |
#define RESET_CTRL1_TIMER2_RST (1 << RESET_CTRL1_TIMER2_RST_SHIFT) |
#define RESET_CTRL1_TIMER3_RST (1 << RESET_CTRL1_TIMER3_RST_SHIFT) |
#define RESET_CTRL1_UART0_RST (1 << RESET_CTRL1_UART0_RST_SHIFT) |
#define RESET_CTRL1_UART1_RST (1 << RESET_CTRL1_UART1_RST_SHIFT) |
#define RESET_CTRL1_UART2_RST (1 << RESET_CTRL1_UART2_RST_SHIFT) |
#define RESET_CTRL1_UART3_RST (1 << RESET_CTRL1_UART3_RST_SHIFT) |
#define RESET_EXT_STAT0_BOD_RESET (1 << RESET_EXT_STAT0_BOD_RESET_SHIFT) |
#define RESET_EXT_STAT0_EXT_RESET (1 << RESET_EXT_STAT0_EXT_RESET_SHIFT) |
#define RESET_EXT_STAT0_WWDT_RESET (1 << RESET_EXT_STAT0_WWDT_RESET_SHIFT) |
#define RESET_EXT_STAT13_MASTER_RESET (1 << RESET_EXT_STAT13_MASTER_RESET_SHIFT) |
#define RESET_EXT_STAT16_MASTER_RESET (1 << RESET_EXT_STAT16_MASTER_RESET_SHIFT) |
#define RESET_EXT_STAT17_MASTER_RESET (1 << RESET_EXT_STAT17_MASTER_RESET_SHIFT) |
#define RESET_EXT_STAT18_MASTER_RESET (1 << RESET_EXT_STAT18_MASTER_RESET_SHIFT) |
#define RESET_EXT_STAT19_MASTER_RESET (1 << RESET_EXT_STAT19_MASTER_RESET_SHIFT) |
#define RESET_EXT_STAT1_CORE_RESET (1 << RESET_EXT_STAT1_CORE_RESET_SHIFT) |
#define RESET_EXT_STAT20_MASTER_RESET (1 << RESET_EXT_STAT20_MASTER_RESET_SHIFT) |
#define RESET_EXT_STAT21_MASTER_RESET (1 << RESET_EXT_STAT21_MASTER_RESET_SHIFT) |
#define RESET_EXT_STAT22_MASTER_RESET (1 << RESET_EXT_STAT22_MASTER_RESET_SHIFT) |
#define RESET_EXT_STAT25_PERIPHERAL_RESET (1 << RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT27_PERIPHERAL_RESET (1 << RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT28_PERIPHERAL_RESET (1 << RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT29_PERIPHERAL_RESET (1 << RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT2_PERIPHERAL_RESET (1 << RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT32_PERIPHERAL_RESET (1 << RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT33_PERIPHERAL_RESET (1 << RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT34_PERIPHERAL_RESET (1 << RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT35_PERIPHERAL_RESET (1 << RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT36_PERIPHERAL_RESET (1 << RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT37_PERIPHERAL_RESET (1 << RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT38_PERIPHERAL_RESET (1 << RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT39_PERIPHERAL_RESET (1 << RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT40_PERIPHERAL_RESET (1 << RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT41_PERIPHERAL_RESET (1 << RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT42_PERIPHERAL_RESET (1 << RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT44_PERIPHERAL_RESET (1 << RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT45_PERIPHERAL_RESET (1 << RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT46_PERIPHERAL_RESET (1 << RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT47_PERIPHERAL_RESET (1 << RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT48_PERIPHERAL_RESET (1 << RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT49_PERIPHERAL_RESET (1 << RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT4_CORE_RESET (1 << RESET_EXT_STAT4_CORE_RESET_SHIFT) |
#define RESET_EXT_STAT50_PERIPHERAL_RESET (1 << RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT51_PERIPHERAL_RESET (1 << RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT52_PERIPHERAL_RESET (1 << RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT53_PERIPHERAL_RESET (1 << RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT54_PERIPHERAL_RESET (1 << RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT55_PERIPHERAL_RESET (1 << RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT56_PERIPHERAL_RESET (1 << RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT57_PERIPHERAL_RESET (1 << RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT58_PERIPHERAL_RESET (1 << RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT5_CORE_RESET (1 << RESET_EXT_STAT5_CORE_RESET_SHIFT) |
#define RESET_EXT_STAT8_PERIPHERAL_RESET (1 << RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT) |
#define RESET_EXT_STAT9_PERIPHERAL_RESET (1 << RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT) |
#define RESET_STATUS0_BUS_RST | ( | x | ) | ((x) << RESET_STATUS0_BUS_RST_SHIFT) |
#define RESET_STATUS0_BUS_RST_MASK (0x3 << RESET_STATUS0_BUS_RST_SHIFT) |
#define RESET_STATUS0_CORE_RST | ( | x | ) | ((x) << RESET_STATUS0_CORE_RST_SHIFT) |
#define RESET_STATUS0_CORE_RST_MASK (0x3 << RESET_STATUS0_CORE_RST_SHIFT) |
#define RESET_STATUS0_CREG_RST | ( | x | ) | ((x) << RESET_STATUS0_CREG_RST_SHIFT) |
#define RESET_STATUS0_CREG_RST_MASK (0x3 << RESET_STATUS0_CREG_RST_SHIFT) |
#define RESET_STATUS0_M4_RST | ( | x | ) | ((x) << RESET_STATUS0_M4_RST_SHIFT) |
#define RESET_STATUS0_M4_RST_MASK (0x3 << RESET_STATUS0_M4_RST_SHIFT) |
#define RESET_STATUS0_MASTER_RST | ( | x | ) | ((x) << RESET_STATUS0_MASTER_RST_SHIFT) |
#define RESET_STATUS0_MASTER_RST_MASK (0x3 << RESET_STATUS0_MASTER_RST_SHIFT) |
#define RESET_STATUS0_PERIPH_RST | ( | x | ) | ((x) << RESET_STATUS0_PERIPH_RST_SHIFT) |
#define RESET_STATUS0_PERIPH_RST_MASK (0x3 << RESET_STATUS0_PERIPH_RST_SHIFT) |
#define RESET_STATUS0_SCU_RST | ( | x | ) | ((x) << RESET_STATUS0_SCU_RST_SHIFT) |
#define RESET_STATUS0_SCU_RST_MASK (0x3 << RESET_STATUS0_SCU_RST_SHIFT) |
#define RESET_STATUS0_WWDT_RST | ( | x | ) | ((x) << RESET_STATUS0_WWDT_RST_SHIFT) |
#define RESET_STATUS0_WWDT_RST_MASK (0x3 << RESET_STATUS0_WWDT_RST_SHIFT) |
#define RESET_STATUS1_DMA_RST | ( | x | ) | ((x) << RESET_STATUS1_DMA_RST_SHIFT) |
#define RESET_STATUS1_DMA_RST_MASK (0x3 << RESET_STATUS1_DMA_RST_SHIFT) |
#define RESET_STATUS1_EEPROM_RST | ( | x | ) | ((x) << RESET_STATUS1_EEPROM_RST_SHIFT) |
#define RESET_STATUS1_EEPROM_RST_MASK (0x3 << RESET_STATUS1_EEPROM_RST_SHIFT) |
#define RESET_STATUS1_EMC_RST | ( | x | ) | ((x) << RESET_STATUS1_EMC_RST_SHIFT) |
#define RESET_STATUS1_EMC_RST_MASK (0x3 << RESET_STATUS1_EMC_RST_SHIFT) |
#define RESET_STATUS1_ETHERNET_RST | ( | x | ) | ((x) << RESET_STATUS1_ETHERNET_RST_SHIFT) |
#define RESET_STATUS1_ETHERNET_RST_MASK (0x3 << RESET_STATUS1_ETHERNET_RST_SHIFT) |
#define RESET_STATUS1_FLASHA_RST | ( | x | ) | ((x) << RESET_STATUS1_FLASHA_RST_SHIFT) |
#define RESET_STATUS1_FLASHA_RST_MASK (0x3 << RESET_STATUS1_FLASHA_RST_SHIFT) |
#define RESET_STATUS1_FLASHB_RST | ( | x | ) | ((x) << RESET_STATUS1_FLASHB_RST_SHIFT) |
#define RESET_STATUS1_FLASHB_RST_MASK (0x3 << RESET_STATUS1_FLASHB_RST_SHIFT) |
#define RESET_STATUS1_GPIO_RST | ( | x | ) | ((x) << RESET_STATUS1_GPIO_RST_SHIFT) |
#define RESET_STATUS1_GPIO_RST_MASK (0x3 << RESET_STATUS1_GPIO_RST_SHIFT) |
#define RESET_STATUS1_LCD_RST | ( | x | ) | ((x) << RESET_STATUS1_LCD_RST_SHIFT) |
#define RESET_STATUS1_LCD_RST_MASK (0x3 << RESET_STATUS1_LCD_RST_SHIFT) |
#define RESET_STATUS1_SDIO_RST | ( | x | ) | ((x) << RESET_STATUS1_SDIO_RST_SHIFT) |
#define RESET_STATUS1_SDIO_RST_MASK (0x3 << RESET_STATUS1_SDIO_RST_SHIFT) |
#define RESET_STATUS1_USB0_RST | ( | x | ) | ((x) << RESET_STATUS1_USB0_RST_SHIFT) |
#define RESET_STATUS1_USB0_RST_MASK (0x3 << RESET_STATUS1_USB0_RST_SHIFT) |
#define RESET_STATUS1_USB1_RST | ( | x | ) | ((x) << RESET_STATUS1_USB1_RST_SHIFT) |
#define RESET_STATUS1_USB1_RST_MASK (0x3 << RESET_STATUS1_USB1_RST_SHIFT) |
#define RESET_STATUS2_ADC0_RST | ( | x | ) | ((x) << RESET_STATUS2_ADC0_RST_SHIFT) |
#define RESET_STATUS2_ADC0_RST_MASK (0x3 << RESET_STATUS2_ADC0_RST_SHIFT) |
#define RESET_STATUS2_ADC1_RST | ( | x | ) | ((x) << RESET_STATUS2_ADC1_RST_SHIFT) |
#define RESET_STATUS2_ADC1_RST_MASK (0x3 << RESET_STATUS2_ADC1_RST_SHIFT) |
#define RESET_STATUS2_DAC_RST | ( | x | ) | ((x) << RESET_STATUS2_DAC_RST_SHIFT) |
#define RESET_STATUS2_DAC_RST_MASK (0x3 << RESET_STATUS2_DAC_RST_SHIFT) |
#define RESET_STATUS2_MOTOCONPWM_RST | ( | x | ) | ((x) << RESET_STATUS2_MOTOCONPWM_RST_SHIFT) |
#define RESET_STATUS2_MOTOCONPWM_RST_MASK (0x3 << RESET_STATUS2_MOTOCONPWM_RST_SHIFT) |
#define RESET_STATUS2_QEI_RST | ( | x | ) | ((x) << RESET_STATUS2_QEI_RST_SHIFT) |
#define RESET_STATUS2_QEI_RST_MASK (0x3 << RESET_STATUS2_QEI_RST_SHIFT) |
#define RESET_STATUS2_RITIMER_RST | ( | x | ) | ((x) << RESET_STATUS2_RITIMER_RST_SHIFT) |
#define RESET_STATUS2_RITIMER_RST_MASK (0x3 << RESET_STATUS2_RITIMER_RST_SHIFT) |
#define RESET_STATUS2_SCT_RST | ( | x | ) | ((x) << RESET_STATUS2_SCT_RST_SHIFT) |
#define RESET_STATUS2_SCT_RST_MASK (0x3 << RESET_STATUS2_SCT_RST_SHIFT) |
#define RESET_STATUS2_TIMER0_RST | ( | x | ) | ((x) << RESET_STATUS2_TIMER0_RST_SHIFT) |
#define RESET_STATUS2_TIMER0_RST_MASK (0x3 << RESET_STATUS2_TIMER0_RST_SHIFT) |
#define RESET_STATUS2_TIMER1_RST | ( | x | ) | ((x) << RESET_STATUS2_TIMER1_RST_SHIFT) |
#define RESET_STATUS2_TIMER1_RST_MASK (0x3 << RESET_STATUS2_TIMER1_RST_SHIFT) |
#define RESET_STATUS2_TIMER2_RST | ( | x | ) | ((x) << RESET_STATUS2_TIMER2_RST_SHIFT) |
#define RESET_STATUS2_TIMER2_RST_MASK (0x3 << RESET_STATUS2_TIMER2_RST_SHIFT) |
#define RESET_STATUS2_TIMER3_RST | ( | x | ) | ((x) << RESET_STATUS2_TIMER3_RST_SHIFT) |
#define RESET_STATUS2_TIMER3_RST_MASK (0x3 << RESET_STATUS2_TIMER3_RST_SHIFT) |
#define RESET_STATUS2_UART0_RST | ( | x | ) | ((x) << RESET_STATUS2_UART0_RST_SHIFT) |
#define RESET_STATUS2_UART0_RST_MASK (0x3 << RESET_STATUS2_UART0_RST_SHIFT) |
#define RESET_STATUS2_UART1_RST | ( | x | ) | ((x) << RESET_STATUS2_UART1_RST_SHIFT) |
#define RESET_STATUS2_UART1_RST_MASK (0x3 << RESET_STATUS2_UART1_RST_SHIFT) |
#define RESET_STATUS2_UART2_RST | ( | x | ) | ((x) << RESET_STATUS2_UART2_RST_SHIFT) |
#define RESET_STATUS2_UART2_RST_MASK (0x3 << RESET_STATUS2_UART2_RST_SHIFT) |
#define RESET_STATUS2_UART3_RST | ( | x | ) | ((x) << RESET_STATUS2_UART3_RST_SHIFT) |
#define RESET_STATUS2_UART3_RST_MASK (0x3 << RESET_STATUS2_UART3_RST_SHIFT) |
#define RESET_STATUS3_CAN0_RST | ( | x | ) | ((x) << RESET_STATUS3_CAN0_RST_SHIFT) |
#define RESET_STATUS3_CAN0_RST_MASK (0x3 << RESET_STATUS3_CAN0_RST_SHIFT) |
#define RESET_STATUS3_CAN1_RST | ( | x | ) | ((x) << RESET_STATUS3_CAN1_RST_SHIFT) |
#define RESET_STATUS3_CAN1_RST_MASK (0x3 << RESET_STATUS3_CAN1_RST_SHIFT) |
#define RESET_STATUS3_I2C0_RST | ( | x | ) | ((x) << RESET_STATUS3_I2C0_RST_SHIFT) |
#define RESET_STATUS3_I2C0_RST_MASK (0x3 << RESET_STATUS3_I2C0_RST_SHIFT) |
#define RESET_STATUS3_I2C1_RST | ( | x | ) | ((x) << RESET_STATUS3_I2C1_RST_SHIFT) |
#define RESET_STATUS3_I2C1_RST_MASK (0x3 << RESET_STATUS3_I2C1_RST_SHIFT) |
#define RESET_STATUS3_I2S_RST | ( | x | ) | ((x) << RESET_STATUS3_I2S_RST_SHIFT) |
#define RESET_STATUS3_I2S_RST_MASK (0x3 << RESET_STATUS3_I2S_RST_SHIFT) |
#define RESET_STATUS3_M0APP_RST | ( | x | ) | ((x) << RESET_STATUS3_M0APP_RST_SHIFT) |
#define RESET_STATUS3_M0APP_RST_MASK (0x3 << RESET_STATUS3_M0APP_RST_SHIFT) |
#define RESET_STATUS3_SGPIO_RST | ( | x | ) | ((x) << RESET_STATUS3_SGPIO_RST_SHIFT) |
#define RESET_STATUS3_SGPIO_RST_MASK (0x3 << RESET_STATUS3_SGPIO_RST_SHIFT) |
#define RESET_STATUS3_SPI_RST | ( | x | ) | ((x) << RESET_STATUS3_SPI_RST_SHIFT) |
#define RESET_STATUS3_SPI_RST_MASK (0x3 << RESET_STATUS3_SPI_RST_SHIFT) |
#define RESET_STATUS3_SPIFI_RST | ( | x | ) | ((x) << RESET_STATUS3_SPIFI_RST_SHIFT) |
#define RESET_STATUS3_SPIFI_RST_MASK (0x3 << RESET_STATUS3_SPIFI_RST_SHIFT) |
#define RESET_STATUS3_SSP0_RST | ( | x | ) | ((x) << RESET_STATUS3_SSP0_RST_SHIFT) |
#define RESET_STATUS3_SSP0_RST_MASK (0x3 << RESET_STATUS3_SSP0_RST_SHIFT) |
#define RESET_STATUS3_SSP1_RST | ( | x | ) | ((x) << RESET_STATUS3_SSP1_RST_SHIFT) |
#define RESET_STATUS3_SSP1_RST_MASK (0x3 << RESET_STATUS3_SSP1_RST_SHIFT) |