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#define | RESET_CTRL0 MMIO32(RGU_BASE + 0x100) |
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#define | RESET_CTRL1 MMIO32(RGU_BASE + 0x104) |
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#define | RESET_STATUS0 MMIO32(RGU_BASE + 0x110) |
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#define | RESET_STATUS1 MMIO32(RGU_BASE + 0x114) |
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#define | RESET_STATUS2 MMIO32(RGU_BASE + 0x118) |
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#define | RESET_STATUS3 MMIO32(RGU_BASE + 0x11C) |
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#define | RESET_ACTIVE_STATUS0 MMIO32(RGU_BASE + 0x150) |
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#define | RESET_ACTIVE_STATUS1 MMIO32(RGU_BASE + 0x154) |
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#define | RESET_EXT_STAT0 MMIO32(RGU_BASE + 0x400) |
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#define | RESET_EXT_STAT1 MMIO32(RGU_BASE + 0x404) |
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#define | RESET_EXT_STAT2 MMIO32(RGU_BASE + 0x408) |
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#define | RESET_EXT_STAT3 MMIO32(RGU_BASE + 0x40C) |
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#define | RESET_EXT_STAT4 MMIO32(RGU_BASE + 0x410) |
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#define | RESET_EXT_STAT5 MMIO32(RGU_BASE + 0x414) |
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#define | RESET_EXT_STAT6 MMIO32(RGU_BASE + 0x418) |
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#define | RESET_EXT_STAT7 MMIO32(RGU_BASE + 0x41C) |
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#define | RESET_EXT_STAT8 MMIO32(RGU_BASE + 0x420) |
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#define | RESET_EXT_STAT9 MMIO32(RGU_BASE + 0x424) |
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#define | RESET_EXT_STAT10 MMIO32(RGU_BASE + 0x428) |
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#define | RESET_EXT_STAT11 MMIO32(RGU_BASE + 0x42C) |
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#define | RESET_EXT_STAT12 MMIO32(RGU_BASE + 0x430) |
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#define | RESET_EXT_STAT13 MMIO32(RGU_BASE + 0x434) |
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#define | RESET_EXT_STAT14 MMIO32(RGU_BASE + 0x438) |
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#define | RESET_EXT_STAT15 MMIO32(RGU_BASE + 0x43C) |
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#define | RESET_EXT_STAT16 MMIO32(RGU_BASE + 0x440) |
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#define | RESET_EXT_STAT17 MMIO32(RGU_BASE + 0x444) |
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#define | RESET_EXT_STAT18 MMIO32(RGU_BASE + 0x448) |
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#define | RESET_EXT_STAT19 MMIO32(RGU_BASE + 0x44C) |
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#define | RESET_EXT_STAT20 MMIO32(RGU_BASE + 0x450) |
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#define | RESET_EXT_STAT21 MMIO32(RGU_BASE + 0x454) |
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#define | RESET_EXT_STAT22 MMIO32(RGU_BASE + 0x458) |
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#define | RESET_EXT_STAT23 MMIO32(RGU_BASE + 0x45C) |
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#define | RESET_EXT_STAT24 MMIO32(RGU_BASE + 0x460) |
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#define | RESET_EXT_STAT25 MMIO32(RGU_BASE + 0x464) |
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#define | RESET_EXT_STAT26 MMIO32(RGU_BASE + 0x468) |
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#define | RESET_EXT_STAT27 MMIO32(RGU_BASE + 0x46C) |
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#define | RESET_EXT_STAT28 MMIO32(RGU_BASE + 0x470) |
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#define | RESET_EXT_STAT29 MMIO32(RGU_BASE + 0x474) |
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#define | RESET_EXT_STAT30 MMIO32(RGU_BASE + 0x478) |
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#define | RESET_EXT_STAT31 MMIO32(RGU_BASE + 0x47C) |
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#define | RESET_EXT_STAT32 MMIO32(RGU_BASE + 0x480) |
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#define | RESET_EXT_STAT33 MMIO32(RGU_BASE + 0x484) |
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#define | RESET_EXT_STAT34 MMIO32(RGU_BASE + 0x488) |
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#define | RESET_EXT_STAT35 MMIO32(RGU_BASE + 0x48C) |
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#define | RESET_EXT_STAT36 MMIO32(RGU_BASE + 0x490) |
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#define | RESET_EXT_STAT37 MMIO32(RGU_BASE + 0x494) |
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#define | RESET_EXT_STAT38 MMIO32(RGU_BASE + 0x498) |
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#define | RESET_EXT_STAT39 MMIO32(RGU_BASE + 0x49C) |
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#define | RESET_EXT_STAT40 MMIO32(RGU_BASE + 0x4A0) |
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#define | RESET_EXT_STAT41 MMIO32(RGU_BASE + 0x4A4) |
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#define | RESET_EXT_STAT42 MMIO32(RGU_BASE + 0x4A8) |
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#define | RESET_EXT_STAT43 MMIO32(RGU_BASE + 0x4AC) |
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#define | RESET_EXT_STAT44 MMIO32(RGU_BASE + 0x4B0) |
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#define | RESET_EXT_STAT45 MMIO32(RGU_BASE + 0x4B4) |
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#define | RESET_EXT_STAT46 MMIO32(RGU_BASE + 0x4B8) |
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#define | RESET_EXT_STAT47 MMIO32(RGU_BASE + 0x4BC) |
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#define | RESET_EXT_STAT48 MMIO32(RGU_BASE + 0x4C0) |
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#define | RESET_EXT_STAT49 MMIO32(RGU_BASE + 0x4C4) |
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#define | RESET_EXT_STAT50 MMIO32(RGU_BASE + 0x4C8) |
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#define | RESET_EXT_STAT51 MMIO32(RGU_BASE + 0x4CC) |
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#define | RESET_EXT_STAT52 MMIO32(RGU_BASE + 0x4D0) |
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#define | RESET_EXT_STAT53 MMIO32(RGU_BASE + 0x4D4) |
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#define | RESET_EXT_STAT54 MMIO32(RGU_BASE + 0x4D8) |
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#define | RESET_EXT_STAT55 MMIO32(RGU_BASE + 0x4DC) |
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#define | RESET_EXT_STAT56 MMIO32(RGU_BASE + 0x4E0) |
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#define | RESET_EXT_STAT57 MMIO32(RGU_BASE + 0x4E4) |
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#define | RESET_EXT_STAT58 MMIO32(RGU_BASE + 0x4E8) |
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#define | RESET_EXT_STAT59 MMIO32(RGU_BASE + 0x4EC) |
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#define | RESET_EXT_STAT60 MMIO32(RGU_BASE + 0x4F0) |
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#define | RESET_EXT_STAT61 MMIO32(RGU_BASE + 0x4F4) |
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#define | RESET_EXT_STAT62 MMIO32(RGU_BASE + 0x4F8) |
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#define | RESET_EXT_STAT63 MMIO32(RGU_BASE + 0x4FC) |
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#define | RESET_CTRL0_CORE_RST_SHIFT (0) |
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#define | RESET_CTRL0_CORE_RST (1 << RESET_CTRL0_CORE_RST_SHIFT) |
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#define | RESET_CTRL0_PERIPH_RST_SHIFT (1) |
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#define | RESET_CTRL0_PERIPH_RST (1 << RESET_CTRL0_PERIPH_RST_SHIFT) |
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#define | RESET_CTRL0_MASTER_RST_SHIFT (2) |
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#define | RESET_CTRL0_MASTER_RST (1 << RESET_CTRL0_MASTER_RST_SHIFT) |
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#define | RESET_CTRL0_WWDT_RST_SHIFT (4) |
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#define | RESET_CTRL0_WWDT_RST (1 << RESET_CTRL0_WWDT_RST_SHIFT) |
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#define | RESET_CTRL0_CREG_RST_SHIFT (5) |
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#define | RESET_CTRL0_CREG_RST (1 << RESET_CTRL0_CREG_RST_SHIFT) |
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#define | RESET_CTRL0_BUS_RST_SHIFT (8) |
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#define | RESET_CTRL0_BUS_RST (1 << RESET_CTRL0_BUS_RST_SHIFT) |
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#define | RESET_CTRL0_SCU_RST_SHIFT (9) |
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#define | RESET_CTRL0_SCU_RST (1 << RESET_CTRL0_SCU_RST_SHIFT) |
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#define | RESET_CTRL0_M4_RST_SHIFT (13) |
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#define | RESET_CTRL0_M4_RST (1 << RESET_CTRL0_M4_RST_SHIFT) |
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#define | RESET_CTRL0_LCD_RST_SHIFT (16) |
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#define | RESET_CTRL0_LCD_RST (1 << RESET_CTRL0_LCD_RST_SHIFT) |
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#define | RESET_CTRL0_USB0_RST_SHIFT (17) |
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#define | RESET_CTRL0_USB0_RST (1 << RESET_CTRL0_USB0_RST_SHIFT) |
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#define | RESET_CTRL0_USB1_RST_SHIFT (18) |
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#define | RESET_CTRL0_USB1_RST (1 << RESET_CTRL0_USB1_RST_SHIFT) |
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#define | RESET_CTRL0_DMA_RST_SHIFT (19) |
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#define | RESET_CTRL0_DMA_RST (1 << RESET_CTRL0_DMA_RST_SHIFT) |
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#define | RESET_CTRL0_SDIO_RST_SHIFT (20) |
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#define | RESET_CTRL0_SDIO_RST (1 << RESET_CTRL0_SDIO_RST_SHIFT) |
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#define | RESET_CTRL0_EMC_RST_SHIFT (21) |
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#define | RESET_CTRL0_EMC_RST (1 << RESET_CTRL0_EMC_RST_SHIFT) |
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#define | RESET_CTRL0_ETHERNET_RST_SHIFT (22) |
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#define | RESET_CTRL0_ETHERNET_RST (1 << RESET_CTRL0_ETHERNET_RST_SHIFT) |
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#define | RESET_CTRL0_FLASHA_RST_SHIFT (25) |
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#define | RESET_CTRL0_FLASHA_RST (1 << RESET_CTRL0_FLASHA_RST_SHIFT) |
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#define | RESET_CTRL0_EEPROM_RST_SHIFT (27) |
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#define | RESET_CTRL0_EEPROM_RST (1 << RESET_CTRL0_EEPROM_RST_SHIFT) |
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#define | RESET_CTRL0_GPIO_RST_SHIFT (28) |
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#define | RESET_CTRL0_GPIO_RST (1 << RESET_CTRL0_GPIO_RST_SHIFT) |
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#define | RESET_CTRL0_FLASHB_RST_SHIFT (29) |
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#define | RESET_CTRL0_FLASHB_RST (1 << RESET_CTRL0_FLASHB_RST_SHIFT) |
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#define | RESET_CTRL1_TIMER0_RST_SHIFT (0) |
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#define | RESET_CTRL1_TIMER0_RST (1 << RESET_CTRL1_TIMER0_RST_SHIFT) |
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#define | RESET_CTRL1_TIMER1_RST_SHIFT (1) |
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#define | RESET_CTRL1_TIMER1_RST (1 << RESET_CTRL1_TIMER1_RST_SHIFT) |
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#define | RESET_CTRL1_TIMER2_RST_SHIFT (2) |
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#define | RESET_CTRL1_TIMER2_RST (1 << RESET_CTRL1_TIMER2_RST_SHIFT) |
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#define | RESET_CTRL1_TIMER3_RST_SHIFT (3) |
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#define | RESET_CTRL1_TIMER3_RST (1 << RESET_CTRL1_TIMER3_RST_SHIFT) |
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#define | RESET_CTRL1_RTIMER_RST_SHIFT (4) |
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#define | RESET_CTRL1_RTIMER_RST (1 << RESET_CTRL1_RTIMER_RST_SHIFT) |
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#define | RESET_CTRL1_SCT_RST_SHIFT (5) |
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#define | RESET_CTRL1_SCT_RST (1 << RESET_CTRL1_SCT_RST_SHIFT) |
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#define | RESET_CTRL1_MOTOCONPWM_RST_SHIFT (6) |
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#define | RESET_CTRL1_MOTOCONPWM_RST (1 << RESET_CTRL1_MOTOCONPWM_RST_SHIFT) |
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#define | RESET_CTRL1_QEI_RST_SHIFT (7) |
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#define | RESET_CTRL1_QEI_RST (1 << RESET_CTRL1_QEI_RST_SHIFT) |
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#define | RESET_CTRL1_ADC0_RST_SHIFT (8) |
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#define | RESET_CTRL1_ADC0_RST (1 << RESET_CTRL1_ADC0_RST_SHIFT) |
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#define | RESET_CTRL1_ADC1_RST_SHIFT (9) |
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#define | RESET_CTRL1_ADC1_RST (1 << RESET_CTRL1_ADC1_RST_SHIFT) |
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#define | RESET_CTRL1_DAC_RST_SHIFT (10) |
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#define | RESET_CTRL1_DAC_RST (1 << RESET_CTRL1_DAC_RST_SHIFT) |
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#define | RESET_CTRL1_UART0_RST_SHIFT (12) |
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#define | RESET_CTRL1_UART0_RST (1 << RESET_CTRL1_UART0_RST_SHIFT) |
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#define | RESET_CTRL1_UART1_RST_SHIFT (13) |
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#define | RESET_CTRL1_UART1_RST (1 << RESET_CTRL1_UART1_RST_SHIFT) |
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#define | RESET_CTRL1_UART2_RST_SHIFT (14) |
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#define | RESET_CTRL1_UART2_RST (1 << RESET_CTRL1_UART2_RST_SHIFT) |
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#define | RESET_CTRL1_UART3_RST_SHIFT (15) |
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#define | RESET_CTRL1_UART3_RST (1 << RESET_CTRL1_UART3_RST_SHIFT) |
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#define | RESET_CTRL1_I2C0_RST_SHIFT (16) |
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#define | RESET_CTRL1_I2C0_RST (1 << RESET_CTRL1_I2C0_RST_SHIFT) |
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#define | RESET_CTRL1_I2C1_RST_SHIFT (17) |
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#define | RESET_CTRL1_I2C1_RST (1 << RESET_CTRL1_I2C1_RST_SHIFT) |
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#define | RESET_CTRL1_SSP0_RST_SHIFT (18) |
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#define | RESET_CTRL1_SSP0_RST (1 << RESET_CTRL1_SSP0_RST_SHIFT) |
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#define | RESET_CTRL1_SSP1_RST_SHIFT (19) |
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#define | RESET_CTRL1_SSP1_RST (1 << RESET_CTRL1_SSP1_RST_SHIFT) |
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#define | RESET_CTRL1_I2S_RST_SHIFT (20) |
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#define | RESET_CTRL1_I2S_RST (1 << RESET_CTRL1_I2S_RST_SHIFT) |
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#define | RESET_CTRL1_SPIFI_RST_SHIFT (21) |
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#define | RESET_CTRL1_SPIFI_RST (1 << RESET_CTRL1_SPIFI_RST_SHIFT) |
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#define | RESET_CTRL1_CAN1_RST_SHIFT (22) |
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#define | RESET_CTRL1_CAN1_RST (1 << RESET_CTRL1_CAN1_RST_SHIFT) |
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#define | RESET_CTRL1_CAN0_RST_SHIFT (23) |
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#define | RESET_CTRL1_CAN0_RST (1 << RESET_CTRL1_CAN0_RST_SHIFT) |
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#define | RESET_CTRL1_M0APP_RST_SHIFT (24) |
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#define | RESET_CTRL1_M0APP_RST (1 << RESET_CTRL1_M0APP_RST_SHIFT) |
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#define | RESET_CTRL1_SGPIO_RST_SHIFT (25) |
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#define | RESET_CTRL1_SGPIO_RST (1 << RESET_CTRL1_SGPIO_RST_SHIFT) |
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#define | RESET_CTRL1_SPI_RST_SHIFT (26) |
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#define | RESET_CTRL1_SPI_RST (1 << RESET_CTRL1_SPI_RST_SHIFT) |
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#define | RESET_STATUS0_CORE_RST_SHIFT (0) |
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#define | RESET_STATUS0_CORE_RST_MASK (0x3 << RESET_STATUS0_CORE_RST_SHIFT) |
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#define | RESET_STATUS0_CORE_RST(x) ((x) << RESET_STATUS0_CORE_RST_SHIFT) |
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#define | RESET_STATUS0_PERIPH_RST_SHIFT (2) |
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#define | RESET_STATUS0_PERIPH_RST_MASK (0x3 << RESET_STATUS0_PERIPH_RST_SHIFT) |
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#define | RESET_STATUS0_PERIPH_RST(x) ((x) << RESET_STATUS0_PERIPH_RST_SHIFT) |
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#define | RESET_STATUS0_MASTER_RST_SHIFT (4) |
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#define | RESET_STATUS0_MASTER_RST_MASK (0x3 << RESET_STATUS0_MASTER_RST_SHIFT) |
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#define | RESET_STATUS0_MASTER_RST(x) ((x) << RESET_STATUS0_MASTER_RST_SHIFT) |
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#define | RESET_STATUS0_WWDT_RST_SHIFT (8) |
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#define | RESET_STATUS0_WWDT_RST_MASK (0x3 << RESET_STATUS0_WWDT_RST_SHIFT) |
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#define | RESET_STATUS0_WWDT_RST(x) ((x) << RESET_STATUS0_WWDT_RST_SHIFT) |
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#define | RESET_STATUS0_CREG_RST_SHIFT (10) |
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#define | RESET_STATUS0_CREG_RST_MASK (0x3 << RESET_STATUS0_CREG_RST_SHIFT) |
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#define | RESET_STATUS0_CREG_RST(x) ((x) << RESET_STATUS0_CREG_RST_SHIFT) |
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#define | RESET_STATUS0_BUS_RST_SHIFT (16) |
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#define | RESET_STATUS0_BUS_RST_MASK (0x3 << RESET_STATUS0_BUS_RST_SHIFT) |
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#define | RESET_STATUS0_BUS_RST(x) ((x) << RESET_STATUS0_BUS_RST_SHIFT) |
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#define | RESET_STATUS0_SCU_RST_SHIFT (18) |
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#define | RESET_STATUS0_SCU_RST_MASK (0x3 << RESET_STATUS0_SCU_RST_SHIFT) |
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#define | RESET_STATUS0_SCU_RST(x) ((x) << RESET_STATUS0_SCU_RST_SHIFT) |
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#define | RESET_STATUS0_M4_RST_SHIFT (26) |
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#define | RESET_STATUS0_M4_RST_MASK (0x3 << RESET_STATUS0_M4_RST_SHIFT) |
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#define | RESET_STATUS0_M4_RST(x) ((x) << RESET_STATUS0_M4_RST_SHIFT) |
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#define | RESET_STATUS1_LCD_RST_SHIFT (0) |
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#define | RESET_STATUS1_LCD_RST_MASK (0x3 << RESET_STATUS1_LCD_RST_SHIFT) |
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#define | RESET_STATUS1_LCD_RST(x) ((x) << RESET_STATUS1_LCD_RST_SHIFT) |
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#define | RESET_STATUS1_USB0_RST_SHIFT (2) |
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#define | RESET_STATUS1_USB0_RST_MASK (0x3 << RESET_STATUS1_USB0_RST_SHIFT) |
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#define | RESET_STATUS1_USB0_RST(x) ((x) << RESET_STATUS1_USB0_RST_SHIFT) |
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#define | RESET_STATUS1_USB1_RST_SHIFT (4) |
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#define | RESET_STATUS1_USB1_RST_MASK (0x3 << RESET_STATUS1_USB1_RST_SHIFT) |
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#define | RESET_STATUS1_USB1_RST(x) ((x) << RESET_STATUS1_USB1_RST_SHIFT) |
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#define | RESET_STATUS1_DMA_RST_SHIFT (6) |
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#define | RESET_STATUS1_DMA_RST_MASK (0x3 << RESET_STATUS1_DMA_RST_SHIFT) |
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#define | RESET_STATUS1_DMA_RST(x) ((x) << RESET_STATUS1_DMA_RST_SHIFT) |
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#define | RESET_STATUS1_SDIO_RST_SHIFT (8) |
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#define | RESET_STATUS1_SDIO_RST_MASK (0x3 << RESET_STATUS1_SDIO_RST_SHIFT) |
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#define | RESET_STATUS1_SDIO_RST(x) ((x) << RESET_STATUS1_SDIO_RST_SHIFT) |
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#define | RESET_STATUS1_EMC_RST_SHIFT (10) |
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#define | RESET_STATUS1_EMC_RST_MASK (0x3 << RESET_STATUS1_EMC_RST_SHIFT) |
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#define | RESET_STATUS1_EMC_RST(x) ((x) << RESET_STATUS1_EMC_RST_SHIFT) |
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#define | RESET_STATUS1_ETHERNET_RST_SHIFT (12) |
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#define | RESET_STATUS1_ETHERNET_RST_MASK (0x3 << RESET_STATUS1_ETHERNET_RST_SHIFT) |
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#define | RESET_STATUS1_ETHERNET_RST(x) ((x) << RESET_STATUS1_ETHERNET_RST_SHIFT) |
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#define | RESET_STATUS1_FLASHA_RST_SHIFT (18) |
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#define | RESET_STATUS1_FLASHA_RST_MASK (0x3 << RESET_STATUS1_FLASHA_RST_SHIFT) |
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#define | RESET_STATUS1_FLASHA_RST(x) ((x) << RESET_STATUS1_FLASHA_RST_SHIFT) |
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#define | RESET_STATUS1_EEPROM_RST_SHIFT (22) |
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#define | RESET_STATUS1_EEPROM_RST_MASK (0x3 << RESET_STATUS1_EEPROM_RST_SHIFT) |
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#define | RESET_STATUS1_EEPROM_RST(x) ((x) << RESET_STATUS1_EEPROM_RST_SHIFT) |
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#define | RESET_STATUS1_GPIO_RST_SHIFT (24) |
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#define | RESET_STATUS1_GPIO_RST_MASK (0x3 << RESET_STATUS1_GPIO_RST_SHIFT) |
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#define | RESET_STATUS1_GPIO_RST(x) ((x) << RESET_STATUS1_GPIO_RST_SHIFT) |
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#define | RESET_STATUS1_FLASHB_RST_SHIFT (26) |
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#define | RESET_STATUS1_FLASHB_RST_MASK (0x3 << RESET_STATUS1_FLASHB_RST_SHIFT) |
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#define | RESET_STATUS1_FLASHB_RST(x) ((x) << RESET_STATUS1_FLASHB_RST_SHIFT) |
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#define | RESET_STATUS2_TIMER0_RST_SHIFT (0) |
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#define | RESET_STATUS2_TIMER0_RST_MASK (0x3 << RESET_STATUS2_TIMER0_RST_SHIFT) |
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#define | RESET_STATUS2_TIMER0_RST(x) ((x) << RESET_STATUS2_TIMER0_RST_SHIFT) |
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#define | RESET_STATUS2_TIMER1_RST_SHIFT (2) |
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#define | RESET_STATUS2_TIMER1_RST_MASK (0x3 << RESET_STATUS2_TIMER1_RST_SHIFT) |
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#define | RESET_STATUS2_TIMER1_RST(x) ((x) << RESET_STATUS2_TIMER1_RST_SHIFT) |
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#define | RESET_STATUS2_TIMER2_RST_SHIFT (4) |
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#define | RESET_STATUS2_TIMER2_RST_MASK (0x3 << RESET_STATUS2_TIMER2_RST_SHIFT) |
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#define | RESET_STATUS2_TIMER2_RST(x) ((x) << RESET_STATUS2_TIMER2_RST_SHIFT) |
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#define | RESET_STATUS2_TIMER3_RST_SHIFT (6) |
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#define | RESET_STATUS2_TIMER3_RST_MASK (0x3 << RESET_STATUS2_TIMER3_RST_SHIFT) |
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#define | RESET_STATUS2_TIMER3_RST(x) ((x) << RESET_STATUS2_TIMER3_RST_SHIFT) |
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#define | RESET_STATUS2_RITIMER_RST_SHIFT (8) |
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#define | RESET_STATUS2_RITIMER_RST_MASK (0x3 << RESET_STATUS2_RITIMER_RST_SHIFT) |
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#define | RESET_STATUS2_RITIMER_RST(x) ((x) << RESET_STATUS2_RITIMER_RST_SHIFT) |
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#define | RESET_STATUS2_SCT_RST_SHIFT (10) |
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#define | RESET_STATUS2_SCT_RST_MASK (0x3 << RESET_STATUS2_SCT_RST_SHIFT) |
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#define | RESET_STATUS2_SCT_RST(x) ((x) << RESET_STATUS2_SCT_RST_SHIFT) |
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#define | RESET_STATUS2_MOTOCONPWM_RST_SHIFT (12) |
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#define | RESET_STATUS2_MOTOCONPWM_RST_MASK (0x3 << RESET_STATUS2_MOTOCONPWM_RST_SHIFT) |
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#define | RESET_STATUS2_MOTOCONPWM_RST(x) ((x) << RESET_STATUS2_MOTOCONPWM_RST_SHIFT) |
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#define | RESET_STATUS2_QEI_RST_SHIFT (14) |
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#define | RESET_STATUS2_QEI_RST_MASK (0x3 << RESET_STATUS2_QEI_RST_SHIFT) |
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#define | RESET_STATUS2_QEI_RST(x) ((x) << RESET_STATUS2_QEI_RST_SHIFT) |
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#define | RESET_STATUS2_ADC0_RST_SHIFT (16) |
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#define | RESET_STATUS2_ADC0_RST_MASK (0x3 << RESET_STATUS2_ADC0_RST_SHIFT) |
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#define | RESET_STATUS2_ADC0_RST(x) ((x) << RESET_STATUS2_ADC0_RST_SHIFT) |
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#define | RESET_STATUS2_ADC1_RST_SHIFT (18) |
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#define | RESET_STATUS2_ADC1_RST_MASK (0x3 << RESET_STATUS2_ADC1_RST_SHIFT) |
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#define | RESET_STATUS2_ADC1_RST(x) ((x) << RESET_STATUS2_ADC1_RST_SHIFT) |
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#define | RESET_STATUS2_DAC_RST_SHIFT (20) |
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#define | RESET_STATUS2_DAC_RST_MASK (0x3 << RESET_STATUS2_DAC_RST_SHIFT) |
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#define | RESET_STATUS2_DAC_RST(x) ((x) << RESET_STATUS2_DAC_RST_SHIFT) |
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#define | RESET_STATUS2_UART0_RST_SHIFT (24) |
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#define | RESET_STATUS2_UART0_RST_MASK (0x3 << RESET_STATUS2_UART0_RST_SHIFT) |
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#define | RESET_STATUS2_UART0_RST(x) ((x) << RESET_STATUS2_UART0_RST_SHIFT) |
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#define | RESET_STATUS2_UART1_RST_SHIFT (26) |
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#define | RESET_STATUS2_UART1_RST_MASK (0x3 << RESET_STATUS2_UART1_RST_SHIFT) |
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#define | RESET_STATUS2_UART1_RST(x) ((x) << RESET_STATUS2_UART1_RST_SHIFT) |
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#define | RESET_STATUS2_UART2_RST_SHIFT (28) |
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#define | RESET_STATUS2_UART2_RST_MASK (0x3 << RESET_STATUS2_UART2_RST_SHIFT) |
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#define | RESET_STATUS2_UART2_RST(x) ((x) << RESET_STATUS2_UART2_RST_SHIFT) |
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#define | RESET_STATUS2_UART3_RST_SHIFT (30) |
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#define | RESET_STATUS2_UART3_RST_MASK (0x3 << RESET_STATUS2_UART3_RST_SHIFT) |
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#define | RESET_STATUS2_UART3_RST(x) ((x) << RESET_STATUS2_UART3_RST_SHIFT) |
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#define | RESET_STATUS3_I2C0_RST_SHIFT (0) |
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#define | RESET_STATUS3_I2C0_RST_MASK (0x3 << RESET_STATUS3_I2C0_RST_SHIFT) |
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#define | RESET_STATUS3_I2C0_RST(x) ((x) << RESET_STATUS3_I2C0_RST_SHIFT) |
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#define | RESET_STATUS3_I2C1_RST_SHIFT (2) |
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#define | RESET_STATUS3_I2C1_RST_MASK (0x3 << RESET_STATUS3_I2C1_RST_SHIFT) |
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#define | RESET_STATUS3_I2C1_RST(x) ((x) << RESET_STATUS3_I2C1_RST_SHIFT) |
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#define | RESET_STATUS3_SSP0_RST_SHIFT (4) |
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#define | RESET_STATUS3_SSP0_RST_MASK (0x3 << RESET_STATUS3_SSP0_RST_SHIFT) |
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#define | RESET_STATUS3_SSP0_RST(x) ((x) << RESET_STATUS3_SSP0_RST_SHIFT) |
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#define | RESET_STATUS3_SSP1_RST_SHIFT (6) |
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#define | RESET_STATUS3_SSP1_RST_MASK (0x3 << RESET_STATUS3_SSP1_RST_SHIFT) |
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#define | RESET_STATUS3_SSP1_RST(x) ((x) << RESET_STATUS3_SSP1_RST_SHIFT) |
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#define | RESET_STATUS3_I2S_RST_SHIFT (8) |
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#define | RESET_STATUS3_I2S_RST_MASK (0x3 << RESET_STATUS3_I2S_RST_SHIFT) |
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#define | RESET_STATUS3_I2S_RST(x) ((x) << RESET_STATUS3_I2S_RST_SHIFT) |
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#define | RESET_STATUS3_SPIFI_RST_SHIFT (10) |
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#define | RESET_STATUS3_SPIFI_RST_MASK (0x3 << RESET_STATUS3_SPIFI_RST_SHIFT) |
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#define | RESET_STATUS3_SPIFI_RST(x) ((x) << RESET_STATUS3_SPIFI_RST_SHIFT) |
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#define | RESET_STATUS3_CAN1_RST_SHIFT (12) |
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#define | RESET_STATUS3_CAN1_RST_MASK (0x3 << RESET_STATUS3_CAN1_RST_SHIFT) |
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#define | RESET_STATUS3_CAN1_RST(x) ((x) << RESET_STATUS3_CAN1_RST_SHIFT) |
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#define | RESET_STATUS3_CAN0_RST_SHIFT (14) |
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#define | RESET_STATUS3_CAN0_RST_MASK (0x3 << RESET_STATUS3_CAN0_RST_SHIFT) |
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#define | RESET_STATUS3_CAN0_RST(x) ((x) << RESET_STATUS3_CAN0_RST_SHIFT) |
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#define | RESET_STATUS3_M0APP_RST_SHIFT (16) |
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#define | RESET_STATUS3_M0APP_RST_MASK (0x3 << RESET_STATUS3_M0APP_RST_SHIFT) |
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#define | RESET_STATUS3_M0APP_RST(x) ((x) << RESET_STATUS3_M0APP_RST_SHIFT) |
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#define | RESET_STATUS3_SGPIO_RST_SHIFT (18) |
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#define | RESET_STATUS3_SGPIO_RST_MASK (0x3 << RESET_STATUS3_SGPIO_RST_SHIFT) |
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#define | RESET_STATUS3_SGPIO_RST(x) ((x) << RESET_STATUS3_SGPIO_RST_SHIFT) |
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#define | RESET_STATUS3_SPI_RST_SHIFT (20) |
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#define | RESET_STATUS3_SPI_RST_MASK (0x3 << RESET_STATUS3_SPI_RST_SHIFT) |
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#define | RESET_STATUS3_SPI_RST(x) ((x) << RESET_STATUS3_SPI_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS0_CORE_RST_SHIFT (0) |
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#define | RESET_ACTIVE_STATUS0_CORE_RST (1 << RESET_ACTIVE_STATUS0_CORE_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT (1) |
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#define | RESET_ACTIVE_STATUS0_PERIPH_RST (1 << RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT (2) |
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#define | RESET_ACTIVE_STATUS0_MASTER_RST (1 << RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT (4) |
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#define | RESET_ACTIVE_STATUS0_WWDT_RST (1 << RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS0_CREG_RST_SHIFT (5) |
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#define | RESET_ACTIVE_STATUS0_CREG_RST (1 << RESET_ACTIVE_STATUS0_CREG_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS0_BUS_RST_SHIFT (8) |
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#define | RESET_ACTIVE_STATUS0_BUS_RST (1 << RESET_ACTIVE_STATUS0_BUS_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS0_SCU_RST_SHIFT (9) |
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#define | RESET_ACTIVE_STATUS0_SCU_RST (1 << RESET_ACTIVE_STATUS0_SCU_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS0_M4_RST_SHIFT (13) |
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#define | RESET_ACTIVE_STATUS0_M4_RST (1 << RESET_ACTIVE_STATUS0_M4_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS0_LCD_RST_SHIFT (16) |
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#define | RESET_ACTIVE_STATUS0_LCD_RST (1 << RESET_ACTIVE_STATUS0_LCD_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS0_USB0_RST_SHIFT (17) |
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#define | RESET_ACTIVE_STATUS0_USB0_RST (1 << RESET_ACTIVE_STATUS0_USB0_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS0_USB1_RST_SHIFT (18) |
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#define | RESET_ACTIVE_STATUS0_USB1_RST (1 << RESET_ACTIVE_STATUS0_USB1_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS0_DMA_RST_SHIFT (19) |
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#define | RESET_ACTIVE_STATUS0_DMA_RST (1 << RESET_ACTIVE_STATUS0_DMA_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS0_SDIO_RST_SHIFT (20) |
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#define | RESET_ACTIVE_STATUS0_SDIO_RST (1 << RESET_ACTIVE_STATUS0_SDIO_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS0_EMC_RST_SHIFT (21) |
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#define | RESET_ACTIVE_STATUS0_EMC_RST (1 << RESET_ACTIVE_STATUS0_EMC_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT (22) |
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#define | RESET_ACTIVE_STATUS0_ETHERNET_RST (1 << RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT (25) |
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#define | RESET_ACTIVE_STATUS0_FLASHA_RST (1 << RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT (27) |
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#define | RESET_ACTIVE_STATUS0_EEPROM_RST (1 << RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT (28) |
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#define | RESET_ACTIVE_STATUS0_GPIO_RST (1 << RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT (29) |
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#define | RESET_ACTIVE_STATUS0_FLASHB_RST (1 << RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT (0) |
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#define | RESET_ACTIVE_STATUS1_TIMER0_RST (1 << RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT (1) |
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#define | RESET_ACTIVE_STATUS1_TIMER1_RST (1 << RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT (2) |
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#define | RESET_ACTIVE_STATUS1_TIMER2_RST (1 << RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT (3) |
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#define | RESET_ACTIVE_STATUS1_TIMER3_RST (1 << RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT (4) |
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#define | RESET_ACTIVE_STATUS1_RITIMER_RST (1 << RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_SCT_RST_SHIFT (5) |
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#define | RESET_ACTIVE_STATUS1_SCT_RST (1 << RESET_ACTIVE_STATUS1_SCT_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT (6) |
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#define | RESET_ACTIVE_STATUS1_MOTOCONPWM_RST (1 << RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_QEI_RST_SHIFT (7) |
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#define | RESET_ACTIVE_STATUS1_QEI_RST (1 << RESET_ACTIVE_STATUS1_QEI_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT (8) |
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#define | RESET_ACTIVE_STATUS1_ADC0_RST (1 << RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT (9) |
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#define | RESET_ACTIVE_STATUS1_ADC1_RST (1 << RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_DAC_RST_SHIFT (10) |
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#define | RESET_ACTIVE_STATUS1_DAC_RST (1 << RESET_ACTIVE_STATUS1_DAC_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_UART0_RST_SHIFT (12) |
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#define | RESET_ACTIVE_STATUS1_UART0_RST (1 << RESET_ACTIVE_STATUS1_UART0_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_UART1_RST_SHIFT (13) |
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#define | RESET_ACTIVE_STATUS1_UART1_RST (1 << RESET_ACTIVE_STATUS1_UART1_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_UART2_RST_SHIFT (14) |
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#define | RESET_ACTIVE_STATUS1_UART2_RST (1 << RESET_ACTIVE_STATUS1_UART2_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_UART3_RST_SHIFT (15) |
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#define | RESET_ACTIVE_STATUS1_UART3_RST (1 << RESET_ACTIVE_STATUS1_UART3_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT (16) |
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#define | RESET_ACTIVE_STATUS1_I2C0_RST (1 << RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT (17) |
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#define | RESET_ACTIVE_STATUS1_I2C1_RST (1 << RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT (18) |
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#define | RESET_ACTIVE_STATUS1_SSP0_RST (1 << RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT (19) |
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#define | RESET_ACTIVE_STATUS1_SSP1_RST (1 << RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_I2S_RST_SHIFT (20) |
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#define | RESET_ACTIVE_STATUS1_I2S_RST (1 << RESET_ACTIVE_STATUS1_I2S_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT (21) |
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#define | RESET_ACTIVE_STATUS1_SPIFI_RST (1 << RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT (22) |
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#define | RESET_ACTIVE_STATUS1_CAN1_RST (1 << RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT (23) |
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#define | RESET_ACTIVE_STATUS1_CAN0_RST (1 << RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT (24) |
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#define | RESET_ACTIVE_STATUS1_M0APP_RST (1 << RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT (25) |
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#define | RESET_ACTIVE_STATUS1_SGPIO_RST (1 << RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT) |
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#define | RESET_ACTIVE_STATUS1_SPI_RST_SHIFT (26) |
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#define | RESET_ACTIVE_STATUS1_SPI_RST (1 << RESET_ACTIVE_STATUS1_SPI_RST_SHIFT) |
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#define | RESET_EXT_STAT0_EXT_RESET_SHIFT (0) |
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#define | RESET_EXT_STAT0_EXT_RESET (1 << RESET_EXT_STAT0_EXT_RESET_SHIFT) |
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#define | RESET_EXT_STAT0_BOD_RESET_SHIFT (4) |
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#define | RESET_EXT_STAT0_BOD_RESET (1 << RESET_EXT_STAT0_BOD_RESET_SHIFT) |
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#define | RESET_EXT_STAT0_WWDT_RESET_SHIFT (5) |
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#define | RESET_EXT_STAT0_WWDT_RESET (1 << RESET_EXT_STAT0_WWDT_RESET_SHIFT) |
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#define | RESET_EXT_STAT1_CORE_RESET_SHIFT (1) |
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#define | RESET_EXT_STAT1_CORE_RESET (1 << RESET_EXT_STAT1_CORE_RESET_SHIFT) |
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#define | RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT2_PERIPHERAL_RESET (1 << RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT4_CORE_RESET_SHIFT (1) |
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#define | RESET_EXT_STAT4_CORE_RESET (1 << RESET_EXT_STAT4_CORE_RESET_SHIFT) |
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#define | RESET_EXT_STAT5_CORE_RESET_SHIFT (1) |
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#define | RESET_EXT_STAT5_CORE_RESET (1 << RESET_EXT_STAT5_CORE_RESET_SHIFT) |
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#define | RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT8_PERIPHERAL_RESET (1 << RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT9_PERIPHERAL_RESET (1 << RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT13_MASTER_RESET_SHIFT (3) |
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#define | RESET_EXT_STAT13_MASTER_RESET (1 << RESET_EXT_STAT13_MASTER_RESET_SHIFT) |
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#define | RESET_EXT_STAT16_MASTER_RESET_SHIFT (3) |
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#define | RESET_EXT_STAT16_MASTER_RESET (1 << RESET_EXT_STAT16_MASTER_RESET_SHIFT) |
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#define | RESET_EXT_STAT17_MASTER_RESET_SHIFT (3) |
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#define | RESET_EXT_STAT17_MASTER_RESET (1 << RESET_EXT_STAT17_MASTER_RESET_SHIFT) |
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#define | RESET_EXT_STAT18_MASTER_RESET_SHIFT (3) |
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#define | RESET_EXT_STAT18_MASTER_RESET (1 << RESET_EXT_STAT18_MASTER_RESET_SHIFT) |
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#define | RESET_EXT_STAT19_MASTER_RESET_SHIFT (3) |
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#define | RESET_EXT_STAT19_MASTER_RESET (1 << RESET_EXT_STAT19_MASTER_RESET_SHIFT) |
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#define | RESET_EXT_STAT20_MASTER_RESET_SHIFT (3) |
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#define | RESET_EXT_STAT20_MASTER_RESET (1 << RESET_EXT_STAT20_MASTER_RESET_SHIFT) |
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#define | RESET_EXT_STAT21_MASTER_RESET_SHIFT (3) |
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#define | RESET_EXT_STAT21_MASTER_RESET (1 << RESET_EXT_STAT21_MASTER_RESET_SHIFT) |
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#define | RESET_EXT_STAT22_MASTER_RESET_SHIFT (3) |
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#define | RESET_EXT_STAT22_MASTER_RESET (1 << RESET_EXT_STAT22_MASTER_RESET_SHIFT) |
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#define | RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT25_PERIPHERAL_RESET (1 << RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT27_PERIPHERAL_RESET (1 << RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT28_PERIPHERAL_RESET (1 << RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT29_PERIPHERAL_RESET (1 << RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT32_PERIPHERAL_RESET (1 << RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT33_PERIPHERAL_RESET (1 << RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT34_PERIPHERAL_RESET (1 << RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT35_PERIPHERAL_RESET (1 << RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT36_PERIPHERAL_RESET (1 << RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT37_PERIPHERAL_RESET (1 << RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT38_PERIPHERAL_RESET (1 << RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT39_PERIPHERAL_RESET (1 << RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT40_PERIPHERAL_RESET (1 << RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT41_PERIPHERAL_RESET (1 << RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT42_PERIPHERAL_RESET (1 << RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT44_PERIPHERAL_RESET (1 << RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT45_PERIPHERAL_RESET (1 << RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT46_PERIPHERAL_RESET (1 << RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT47_PERIPHERAL_RESET (1 << RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT48_PERIPHERAL_RESET (1 << RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT49_PERIPHERAL_RESET (1 << RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT50_PERIPHERAL_RESET (1 << RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT51_PERIPHERAL_RESET (1 << RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT52_PERIPHERAL_RESET (1 << RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT53_PERIPHERAL_RESET (1 << RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT54_PERIPHERAL_RESET (1 << RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT55_PERIPHERAL_RESET (1 << RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT56_PERIPHERAL_RESET (1 << RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT57_PERIPHERAL_RESET (1 << RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT) |
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#define | RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT (2) |
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#define | RESET_EXT_STAT58_PERIPHERAL_RESET (1 << RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT) |
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